TWI701444B - Sensing circuit - Google Patents

Abstract

The present invention is a sensing circuit that is difficult to enter the test mode by mistake with respect to external input such as noise. The sensing circuit includes a clock generating circuit, which outputs a control signal for controlling intermittent operation to a physical quantity detection unit, and outputs it during a rest period. Sampling signal; potential detection circuit, which detects the potential of the output terminal, and outputs the detection signal; and clock control circuit, when a predetermined signal pattern is detected in the data obtained by sampling the detection signal based on the sampling signal, the output generates the clock The mode switching signal for switching the circuit to the test mode.

Description

Sensing circuit

The present invention relates to a sensor circuit, and particularly relates to a sensor circuit with a test circuit.

In the past, sensing circuits that detect various physical quantities were installed in electronic equipment and used effectively. The sensing circuit is sometimes mounted in a three-terminal package of power terminals, ground terminals, and output terminals. In this way, many sensing circuits mounted in packages with a small number of terminals cannot be provided with dedicated terminals for switching to the test mode. Therefore, in a sensing circuit with a small number of terminals, the output terminal is also used as a test terminal.

The conventional sensing circuit includes: a first inversion part that outputs the potential level of the output signal of the detection part; a second inversion part that inverts the potential level of the output signal of the detection part and outputs it to the output Terminal; and a mode switching circuit, according to the potential level of the first inversion portion and the potential level of the second inversion portion to switch to the test mode. In addition, by forcibly inputting a voltage from the output terminal, the mode switching circuit detects a potential state (the same potential) that is not normally caused and switches to the test mode (for example, refer to Patent Document 1).

Prior art literature Patent literature

Patent Document 1: Japanese Patent Laid-Open No. 2009-31225

However, the magnetic sensing circuit of Patent Document 1 may erroneously switch to the test mode for unexpected external input such as noise superimposed from the output terminal. Moreover, when the load capacity of the output terminal is large, it is also possible that the change of the potential level of the conventional output terminal corresponding to the detection result is delayed, and the test mode may be unexpectedly switched.

The sensing circuit of the present invention includes: a clock generating circuit, which outputs a control signal for controlling intermittent operation to the physical quantity detection part, and outputs a sampling signal during the rest period; a potential detection circuit, which detects the potential of the output terminal, and outputs the detection Signal; and the clock control circuit, when a predetermined signal pattern (Pattern) is detected in the data obtained by sampling the detection signal based on the sampling signal, it outputs a mode switching signal that switches the clock generation circuit to the test mode.

According to the sensing circuit of the present invention, the possibility of erroneous switching to the test mode is low, and stable operation can be realized.

10: Physical quantity detection department

12: Physical quantity detection signal

20: Clock generation circuit

21: Control signal

22: Sampling signal

30: output driver

31: Output terminal

32: Output logic signal

40: Potential detection circuit

41: Potential detection signal

50: Clock control circuit

51: Mode switching signal

60: counter

61: Timeout signal

70: Dead time control circuit

71: Dead time signal

80: reset circuit

81: Reset signal

100, 200, 300, 400: sensing circuit

Bin: Magnetic flux density

BOP, BRP: threshold

V12, V21, V22, V31, V41, V51, V61, V71, V81: voltage

t0~t11: time

FIG. 1 is a block diagram of the sensing circuit of the first embodiment.

Fig. 2 is a timing chart showing the operation of the sensing circuit of the first embodiment.

Fig. 3 is a block diagram of the sensing circuit of the second embodiment.

Fig. 4 is a timing chart showing the operation of the sensing circuit of the second embodiment.

Fig. 5 is a block diagram of a sensing circuit of a third embodiment.

Fig. 6 is a timing chart showing the operation of the sensing circuit of the third embodiment.

Fig. 7 is a block diagram of a sensing circuit of a fourth embodiment.

FIG. 8 is a timing chart showing the operation of the sensing circuit of the fourth embodiment.

Hereinafter, for the sensing circuit of the present invention, a magnetic switch that performs a binary output as a result of comparing the output voltage of the Hall element with the reference voltage is described as an example.

<First Embodiment>

FIG. 1 is a block diagram of a sensing circuit 100 according to the first embodiment.

The sensing circuit 100 of the first embodiment includes a physical quantity detection unit 10, a clock generation circuit 20, an output driver 30, and a potential detection circuit 40 and a clock control circuit 50.

The physical quantity detection unit 10 outputs two physical quantity detection signals 12 with different potential levels according to the applied physical quantity.

The input of the output driver 30 is connected to the output of the physical quantity detection unit 10 and the output is connected to the output terminal 31. The output driver 30 inverts the potential level of the physical quantity detection signal 12 of the physical quantity detection unit 10 and outputs the output logic signal 32 of the sensing circuit 100 to the output terminal 31.

The input of the potential detection circuit 40 is connected to the output terminal 31 and outputs a binary potential detection signal 41 based on the potential of the output terminal 31.

The clock generation circuit 20 outputs a control signal 21 for controlling the detection operation to the physical quantity detection unit 10, and outputs a sampling signal 22 to the clock control circuit 50 during the rest period.

The clock control circuit 50 inputs the potential detection signal 41, the sampling signal 22 and the physical quantity detection signal 12, and outputs the mode switching signal 51 to the clock generation circuit 20.

The physical quantity detection unit 10 is a magnetic switch that detects an S-pole or N-pole magnetic field, and switches the potential level of the physical quantity detection signal 12 according to the magnitude of the magnetic flux density applied from the outside. Furthermore, the physical quantity detection unit 10 performs an intermittent operation having an operation period and a rest period. The operation period is a period during which the physical quantity is detected or cancelled based on the control signal 21, and the rest period is a period when the operating current of the internal circuit is increased. The period of partial blockade.

The clock control circuit 50 samples the potential detection signal 41 in synchronization with the sampling signal 22 and holds the data in a shift register or the like. The clock control circuit 50 switches the mode switching signal 51 to a level corresponding to the test mode when obtaining a predetermined signal pattern (here, LHHL, HLLH) from the potential detection signal 41. Moreover, the clock control circuit 50 switches the mode switching signal 51 to a level corresponding to the normal mode when the physical quantity detection signal 12 changes.

The physical quantity detection unit 10 is configured to perform the following operations, for example.

When the control signal 21 is at the H level, the physical quantity detection unit 10 compares the output voltage of the Hall element with the reference voltage. When the control signal 21 is at the L level, it becomes the rest period. If the applied magnetic flux density is less than the specified The value of Then, the L-level physical quantity detection signal 12 is output, and if it is greater than a predetermined value, the H-level physical quantity detection signal 12 is output.

The output driver 30 uses, for example, a Complementary Metal-Oxide-Semiconductor (CMOS) driver. When the applied physical quantity of the output driver 30 is small, for example, when the input physical quantity detection signal 12 is at the L level, the Nch driver is turned off and the Pch driver is turned on, and outputs the H-level output logic signal 32 to the output terminal 31. When the applied physical quantity is large, for example, when the input physical quantity detection signal 12 is at the H level, the Nch driver is turned on and the Pch driver is turned off, and the L-level output logic signal 32 is output to the output terminal 31.

The potential detection circuit 40 includes, for example, a schmitt trigger circuit, a comparator including a differential pair and a reference voltage circuit, or the like. The potential detection circuit 40 outputs the H-level potential detection signal 41 when the potential of the output terminal 31 is at the H level, and outputs the L-level potential detection signal 41 when the potential of the output terminal 31 is at the L level.

Next, the operation of the sensing circuit 100 of the first embodiment will be described.

FIG. 2 is a timing chart showing the operation of the sensing circuit 100 according to the first embodiment.

In FIG. 2, the magnetic flux density applied to the sensing circuit 100 is set to Bin, the voltage of the physical quantity detection signal 12 is set to V12, the voltage of the output terminal 31 is set to V31, and the voltage of the potential detection signal 41 is set to V41. , The control signal 21 The voltage is set to V21, the voltage of the sampling signal 22 is set to V22, and the voltage of the mode switching signal 51 is set to V51. In addition, the threshold value of the physical quantity detected by the physical quantity detecting unit 10 is set to BOP, and the threshold value to cancel the detection is set to BRP.

To the sensing circuit 100, the magnetic flux density Bin shown in the timing chart is applied. The magnetic flux density Bin is lower than the threshold BRP before time t0, so the physical quantity detection signal 12 is at the L level, and the voltages of the output terminal 31 and the potential detection signal 41 are at the H level.

The sensing circuit 100 is in the rest period of the normal operation before the time t1, the mode switching signal 51 maintains the L level, and the sampling signal 22 is output from the clock generating circuit 20. In the sampled signal 22 before time t1, the clock control circuit 50 continuously maintains the H level of the potential detection signal 41, and therefore maintains the normal operation (the mode switching signal 51 is at the L level). Here, the clock control circuit 50 reads the potential of the potential detection signal 41 at the rising edge of the sampling signal 22.

The period from time t1 to time t2 of the sensing circuit 100 is a normal operation period, and the clock generating circuit 20 sets the control signal 21 to the H level. The physical quantity detection unit 10 detects that the magnetic flux density Bin is higher than the threshold value BOP during the operation period and performs signal processing. When the control signal 21 reaches the L level, the physical quantity detection signal 12 is set to the H level. In response to this, the voltages of the output terminal 31 and the potential detection signal 41 become the L level. In addition, when the sensing circuit 100 is in the rest period in the normal operation again, the mode switching signal 51 maintains the L level, and the sampling signal 22 is output from the clock generating circuit 20.

The clock control circuit 50 reads the L level of the potential detection signal 41 according to the sampling signal 22 at time t3.

Here, when the H level is forcibly input to the output terminal 31 from the outside from time t4 to time t7, the clock control circuit 50 reads the H bit of the potential detection signal 41 based on the sampling signal 22 at time t5 and t6 Furthermore, at time t8, the L level of the potential detection signal 41 is read based on the sampling signal 22.

Therefore, since the input signal pattern is at the LHHL level, the clock control circuit 50 determines that it is a test mode input signal during the period from time t8 to time t9, switches from the normal operation to the test mode, and outputs the H-level mode Switch signal 51.

The sensing circuit 100 maintains the test mode until time t10, and then, when the physical quantity detection unit 10 detects that the magnetic flux density Bin is less than or equal to the release threshold BRP, the physical quantity detection signal 12 changes to the L level. The clock control circuit 50 receives the situation where the physical quantity detection signal 12 changes to the L level, switches from the test mode to the normal operation, and outputs the mode switch signal 51 at the L level.

As described above, the sensing circuit 100 of this embodiment adopts the following structure: during the rest period of the normal operation, a voltage having a predetermined signal pattern is forcibly input to the output terminal 31 from the outside, and the voltage is detected Switch from the normal operation to the test mode, and receive a change in the level of the physical quantity detection signal 12, and switch from the test mode to the normal operation. Therefore, the sensing circuit 100 of the present embodiment has a low possibility of erroneously switching to the test mode, and stable operation can be realized.

In addition, in the timing chart of FIG. 2, it is explained that the magnetic flux density Bin is higher than the detection threshold BOP and the test mode is switched to. The magnetic flux density Bin is lower than the release threshold BRP. In the case of test mode same. At this time, the output terminal 31 can be forcibly set to an L-level potential and the signal pattern is set to HLLH, whereby the clock control circuit 50 determines that it is a test mode input signal and switches from the normal operation to the test mode.

Furthermore, the signal pattern has been described as LHHL or HLLH, but it is not limited to this, and it may be a more complicated signal pattern or a shorter signal pattern.

<Second Embodiment>

FIG. 3 is a block diagram of the sensing circuit 200 of the second embodiment. The sensing circuit 200 of the second embodiment is additionally provided with a counter 60 to the sensing circuit 100 of FIG. 1, and the counter 60 counts a time out time. Furthermore, the clock control circuit 50 in the second embodiment adopts a structure that receives the timeout signal 61 output from the counter 60. The other structure is the same as that of the sensing circuit 100 in FIG. 1, so the same components are denoted by the same reference numerals, and the description is omitted.

The counter 60 inputs the potential detection signal 41 output from the potential detection circuit 40 and outputs a timeout signal 61 to the clock control circuit 50. The clock control circuit 50 masks the sampling signal 22 when receiving the H-level timeout signal 61.

Next, the operation of the sensing circuit 200 of the second embodiment will be described.

FIG. 4 is a timing chart showing the operation of the sensing circuit 200 of the second embodiment.

In FIG. 4, the voltage of the timeout signal 61 is set to V61. In addition, descriptions of the same operations as those in the timing chart of FIG. 2 are omitted.

At time t1, the physical quantity detection signal 12 becomes H level, and the output terminal The voltage of 31 becomes the L level.

At time t2, when noise from the outside is superimposed on the output terminal 31, as shown in the figure, the voltage V31 fluctuates, and the H-level potential detection signal 41 is output. Therefore, the clock control circuit 50 reads the H level of the potential detection signal 41 according to the sampling signal 22.

The counter 60 receives the change in the potential detection signal 41 and starts counting, and when the timeout period is reached at time t3, the timeout signal 61 is changed from the L level to the H level. When the clock control circuit 50 receives the H-level timeout signal 61, it masks the sampling signal 22, and therefore does not read the H-level of the potential detection signal 41 caused by external noise at time t4.

Therefore, the clock control circuit 50 does not recognize the signal pattern after the time t2 as HLLH, so even if there is noise as shown in FIG. 4, it will not switch to the test mode by mistake.

As described above, the sensing circuit of the second embodiment includes the counter 60 that outputs the time-out signal 61, so it is possible to more reliably prevent the erroneous operation of erroneous switching to the test mode.

In addition, the counter 60 may also include a digital circuit using a logic circuit based on a flip-flop, and may also include an analog timing circuit based on a constant current source and a capacitive element. Moreover, the timeout signal 61 only needs to be reset from the H level to the L level according to the control signal 21 at time t5 or t6, for example.

<Third Embodiment>

FIG. 5 is a block diagram of the sensing circuit 300 of the third embodiment. No. 3 The sensing circuit 300 of the embodiment is additionally provided with a dead time control circuit 70 to the sensing circuit 100 of FIG. 1, and the dead time control circuit 70 receives the control signal 21 and outputs a dead time signal 71. Furthermore, the clock control circuit 50 in the third embodiment adopts a structure that receives the dead time signal 71 output by the dead time control circuit 70. The other structure is the same as that of the sensing circuit 100 of FIG.

The dead time control circuit 70 inputs the potential detection signal 41 and outputs the dead time signal 71 to the clock control circuit 50. The clock control circuit 50 masks the sampling signal 22 when receiving the H-level dead time signal 71.

Next, the operation of the sensing circuit 300 of the third embodiment will be described.

FIG. 6 is a timing chart showing the operation of the sensing circuit 300 according to the third embodiment.

In FIG. 6, the voltage of the dead time signal 71 is set to V71. In addition, descriptions of the same operations as those in the timing chart of FIG. 2 are omitted.

At time t1, the physical quantity detection signal 12 becomes the H level, and the output driver 30 sets the output to the L level. Here, when the capacitive load of the output terminal 31 is large, the voltage V31 of the output terminal 31 is stable in accordance with the time constant determined by the capacitive load of the output terminal 31 and the on-resistance of the output driver 30, which takes a relatively long time to stabilize .

The dead time control circuit 70 receives when the control signal 21 becomes the H level, that is, during a predetermined period after the transition to the rest period, it outputs the dead time of the H level Signal 71. The clock control circuit 50 shields the sampling signal 22 and does not perform the sampling operation until the time t3 when the dead time signal 71 maintains the H level. Therefore, the clock control circuit 50 does not read the H level of the potential detection signal 41 from time t1 to time t3.

At time t2, the voltage V31 of the output terminal 31 is lower than the determination threshold value Vth of the potential detection circuit 40, so the potential detection signal 41 becomes the L level. Therefore, the time that the dead time signal 71 maintains the H level only needs to be longer than the time that the voltage V31 is lower than the determination threshold value Vth.

Therefore, even if noise is superimposed on the output terminal 31 at time t4, the clock control circuit 50 will not recognize the signal pattern after time t1 as HLLH, and therefore will not switch to the test mode by mistake.

In this way, the sensing circuit 300 of the third embodiment includes the dead time control circuit 70 that outputs the dead time signal 71 to the clock control circuit 50, and therefore, it is possible to more reliably prevent the erroneous operation of switching to the test mode by mistake.

In addition, the dead time control circuit 70 can also include a logic circuit based on a flip-flop, and can also include a timing circuit based on a constant current source, a capacitive element, and a threshold circuit.

Furthermore, the case where the dead time signal 71 receives the control signal 21 at the H level and outputs the H level has been described. However, any signal can be used as a starting point as long as it conforms to the gist of the invention.

<Fourth Embodiment>

FIG. 7 is a block diagram of the sensing circuit 400 of the fourth embodiment. No. 4 The sensing circuit 400 of the embodiment is additionally provided with a reset circuit 80 in the sensing circuit 100 of FIG. 1, and the reset circuit 80 outputs a reset signal 81. Furthermore, the clock control circuit 50 in the fourth embodiment adopts a structure that receives the reset signal 81 output by the reset circuit 80. The other structure is the same as that of the sensing circuit 100 of FIG.

The reset circuit 80 inputs the potential detection signal 41 and outputs a reset signal 81 to the clock control circuit 50. When receiving the reset signal 81 at the H level, the clock control circuit 50 resets the shift register holding the signal pattern.

Next, the operation of the sensing circuit 400 of the fourth embodiment will be described.

FIG. 8 is a timing chart showing the operation of the sensing circuit 400 of the fourth embodiment.

In FIG. 8, the voltage of the reset signal 81 is set to V81. In addition, descriptions of the same operations as those in the timing chart of FIG. 2 are omitted.

At time t1, the physical quantity detection signal 12 becomes the H level, and the output driver 30 sets the output to the L level. The reset signal 81 is reset to the L level when it becomes the rest period.

At time t2, when noise from the outside is superimposed on the output terminal 31, as shown in the figure, the voltage V31 fluctuates, and the H-level potential detection signal 41 is output. Therefore, the clock control circuit 50 reads the H level of the potential detection signal 41 according to the sampling signal 22.

Here, the reset circuit 80 has a wide range of signals from the potential detection signal 41. The function of detecting the degree. For example, when the width is detected to be small as shown at time t2 in FIG. 8, for example, at time t3, the reset signal 81 at the H level is output to the clock control circuit 50. When receiving the reset signal 81 at the H level, the clock control circuit 50 resets the shift register holding the signal pattern. That is, the H level read into the shift register at time t2 is reset.

Therefore, at time t4, even if noise from the outside is superimposed on the output terminal 31, the clock control circuit 50 does not mistakenly recognize the pattern of the potential detection signal 41 as HLLH.

In this way, the sensing circuit 400 of the fourth embodiment includes the reset circuit 80 that outputs the reset signal 81 to the clock control circuit 50, and therefore, it is possible to more reliably prevent the erroneous operation of switching to the test mode by mistake.

In addition, in FIG. 8, the reset signal 81 becomes the L level when the reception control signal 21 becomes the H level, but for example, it may be set as a one shot pulse.

As described above, the sensing circuit of the present invention includes the clock control circuit 50 that samples the potential detection signal 41 in synchronization with the sampling signal 22, and the clock generation circuit 20 that outputs the sampling signal 22 during the rest period. Practically prevent the erroneous operation of switching to the test mode by mistake.

In addition, in the embodiment, the physical quantity detection unit 10 is described as a magnetic sensing circuit, but as long as the physical quantity detection result is output from the output terminal 31 as a binary signal, it is not limited to this. For example, the physical quantity detection unit 10 may also be a temperature sensing circuit or a light sensing circuit.

Furthermore, the sensing circuit of the present invention is not necessarily limited to the structure or the sensor element, and various changes or combinations can be made without departing from the scope of the invention. For example, the circuits of the respective embodiments may be appropriately combined. Furthermore, it is also possible to adopt a configuration in which a combination of multiple sets of physical quantity detection units 10, output terminals 31, and clock control circuit 50 is provided, a voltage is forcibly applied to each output terminal, and the combination is used to switch to the test mode.

10‧‧‧Physical Quantity Testing Department

12‧‧‧Physical quantity detection signal

20‧‧‧Clock generating circuit

21‧‧‧Control signal

22‧‧‧Sampling signal

30‧‧‧Output Driver

31‧‧‧Output terminal

32‧‧‧Output logic signal

40‧‧‧Potential detection circuit

41‧‧‧potential detection signal

50‧‧‧Clock control circuit

51‧‧‧Mode switching signal

100‧‧‧Sensing circuit

Claims (5)

A sensing circuit that performs intermittent operation with an operation period and a rest period. The sensing circuit is characterized by comprising: a physical quantity detection unit, which outputs two physical quantity detection signals with different potential levels according to the applied physical quantity; an output driver , Receiving the physical quantity detection signal, and outputting a logical signal to an output terminal; a clock generating circuit, outputting a control signal for controlling the intermittent operation to the physical quantity detecting part, and outputting a sampling signal during the rest period; A detection circuit that detects the potential of the output terminal and outputs a detection signal; and a clock control circuit that inputs the sampling signal and the detection signal, and outputs a mode switching signal to the clock generation circuit, and the clock control When a predetermined signal pattern is detected in the data obtained by sampling the detection signal based on the sampling signal, the circuit outputs a mode switching signal for switching the clock generation circuit to a test mode. The sensing circuit according to the first item of the scope of patent application, wherein the clock control circuit further inputs the physical quantity detection signal output by the physical quantity detection unit, and when in the test mode, the physical quantity detection signal When a change occurs, a mode switching signal to switch to the normal mode is output. For example, the sensing circuit described in item 1 or item 2 of the scope of the patent application further includes: a counter, which receives a change in the detection signal and starts counting, and once the timeout period is reached, the clock is controlled The circuit outputs a timeout signal, and the clock control circuit uses the timeout signal to shield the sampling signal. For example, the sensing circuit described in item 1 or item 2 of the scope of the patent application further includes: a dead time control circuit, wherein the dead time control circuit controls the time during the specified period after the transition to the rest period The pulse control circuit outputs a dead time signal, and the clock control circuit masks the sampling signal by the dead time signal. The sensing circuit described in item 1 or item 2 of the scope of the patent application further includes: a reset circuit, the reset circuit outputs a reset circuit to the clock control circuit when the width of the detection signal is detected to be small The reset signal is used by the clock control circuit to mask the sampling signal.

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