KR102303877B1 - Sensor circuit - Google Patents

Abstract

It is a sensor circuit that is not easily input into test mode with respect to external input such as noise, and the sensor circuit includes a clock generator circuit that outputs a control signal for controlling intermittent operation to a physical quantity detection unit and outputs a sampling signal during a rest period; , a potential detection circuit that detects the potential of the output terminal and outputs a detection signal, and a mode switching signal that switches the clock generator circuit to a test mode when a predetermined signal pattern is detected in data sampled based on the sampling signal A clock control circuit for outputting is provided.

Description

sensor circuit {SENSOR CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sensor circuit, and more particularly to a sensor circuit having a test circuit.

Conventionally, sensor circuits for detecting various physical quantities have been installed and utilized in electronic devices. A sensor circuit may be mounted in the package of 3 terminals of a power supply terminal, a ground terminal, and an output terminal. In many cases, the sensor circuit mounted in a package having a small number of terminals cannot form a dedicated terminal for switching to the test mode as described above. For this reason, in a sensor circuit with a small number of terminals, the output terminal is also used as a test terminal.

A conventional sensor circuit includes a first inverting unit for outputting the potential level of the output signal of the detection unit, a second inversion unit for inverting the potential level of the output signal of the detection unit and outputting the potential level to the output terminal, and the potential level of the first inversion unit and A mode switching circuit for switching to the test mode according to the potential level of the second inverting unit is provided. Then, by forcibly inputting a voltage from the output terminal, the mode switching circuit detects a potential state that cannot normally occur (the same potential) and switches to the test mode (see, for example, Patent Document 1). .

Japanese Patent Laid-Open No. 2009-31225

However, the magnetic sensor circuit of Patent Document 1 may be erroneously switched to the test mode with respect to an unintended external input such as noise superimposed from the output terminal. Further, even when the load capacitance of the output terminal is large, the change in the potential level of the normal output terminal according to the detection result is delayed, so that there is a possibility that the test mode is switched unintentionally.

The sensor circuit of the present invention includes a clock generation circuit that outputs a control signal for controlling intermittent operation to a physical quantity detection unit and outputs a sampling signal during a rest period, and a potential detection circuit that detects the potential of an output terminal and outputs a detection signal and a clock control circuit that outputs a mode switching signal for switching the clock generation circuit to a test mode when a predetermined signal pattern is detected in data sampled from the detection signal based on the sampling signal.

According to the sensor circuit of the present invention, the possibility of erroneous switching to the test mode is low, and stable operation is possible.

1 is a block diagram of a sensor circuit of a first embodiment;
Fig. 2 is a timing diagram showing the operation of the sensor circuit of the first embodiment.
Fig. 3 is a block diagram of a sensor circuit of the second embodiment.
Fig. 4 is a timing diagram showing the operation of the sensor circuit of the second embodiment.
Fig. 5 is a block diagram of a sensor circuit according to a third embodiment.
Fig. 6 is a timing diagram showing the operation of the sensor circuit of the third embodiment.
Fig. 7 is a block diagram of a sensor circuit of the fourth embodiment.
Fig. 8 is a timing diagram showing the operation of the sensor circuit of the fourth embodiment.

Hereinafter, with respect to the sensor circuit of the present invention, a magnetic switch that outputs a result of comparing the output voltage of the Hall element with a reference voltage will be described as an example.

<First embodiment>

1 is a block diagram of a sensor circuit 100 according to a first embodiment.

The sensor circuit 100 of the first embodiment includes a physical quantity detection unit 10 , a clock generation circuit 20 , an output driver 30 , a potential detection circuit 40 , and a clock control circuit 50 . has been

The physical quantity detection unit 10 outputs the physical quantity detection signals 12 of two different potential levels in accordance with the applied physical quantity.

The output driver 30 has an input connected to an output of the physical quantity detection unit 10 and an output connected to an output terminal 31 . The output driver 30 inverts the potential level of the physical quantity detection signal 12 of the physical quantity detection unit 10 , and outputs the output logic signal 32 of the sensor circuit 100 to the output terminal 31 .

The potential detection circuit 40 has an input connected to the output terminal 31 , and outputs a binary potential detection signal 41 based on the potential of the output terminal 31 .

The clock generation circuit 20 outputs a control signal 21 for controlling the detection operation to the physical quantity detection unit 10 , and outputs a sampling signal 22 to the clock control circuit 50 in the idle period.

The clock control circuit 50 receives the potential detection signal 41 , the sampling signal 22 , and the physical quantity detection signal 12 , and outputs the mode switching signal 51 to the clock generation circuit 20 .

The physical quantity detection unit 10 is a magnetic switch that detects a magnetic field of S pole or N pole, and switches the potential level of the physical quantity detection signal 12 according to the magnitude of the magnetic flux density applied from the outside. Further, the physical quantity detecting unit 10 performs intermittent driving having an operation period for detecting or canceling detection of the physical quantity according to the control signal 21 and a rest period for cutting off most of the operating current of the internal circuit.

The clock control circuit 50 samples the potential detection signal 41 in synchronization with the sampling signal 22, and holds the data in a shift register or the like. The clock control circuit 50 switches the mode switching signal 51 to a level corresponding to the test mode when a predetermined signal pattern (herein referred to as LHHL and HLLH) is obtained from the potential detection signal 41 . Further, when the physical quantity detection signal 12 changes, the clock control circuit 50 switches the mode switching signal 51 to a level corresponding to the normal mode.

The physical quantity detection part 10 is comprised so that the operation|movement shown below may be performed, for example.

The physical quantity detection unit 10 becomes an operating period when the control signal 21 is at the H level, compares the output voltage of the Hall element with a reference voltage, and becomes a rest period when the control signal 21 is at the L level, and is applied When the obtained magnetic flux density is smaller than a predetermined value, an L level physical quantity detection signal 12 is output if it is greater than a predetermined value, and an H level physical quantity detection signal 12 is output.

As the output driver 30, a CMOS driver is used, for example. The output driver 30 generates an output logic signal ( 32) is output to the output terminal 31 . When the applied physical quantity is large, for example, when the input physical quantity detection signal 12 is at H level, the Nch driver is turned on and the Pch driver is turned off, so that the L level output logic signal 32 is output to the output terminal 31 . output to

The electric potential detection circuit 40 is comprised, for example with a smit trigger circuit, a comparator by a differential pair and a reference voltage circuit, etc. The potential detection circuit 40 outputs an H-level potential detection signal 41 when the potential of the output terminal 31 is at the H level, and detects the L-level potential when the potential of the output terminal 31 is at the L level. A signal 41 is output.

Next, the operation of the sensor circuit 100 of the first embodiment will be described.

2 is a timing diagram showing the operation of the sensor circuit 100 of the first embodiment.

In Fig. 2, the magnetic flux density applied to the sensor circuit 100 is Bin, the voltage of the physical quantity detection signal 12 is V12, the voltage of the output terminal 31 is V31, the voltage of the potential detection signal 41 is V41, The voltage of the control signal 21 is V21, the voltage of the sampling signal 22 is V22, and the voltage of the mode switching signal 51 is V51. Moreover, let BOP be the threshold value at which the physical quantity detection part 10 detects a physical quantity, and let BRP be the threshold value which cancel|releases detection.

A magnetic flux density Bin as shown in the timing diagram is applied to the sensor circuit 100 . Since the magnetic flux density Bin is lower than the threshold value BRP before time t0, the physical quantity detection signal 12 is at the L level, and the voltages of the output terminal 31 and the potential detection signal 41 are at the H level.

The sensor circuit 100 is a rest period during normal operation until the time t1, the mode switching signal 51 maintains the L level, and the sampling signal 22 is output from the clock generator circuit 20 . In the sampling signal 22 before the time t1, the clock control circuit 50 continuously maintains the H level of the potential detection signal 41, so that the normal operation (mode switching signal 51 is L level) to keep Here, it is assumed that the clock control circuit 50 reads out the potential of the potential detection signal 41 at the rising edge of the sampling signal 22 .

The sensor circuit 100 is an operation period during normal operation between time t1 and time t2, and the clock generation circuit 20 sets the control signal 21 to H level. The physical quantity detection unit 10 detects that the magnetic flux density Bin is higher than the threshold value BOP during the operation period and performs signal processing, and when the control signal 21 becomes L level, the physical quantity detection signal 12 is H level. Accordingly, the voltages of the output terminal 31 and the potential detection signal 41 become L level. Then, the sensor circuit 100 again becomes a rest period during normal operation, the mode switching signal 51 maintains the L level, and the sampling signal 22 is output from the clock generator circuit 20 .

The clock control circuit 50 reads and inputs the L level of the potential detection signal 41 by the sampling signal 22 at time t3.

Here, from time t4 to time t7, when H level is forcibly inputted to the output terminal 31 from the outside, the clock control circuit 50 detects a potential by the sampling signal 22 at times t5 and t6. The H level of the signal 41 is read and input, and the L level of the potential detection signal 41 is read and inputted by the sampling signal 22 at time t8.

Therefore, the clock control circuit 50 judges that it is a test mode input signal between time t8 and time t9 because the input signal pattern is at the LHHL level, and switches from the normal operation to the test mode, A mode switching signal 51 is output.

After the sensor circuit 100 maintains the test mode until time t10, when the physical quantity detection unit 10 detects that the magnetic flux density Bin has become equal to or less than the release threshold value BRP, the physical quantity detection signal 12 is L change to level. The clock control circuit 50 receives that the physical quantity detection signal 12 has changed to the L level, switches from the test mode to the normal operation, and outputs the L level mode switching signal 51 .

As described above, the sensor circuit 100 of the present embodiment performs a normal operation by forcibly inputting a voltage having a predetermined signal pattern to the output terminal 31 from the outside and detecting it in the idle period during normal operation. It was set as the structure which switches from operation|movement to a test mode, receives the change of the level of the physical quantity detection signal 12, and switches from a test mode to a normal operation|movement. Accordingly, the sensor circuit 100 of the present embodiment is unlikely to be accidentally switched to the test mode, and stable operation is possible.

In addition, in the timing diagram of FIG. 2, although the description was made for switching to the test mode from the state in which the magnetic flux density Bin is higher than the detection threshold value BOP, from the state in which the magnetic flux density Bin is lower than the release threshold value BRP. The same is true for switching to test mode. In this case, by forcibly setting the output terminal 31 to the L level potential and setting the signal pattern to HLLH, the clock control circuit 50 determines that it is a test mode input signal, and can switch from the normal operation to the test mode. have.

Moreover, although the signal pattern was demonstrated as LHHL or HLLH, it is not limited to this, A more complex signal pattern or a short signal pattern may be sufficient.

<Second embodiment>

3 is a block diagram of a sensor circuit 200 according to the second embodiment. The sensor circuit 200 of the second embodiment was provided with a counter 60 for counting the timeout time in addition to the sensor circuit 100 of FIG. 1 . Further, the clock control circuit 50 in the second embodiment is configured to receive the timeout signal 61 output from the counter 60 . About the other structure, since it is the same as that of the sensor circuit 100 of FIG. 1, the same code|symbol is attached|subjected to the same component, and description is abbreviate|omitted.

The counter 60 receives the potential detection signal 41 output from the potential detection circuit 40 , and outputs a timeout signal 61 to the clock control circuit 50 . When the clock control circuit 50 receives the H level timeout signal 61 , it masks the sampling signal 22 .

Next, the operation of the sensor circuit 200 of the second embodiment will be described.

4 is a timing diagram showing the operation of the sensor circuit 200 according to the second embodiment.

In Fig. 4, the voltage of the timeout signal 61 is V61. In addition, about the same operation|movement as the timing diagram of FIG. 2, the description is abbreviate|omitted.

At time t1, the physical quantity detection signal 12 becomes H level, and the voltage of the output terminal 31 becomes L level.

At time t2, when noise from the outside is superimposed on the output terminal 31, as shown in the figure, the voltage V31 fluctuates, and an H-level potential detection signal 41 is output. Accordingly, the clock control circuit 50 reads and inputs the H level of the potential detection signal 41 by the sampling signal 22 .

The counter 60 starts counting in response to the fluctuation of the potential detection signal 41, and when the timeout time is reached at the time t3, the timeout signal 61 is changed from the L level to the H level. When the clock control circuit 50 receives the timeout signal 61 of H level, since it masks the sampling signal 22, the H level of the potential detection signal 41 due to noise from the outside at time 4 do not read input

Therefore, since the clock control circuit 50 does not recognize the signal pattern after time t2 as HLLH, even if there is noise as in FIG. 4, it does not accidentally switch to the test mode.

As described above, in the sensor circuit of the second embodiment, since the counter 60 for outputting the timeout signal 61 is provided, it is possible to more reliably prevent a malfunction of accidentally switching to the test mode.

In addition, the counter 60 may be comprised by the digital circuit using the logic circuit by a flip-flop, and may be comprised by the analog clock circuit by the constant current source and a capacitor element. The timeout signal 61 may be reset from the H level to the L level by the control signal 21, for example, at time t5 or t6.

<Third embodiment>

5 is a block diagram of a sensor circuit 300 according to the third embodiment. The sensor circuit 300 of the third embodiment includes a dead time control circuit 70 that receives the control signal 21 and outputs the dead time signal 71 in addition to the sensor circuit 100 of FIG. 1 . Moreover, the clock control circuit 50 in 3rd Embodiment was set as the structure which receives the dead-time signal 71 outputted from the dead-time control circuit 70. As shown in FIG. About the other structure, since it is the same as that of the sensor circuit 100 of FIG. 1, the same code|symbol is attached|subjected to the same component, and description is abbreviate|omitted.

The dead time control circuit 70 receives the potential detection signal 41 and outputs the dead time signal 71 to the clock control circuit 50 . The clock control circuit 50 masks the sampling signal 22 upon receiving the H-level dead time signal 71 .

Next, the operation of the sensor circuit 300 of the third embodiment will be described.

6 is a timing diagram showing the operation of the sensor circuit 300 according to the third embodiment.

In Fig. 6, the voltage of the dead time signal 71 is V71. In addition, about the same operation|movement as the timing diagram of FIG. 2, the description is abbreviate|omitted.

At time t1, the physical quantity detection signal 12 is at the H level, and the output driver 30 sets the output to the L level. Here, when the capacitive load of the output terminal 31 is large, the voltage V31 of the output terminal 31 depends on a time constant determined by the capacitive load of the output terminal 31 and the on-resistance of the output driver 30 . It takes a relatively long time to correct.

The dead time control circuit 70 receives that the control signal 21 has reached the H level, that is, outputs the H level dead time signal 71 for a predetermined period after the transition to the idle period. The clock control circuit 50 masks the sampling signal 22 and does not perform the sampling operation until the time t3 at which the dead time signal 71 maintains the H level. Therefore, the clock control circuit 50 does not read and input the H level of the potential detection signal 41 from time t1 to time t3.

At time t2, since the voltage V31 of the output terminal 31 is less than the determination threshold value Vth of the potential detection circuit 40, the potential detection signal 41 becomes L level. Therefore, the time during which the dead time signal 71 maintains the H level may be longer than the time during which the voltage V31 becomes less than the determination threshold value Vth.

Therefore, since the clock control circuit 50 does not recognize the signal pattern after time t1 as HLLH even if noise is superimposed on the output terminal 31 at time t4, it does not accidentally switch to the test mode. .

As described above, since the sensor circuit 300 of the third embodiment includes the dead-time control circuit 70 that outputs the dead-time signal 71 to the clock control circuit 50, a malfunction of erroneously switching to the test mode can be prevented more reliably.

In addition, the dead time control circuit 70 may be comprised by the logic circuit by a flip-flop, and may be comprised by the clock circuit by a constant current source, a capacitor|capacitance element, and a threshold value circuit.

In addition, although it has been described that the dead time signal 71 outputs the H level when the control signal 21 has reached the H level, any signal may be used as the starting point as long as it meets the gist of the invention.

<Fourth embodiment>

7 is a block diagram of a sensor circuit 400 according to the fourth embodiment. The sensor circuit 400 of the fourth embodiment includes a reset circuit 80 that outputs a reset signal 81 in addition to the sensor circuit 100 of FIG. 1 . Further, the clock control circuit 50 in the fourth embodiment is configured to receive the reset signal 81 output from the reset circuit 80 . About the other structure, since it is the same as that of the sensor circuit 100 of FIG. 1, the same code|symbol is attached|subjected to the same component, and description is abbreviate|omitted.

The reset circuit 80 receives the potential detection signal 41 and outputs the reset signal 81 to the clock control circuit 50 . When the clock control circuit 50 receives the reset signal 81 of the H level, it resets the shift register holding the signal pattern.

Next, the operation of the sensor circuit 400 of the fourth embodiment will be described.

8 is a timing diagram showing the operation of the sensor circuit 400 according to the fourth embodiment.

In Fig. 8, the voltage of the reset signal 81 is V81. In addition, about the same operation|movement as the timing diagram of FIG. 2, the description is abbreviate|omitted.

At time t1, the physical quantity detection signal 12 is at the H level, and the output driver 30 sets the output to the L level. The reset signal 81 is reset to the L level when the rest period is reached.

At time t2, when noise from the outside is superimposed on the output terminal 31, as shown in the figure, the voltage V31 fluctuates, and an H-level potential detection signal 41 is output. Accordingly, the clock control circuit 50 reads and inputs the H level of the potential detection signal 41 by the sampling signal 22 .

Here, the reset circuit 80 has a function of detecting the signal width of the potential detection signal 41 . For example, when detecting that the width is small as in time t2 in FIG. 8 , the reset signal 81 of H level is output to the clock control circuit 50 at time t3, for example. When the clock control circuit 50 receives the reset signal 81 of the H level, it resets the shift register holding the signal pattern. That is, the H level read and input into the shift register at time t2 is reset.

Therefore, even if noise from the outside is superimposed on the output terminal 31 at time t4, the clock control circuit 50 does not mistake the pattern of the potential detection signal 41 and recognizes it as HLLH.

As described above, since the sensor circuit 400 of the fourth embodiment is provided with the reset circuit 80 for outputting the reset signal 81 to the clock control circuit 50, a malfunction of erroneously switching to the test mode is more reliably confirmed. can be prevented

In addition, although the reset signal 81 is L level in response to the control signal 21 becoming H level in FIG. 8, it is good also as a one-shot pulse, for example.

As described above, the sensor circuit of the present invention includes a clock control circuit 50 that samples the potential detection signal 41 in synchronization with the sampling signal 22, and a clock that outputs the sampling signal 22 in the idle period. Since the generator circuit 20 is provided, it is possible to more reliably prevent a malfunction of accidentally switching to the test mode.

In addition, in embodiment, although the physical quantity detection part 10 was demonstrated as a magnetic sensor circuit, if it is a structure which outputs the detection result of a physical quantity as a binary signal from the output terminal 31, it will not restrict to this. For example, the physical quantity detection unit 10 may be a temperature sensor circuit or an optical sensor circuit.

In addition, the sensor circuit of this invention is not necessarily limited to this structure or a sensor element, Various changes, combinations, etc. are possible in the range which does not deviate from the meaning of invention. For example, you may combine the circuits of each embodiment suitably. In addition, even with a configuration in which a plurality of combinations of the physical quantity detection unit 10, the output terminal 31, and the clock control circuit 50 are provided, a voltage is forcibly applied to each output terminal, and the combination switches to the test mode. do.

10: physical quantity detection unit
20: clock generation circuit
30: output driver
31: output terminal
40: potential detection circuit
50: clock control circuit
60 : counter
70: dead time control circuit
80: reset circuit
100, 200, 300, 400: sensor circuit

Claims (5)

A sensor circuit for intermittent operation having an operation period and an idle period, the sensor circuit comprising:
a physical quantity detection unit for outputting physical quantity detection signals of two different potential levels according to the applied physical quantity;
an output driver receiving the physical quantity detection signal and outputting a logic signal to an output terminal;
a clock generation circuit for outputting a control signal for controlling the intermittent operation to the physical quantity detection unit and outputting a sampling signal during the idle period;
a potential detection circuit for detecting the potential of the output terminal and outputting a detection signal;
a clock control circuit receiving the sampling signal and the detection signal and outputting a mode switching signal to the clock generator circuit;
wherein the clock control circuit outputs a mode switching signal for switching the clock generation circuit to a test mode when a predetermined signal pattern is detected in data sampled from the detection signal based on the sampling signal. . The method of claim 1,
The clock control circuit further receives the physical quantity detection signal output by the physical quantity detection unit;
and outputting a mode switching signal for switching to a normal mode when the physical quantity detection signal changes in the test mode. 3. The method according to claim 1 or 2,
In addition, a counter is provided,
the counter starts counting in response to a change in the detection signal, and outputs a timeout signal to the clock control circuit when a timeout time is reached;
and the clock control circuit masks the sampling signal by the timeout signal. 3. The method according to claim 1 or 2,
Further comprising a dead time control circuit,
the dead time control circuit outputs a dead time signal to the clock control circuit in a predetermined period after the transition to the idle period;
and the clock control circuit masks the sampling signal by the dead time signal. 3. The method according to claim 1 or 2,
Further comprising a reset circuit,
the reset circuit outputs a reset signal to the clock control circuit when detecting that the width of the detection signal is smaller than a predetermined value;
and the clock control circuit masks the sampling signal by the reset signal.

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