JP2010220027A - Binarizing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a binarizing circuit which binarizes input signal. <P>SOLUTION: The binarizing circuit 10 includes an input terminal 20, a basic clock terminal 22, a reset terminal 24, a first output terminal 26, a second output terminal 28, a decision clock terminal 27, a peak hold circuit 30, a bottom hold circuit 40, an output signal generation circuit 120, and a compensation signal generation circuit 130. The output signal generation circuit 120 outputs a peak hold value decreasing signal to the bottom hold circuit 40 and also outputs a bottom hold value increasing signal to the peak hold circuit 30 during a period of operation when an input signal input to the input terminal 20 varies in a short period. The compensation signal generation circuit 130 outputs a compensation signal to the peak hold circuit 30 and also to the bottom hold circuit 40 during a period when the input signal does not vary in a short period. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a binarization circuit that binarizes an input signal that changes with time.

There are many situations where it is desired to measure an input signal that changes with time following a state change, and to detect the actual state change from the change in the measured input signal. In such a situation, a peak circuit and a bottom voltage of the measured input signal are detected using a hold circuit such as a peak hold circuit and a bottom hold circuit.
For example, a technique for measuring the rotation speed and rotation angle of a rotating body using a magnetic sensor or the like has been put into practical use. In this technique, the rotating body is formed of a magnetic body, and peaks and valleys are alternately formed in the circumferential direction on the outer peripheral surface of the rotating body. Moreover, the magnetic sensor is arrange | positioned in the position facing the outer peripheral surface of a rotary body. When the rotating body rotates, the voltage (input signal) generated in the magnetic sensor changes with time following the alternately passing peaks and troughs at positions facing the magnetic sensor. For example, when an intermediate value between a peak voltage and a bottom voltage of the input signal is obtained from the input signal detected by the magnetic sensor and the measured voltage is binarized using the intermediate value as a threshold voltage, the binarized signal (2 The rotation number and the rotation angle of the rotating body can be detected from the value output. In order to accurately detect the rotation speed and rotation angle of the rotating body, a technique for accurately measuring both the peak voltage and the bottom voltage of the input signal is required.

In the input signal, a voltage that changes in a long cycle may be superimposed on a voltage that changes in a short cycle. In the case of the above example, an input signal may be detected in which a voltage that changes in a short cycle following the rotation of the rotating body is superimposed on a voltage that changes in a long cycle due to environmental temperature changes or rotor eccentricity. is there.
FIG. 13A illustrates an input signal that is measured when a voltage that changes over a long period tends to decrease. In this case, it is necessary to detect the peak voltage of the input signal that changes in a short cycle.
FIG. 13B illustrates an input signal that is measured when a voltage that changes over a long period tends to increase. Even in this case, it is necessary to detect the bottom voltage of the input signal that changes in a short cycle.
In the case of FIG. 13A, when a simple peak hold circuit is used, the peak voltage Vp ′ indicated by the broken line is not detected, and the peak voltage of the input signal that changes in a short cycle cannot be detected. In the case of FIG. 13B, if a simple bottom hold circuit is used, the bottom voltage Vb ′ indicated by the broken line is not detected, and the bottom voltage of the input signal that changes in a short cycle cannot be detected.

Patent Document 1 discloses a compensation technique for appropriately detecting both the peak voltage of each input signal and the bottom voltage of each input signal.
The peak hold circuit of Patent Document 1 includes a first memory circuit, and increases the stored value of the first memory circuit while the voltage at the input terminal is higher than the stored value of the first memory circuit. The first memory circuit decreases the stored value in synchronization with the input of the clock signal input from the outside. The bottom hold circuit of Patent Document 1 includes a second memory circuit, and reduces the stored value of the second memory circuit while the voltage at the input terminal is lower than the stored value of the second memory circuit. The second memory circuit increases the stored value in synchronization with the input of the clock signal input from the outside.

In the compensation technique of Patent Document 1, compensation is performed by changing the stored values of the first memory circuit and the second memory circuit based on a clock signal input from the outside. That is, as indicated by a solid line in FIG. 13A, when the voltage that changes in a long cycle tends to decrease, the stored value of the first memory circuit is decreased to change the peak of the input voltage that changes in a short cycle. Prepare for the voltage drop. As a result, the voltage held by the peak hold circuit can be reduced in accordance with the drop in the peak voltage.
Similarly, as shown by a solid line in FIG. 13B, when the voltage that changes in a long cycle tends to increase, the stored value of the second memory circuit is increased to reduce the input voltage that changes in a short cycle. Prepare for rising bottom voltage. As a result, the voltage held by the bottom hold circuit can be increased as the bottom voltage increases.

The period of the input signal changes according to the rotational speed of the rotating body. Therefore, it is preferable to compensate the clock signal input to the peak hold circuit and the bottom hold circuit in synchronization with the input signal. Applicants have filed a useful compensation technique for this purpose. The technical contents are disclosed in the specification and drawings attached to Japanese Patent Application No. 2008-244369. However, this application is still unpublished at the time of filing this application.
In the compensation technique described above, the intermediate threshold value Vref between the memory value of the first memory circuit and the memory value of the second memory circuit is used, and the input signal exceeds the intermediate threshold value Vref and the input signal exceeds the intermediate threshold value Vref. When it descends, it outputs a binary signal that reverses. In the above technique, the high-side offset threshold value Vu, which is an intermediate voltage between the storage value of the first storage circuit and the intermediate threshold value Vref, the intermediate threshold value Vref, and the low-side offset threshold value Vd, which is an intermediate voltage of the storage value of the second storage circuit. Used to output a delayed binary signal that reverses when the input signal rises above the high-side offset threshold Vu and when the input signal falls below the low-side offset threshold Vd.
In the technology disclosed in the specification and drawings attached to Japanese Patent Application No. 2008-244369 (hereinafter referred to as “Technical Document 1”), a clock signal synchronized with a delayed binary signal is used as a peak hold circuit or bottom hold circuit. To enter. According to this technique, the clock signal input to the peak hold circuit or the bottom hold circuit can be compensated in synchronization with the input signal, and the input signal can be appropriately binarized.

JP 2007-178498 A

  The technique of Patent Document 1 and the technique of Technical Document 1 are very useful and useful, and can be applied to various uses. However, if the same compensation technique is used in the operating period of the rotating body in which the binarized signal changes in a short period and the rotating period in which the binarized signal does not change in a short period, the input signal is appropriately binarized. There are cases where you can't.

(Explanation when input signal cannot be binarized properly during operation period)
FIG. 14 shows an example of an input signal during the operation period. As shown in FIG. 14, when an input signal that does not change in a long cycle is input during the operation period, when the technique of Patent Document 1 is used, the intermediate threshold Vref is equal to the peak voltage Vp of the input signal indicated by the dotted line in FIG. There is a case where it deviates from the reference voltage Vm which is an intermediate value of the bottom voltage Vb. Therefore, the binarized signal obtained by binarizing the input signal using the intermediate threshold value Vref deviates from the binarized signal obtained by binarizing the input signal using the reference voltage Vm indicated by the dotted line in FIG. The input signal cannot be appropriately binarized using the threshold value Vref. When the technique of Patent Document 1 is used, the input signal can be binarized during operation after stopping, but the input signal may not be binarized appropriately.

(Explanation when the input signal cannot be properly binarized in the operation period after the stop)
FIG. 16 shows an example of an input signal when the operation is stopped and restarted after operation. In the stop period, the input signal may increase as the ambient temperature increases from T1 ° C. to T2 ° C. In such a case, the input signal does not drop beyond the low-side offset threshold Vd. For this reason, even if the technique of Technical Document 1 is used, the stored value of the second storage circuit cannot be increased in accordance with the increase of the input signal. When shifting from the stop period to the operation period again, the input signal cannot be binarized appropriately. In this way, even when the input signal can be appropriately binarized using the technique of Technical Document 1 during the operation period, the input signal is output using the same technique when the operation period is shifted from the stop period to the operation period again. There are cases where binarization cannot be performed appropriately.

  As described above, when the same compensation technique is used in the operation period and the stop period, there are cases where the input signal cannot be appropriately binarized. A technique for appropriately binarizing an input signal regardless of the state of the input signal is desired.

  The present invention solves the above problems. That is, an object of the present invention is to provide a technique capable of appropriately binarizing an input signal regardless of the state of the input signal.

In the present invention, the operation period and the stop period are determined based on whether or not the binarized output is inverted at a predetermined time, and the compensation method is switched based on this determination, so that the input is performed according to the state of the input signal. The signal was successfully binarized.
The present invention is embodied in a binarization circuit that binarizes an input signal that varies with time. The binarization circuit includes a peak hold circuit, a bottom hold circuit, an output signal generation circuit, and a compensation signal generation circuit.
The peak hold circuit includes a first memory circuit, and increases the memory value of the first memory circuit while the voltage of the input signal is higher than the memory value of the first memory circuit, and compensates for the output signal generation circuit. The stored value of the first storage circuit is changed by a compensation method determined based on the compensation signal from the signal generation circuit, and the stored value of the first storage circuit is output to the output signal generation circuit.
The bottom hold circuit includes a second memory circuit, and subtracts the memory value of the second memory circuit while the voltage of the input signal is lower than the memory value of the second memory circuit, and compensates with the output signal generation circuit. The stored value of the second storage circuit is changed by a compensation method determined based on the compensation signal from the signal generation circuit, and the stored value of the second storage circuit is output to the output signal generation circuit.
The output signal generation circuit binarizes the input signal based on a threshold value calculated from the storage value of the first storage circuit and the storage value of the second storage circuit.
The compensation signal generation circuit outputs a compensation signal that is switched between when the binarized output is inverted and when it is not inverted within a predetermined period.

In the correction signal generation circuit of the present invention, when the binarized output is inverted within a predetermined time, it is determined as an operation period, and when it is not inverted, it is determined as a stop period. The correction signal generation circuit of the present invention outputs a compensation signal based on this determination, and switches the compensation method of the stored value stored in the peak hold circuit and the bottom hold circuit based on the compensation signal.
According to the present invention, the compensation method can be switched according to each period. Therefore, the stored value can be compensated using an appropriate compensation method, and the input signal can be binarized using a threshold value calculated from the appropriately compensated stored value. Thereby, the input signal can be appropriately binarized regardless of the state of the input signal.

The binarization circuit of the present invention can be expressed as follows. The binarization circuit of the present invention inputs an input terminal for inputting an input signal, a first output terminal for outputting a first output signal, a second output terminal for outputting a second output signal, and a determination clock signal. A determination clock terminal, a compensation signal generation circuit, a peak hold circuit, a bottom hold circuit, and an output signal generation circuit are provided.
The peak hold circuit is connected to the input terminal, the output signal generation circuit, and the compensation signal generation circuit. The peak hold circuit includes a first memory circuit, and executes at least the following four operations.
(1) The storage value of the first storage circuit is increased while the voltage of the input signal is higher than the storage value of the first storage circuit.
(2) When the peak hold value decrease signal is input from the output signal generation circuit, the first predetermined value is subtracted from the stored value of the first storage circuit.
(3) When the compensation signal is input from the compensation signal generation circuit, the second predetermined value is subtracted from the stored value of the first storage circuit.
(4) The stored value of the first storage circuit is output to the output signal generation circuit.

The bottom hold circuit is connected to the input terminal, the output signal generation circuit, and the compensation signal generation circuit. Further, the bottom hold circuit includes a second memory circuit and executes at least the following four operations.
(1) While the input signal voltage is lower than the storage value of the second storage circuit, the storage value of the second storage circuit is decreased.
(2) When a bottom hold value increase signal is input from the output signal generation circuit, a third predetermined value is added from the stored value of the second storage circuit.
(3) When a compensation signal is input from the compensation signal generation circuit, a fourth predetermined value is added from the stored value of the second storage circuit.
(4) The stored value of the second storage circuit is output to the output signal generation circuit.

The output signal generation circuit is connected to the input terminal, the first output terminal, the second output terminal, the peak hold circuit, and the bottom hold circuit. The output signal generation circuit executes at least the following four operations.
(1) A first output signal obtained by binarizing an input signal based on a threshold value calculated from a storage value of the first storage circuit and a storage value of the second storage circuit is output to the first output terminal.
(2) A second output signal delayed by a predetermined phase with respect to the first output signal is output to the second output terminal.
(3) A peak hold value decrease signal is output to the peak hold circuit when the second output signal is inverted from one state to the other state.
(4) When the second output signal is inverted from the other state to one state, a bottom hold value increase signal is output to the bottom hold circuit.

  The compensation signal generation circuit is connected to the first output terminal, the peak hold circuit, and the bottom hold circuit. The compensation signal generation circuit outputs a compensation signal to the peak hold circuit and the bottom hold circuit when the first output signal is not inverted for a predetermined period.

  In the output signal generation circuit according to the present invention, when the input signal changes in a short cycle, the first output signal has a short cycle based on the threshold value calculated from the stored value of the first memory circuit and the stored value of the second memory circuit. Invert. Further, the second output signal is inverted as the first output signal is inverted. That is, the second output signal is inverted when the input signal changes in a short cycle. When the second output signal is inverted, a peak hold value decrease signal is output from the output signal generation circuit to the peak hold circuit, and the stored value of the first storage circuit decreases. Further, a bottom hold value increase signal is output from the output signal generation circuit to the bottom hold circuit, and the stored value of the second storage circuit increases.

  On the other hand, the compensation signal generation circuit outputs a compensation signal when the first output signal is not inverted in a short period. That is, the compensation signal is output when the input signal does not change in a short cycle. When the compensation signal is output from the compensation signal generation circuit to the peak hold circuit, the stored value of the first storage circuit decreases. Further, when the compensation signal is output from the compensation signal generation circuit to the bottom hold circuit, the stored value of the second storage circuit increases.

  According to the present invention, the storage value of the first storage circuit and the storage value of the second storage circuit can be appropriately binarized regardless of the state of the input signal. Thereby, the input signal in the operation period and the stop period can be appropriately binarized.

The binarization circuit preferably further includes a determination clock terminal. The determination clock terminal receives the determination clock signal and is connected to the compensation signal generation circuit. The compensation signal generation circuit outputs a compensation signal when the first output signal is not inverted over a predetermined period determined based on the period of the determination clock signal.
According to the present invention, the predetermined period for determining whether or not the first output signal is inverted can be set using the determination clock signal.

The binarization circuit preferably further includes a compensation clock terminal. The compensation clock terminal receives the compensation clock signal and is connected to the compensation signal generation circuit. The compensation signal generation circuit outputs a compensation signal synchronized with the compensation clock signal to the peak hold circuit and the bottom hold circuit when the first output signal is not inverted over a predetermined period determined based on the period of the determination clock signal. .
According to the present invention, the period of the compensation signal can be set using the compensation clock signal.

In the above binarization circuit, the output signal generation circuit includes a threshold value operation circuit, a first comparison circuit, a second comparison circuit, a first selection circuit, a second selection circuit, a third selection circuit, and a fourth selection circuit. It is preferable.
The threshold calculation circuit is connected to the peak hold circuit, the bottom hold circuit, the first comparison circuit, and the second comparison circuit. The threshold value calculation circuit includes an intermediate threshold value between the storage value of the first storage circuit and the storage value of the second storage circuit, a high-side offset threshold value between the intermediate threshold value and the storage value of the first storage circuit, and the intermediate threshold value. A low-side offset threshold value between the stored values of the second storage circuit is calculated. The threshold value calculation circuit outputs the calculated intermediate threshold value and the high-side offset threshold value to the first comparison circuit, and outputs the calculated intermediate threshold value and the low-side offset threshold value to the second comparison circuit.
The first comparison circuit is connected to the threshold value operation circuit, the input terminal, the first selection circuit, the second selection circuit, and the third selection circuit. The first comparison circuit outputs a signal that is inverted when the voltage at the input terminal falls below the intermediate threshold and when the voltage at the input terminal rises above the high-side offset threshold.
The second comparison circuit is connected to the threshold value operation circuit, the input terminal, the first selection circuit, the second selection circuit, and the fourth selection circuit. The second comparison circuit outputs a signal that is inverted when the voltage at the input terminal exceeds the intermediate threshold value and when the voltage at the input terminal falls below the low-side offset threshold value.
The first selection circuit is connected to the first comparison circuit, the second comparison circuit, and the first output terminal. The first selection circuit is inverted when the voltage at the input terminal exceeds the intermediate threshold after falling below the low-side offset threshold, and when the voltage at the input terminal falls below the intermediate threshold after exceeding the high-side offset threshold. An output signal is output to the first output terminal.
The second selection circuit is connected to the first comparison circuit, the second comparison circuit, and the second output terminal. The second selection circuit outputs, to the second output terminal, a second output signal that is inverted when the voltage at the input terminal exceeds the high-side offset threshold and when the voltage at the input terminal falls below the low-side offset threshold.
The third selection circuit is connected to the first comparison circuit and the peak hold circuit. The third selection circuit outputs a peak hold value decrease signal that is inverted when the voltage at the input terminal exceeds the high-side offset threshold value to the peak hold circuit.
The fourth selection circuit is connected to the second comparison circuit and the bottom hold circuit. The fourth selection circuit outputs to the bottom hold circuit a bottom hold value increase signal that is inverted when the voltage at the input terminal falls below the low-side offset threshold.
According to the present invention, it is possible to generate the second output signal delayed from the first output signal.

  According to the present invention, an input signal can be appropriately binarized regardless of the state of the input signal.

A circuit diagram of the binarization circuit 10 is shown. A circuit diagram of the peak hold circuit 30 is shown. A circuit diagram of the bottom hold circuit 40 is shown. A circuit diagram of the output signal generation circuit 120 is shown. 6 is a diagram for explaining the operation of an output signal generation circuit 120. FIG. A circuit diagram of the compensation signal generation circuit 130 is shown. FIG. 6 is a diagram for explaining the operation of a compensation signal generation circuit 130. 2 is a diagram illustrating a flowchart of the binarization circuit 10. FIG. 3 is a diagram illustrating a time chart of the binarization circuit 10. FIG. A circuit diagram of the binarization circuit 210 is shown. A circuit diagram of the stop determination circuit 222 is shown. The circuit diagram of another Example of the binarization circuit of a present Example is shown. It is a figure which shows the problem of a peak hold circuit and a bottom hold circuit. It is a figure explaining the problem of a prior art. It is a figure explaining the effect of this invention. It is a figure explaining the problem of a prior art. It is a figure explaining the effect of this invention.

The main features of the embodiments described below are first organized.
(Feature 1) The peak hold circuit includes a comparator circuit, a peak counter circuit, and a D / A conversion circuit.
(Feature 2) The bottom hold circuit includes a comparator circuit, a bottom counter circuit, and a D / A conversion circuit.
(Feature 3) The peak hold circuit has a terminal to which a reset signal is input. When a reset signal is input to the peak hold circuit, the stored value of the first storage circuit is initialized.
(Feature 4) The bottom hold circuit includes a terminal to which a reset signal is input. When a reset signal is input to the bottom hold circuit, the stored value of the second storage circuit is initialized.
(Feature 5) The peak hold circuit includes a terminal to which a basic clock signal is input. When the voltage of the input signal is higher than the stored value of the first storage circuit, the peak hold circuit increases the stored value of the first storage circuit in synchronization with the basic clock signal.
(Feature 6) The bottom hold circuit includes a terminal to which a basic clock signal is input. When the voltage of the input signal is lower than the stored value of the second storage circuit, the bottom hold circuit decreases the stored value of the second storage circuit in synchronization with the basic clock signal.

  FIG. 1 shows a binarization circuit 10. The binarization circuit 10 includes an input terminal 20, a basic clock terminal 22, a reset terminal 24, a first output terminal 26, a second output terminal 28, a determination clock terminal 27, a peak hold circuit 30, a bottom hold circuit 40, and an output signal generation. A circuit 120 and a compensation signal generation circuit 130 are provided.

The input terminal 20 is connected to the peak hold circuit 30, the bottom hold circuit 40, and the output signal generation circuit 120, and an input voltage is input from an external circuit (not shown) such as a magnetic sensor.
The basic clock terminal 22 is connected to the peak hold circuit 30, the bottom hold circuit 40, and the compensation signal generation circuit 130, and receives a basic clock signal that changes at an interval of a first predetermined time from an external circuit (not shown). Has been.
The reset terminal 24 is connected to the peak hold circuit 30, the bottom hold circuit 40, and the compensation signal generation circuit 130, and a reset signal is input from an external circuit (not shown).
The determination clock terminal 27 is connected to the compensation signal generation circuit 130, and receives a determination clock signal that changes at intervals of a second predetermined time from an external circuit (not shown).

  The peak hold circuit 30 is connected to the input terminal 20, the basic clock terminal 22, the reset terminal 24, the output signal generation circuit 120, and the compensation signal generation circuit 130. FIG. 2 shows a specific configuration of the peak hold circuit 30. The peak hold circuit 30 includes a comparator 31, an AND circuit 32, a counter circuit 33, and a D / A conversion circuit 34. A non-inverting input terminal 31 a of the comparator 31 is connected to the input terminal 20. The inverting input terminal 31 b of the comparator 31 is connected to the output terminal 34 a of the D / A conversion circuit 34. The output terminal 31 c of the comparator 31 is connected to one input terminal 32 a of the AND circuit 32. The other input terminal 32 b of the AND circuit 32 is connected to the basic clock terminal 22. The output terminal 32 c of the AND circuit 32 is connected to the UP input terminal 33 b of the counter circuit 33. The first DOWN input terminal 33 c of the counter circuit 33 is connected to the output signal generation circuit 120. The second DOWN input terminal 33 d of the counter circuit 33 is connected to the compensation signal generation circuit 130. A reset (RES) input terminal 33 a of the counter circuit 33 is connected to the reset terminal 24. The counter circuit 33 is connected to the D / A conversion circuit 34. The output terminal 34 a of the D / A conversion circuit 34 is connected to the inverting input terminal 31 b of the comparator 31 and is also connected to the output signal generation circuit 120.

  In the peak hold circuit 30, the voltage input to the non-inverting input terminal 31a of the comparator 31 (the voltage of the input signal) is the voltage of the peak hold circuit 30 input to the inverting input terminal 31b (that is, the stored value of the peak hold circuit 30). ), The voltage at the output terminal 31c becomes high. When the voltage at the output terminal 31c of the comparator 31 is high, an output signal synchronized with the basic clock signal is input from the output terminal 32c of the AND circuit 32 to the UP input terminal 33b of the counter circuit 33, and the counter is accompanied by this signal. The counter value stored in the circuit 33 increases. That is, the counter circuit 33 corresponds to the first storage circuit, and the counter value stored in the counter circuit 33 corresponds to the storage value of the first storage circuit. In the counter circuit 33, when the signal from the output signal generation circuit 120 is input to the first DOWN input terminal 33c of the counter circuit 33, the counter value of the counter circuit 33 is decreased by a first predetermined value in accordance with this signal. To do. When the signal from the compensation signal generation circuit 130 is input to the second DOWN input terminal 33d of the counter circuit 33, the counter value of the counter circuit 33 is decreased by a second predetermined value along with this signal. In the counter circuit 33, when a reset signal is input from the reset terminal 24 to the RES input terminal 33a of the counter circuit 33, the counter value of the counter circuit 33 is reset to an initial value in accordance with this signal. The D / A conversion circuit 34 reads the counter value of the counter circuit 33, generates a peak voltage corresponding to the counter value, and outputs the peak voltage from the output terminal 34a to the output signal generation circuit 120.

In the peak hold circuit 30, the counter value of the counter circuit 33 is decreased in accordance with the signals from the output signal generation circuit 120 and the compensation signal generation circuit 130. Therefore, even when the input voltage includes a long-cycle fluctuation component as well as a short-cycle fluctuation component, and even when the peak voltage of the input voltage gradually decreases, the peak hold circuit 30 Can be memorized. Specifically, the counter value of the counter circuit 33 is decreased by a first predetermined value in accordance with a peak hold value decrease signal from the output signal generation circuit 120 described later, and the counter is increased in accordance with the compensation signal from the compensation signal generation circuit 130. The counter value of the circuit 33 is decreased by a second predetermined value.
As will be described later, a peak hold value decrease signal is input when the input voltage changes in a short cycle, and a compensation signal is input when the input voltage does not change in a short cycle. Therefore, in the peak hold circuit 30, a signal for decreasing the counter value of the counter circuit 33 is switched according to the state of the input voltage.

  The bottom hold circuit 40 is connected to the input terminal 20, the basic clock terminal 22, the reset terminal 24, the output signal generation circuit 120, and the compensation signal generation circuit 130. FIG. 3 shows a specific configuration of the bottom hold circuit 40. The bottom hold circuit 40 includes a comparator 41, an AND circuit 42, a counter circuit 43, and a D / A conversion circuit 44. An inverting input terminal 41 b of the comparator 41 is connected to the input terminal 20. The non-inverting input terminal 41 a of the comparator 41 is connected to the output terminal 44 a of the D / A conversion circuit 44. The output terminal 41 c of the comparator 41 is connected to one input terminal 42 a of the AND circuit 42. The other input terminal 42 b of the AND circuit 42 is connected to the basic clock terminal 22. The output terminal 42 c of the AND circuit 42 is connected to the DOWN input terminal 43 b of the counter circuit 43. The first UP input terminal 43 c of the counter circuit 43 is connected to the output signal generation circuit 120. The second UP input terminal 43 d of the counter circuit 43 is connected to the compensation signal generation circuit 130. A reset (RES) input terminal 43 a of the counter circuit 43 is connected to the reset terminal 24. The counter circuit 43 is connected to the D / A conversion circuit 44. The output terminal 44 a of the D / A conversion circuit 44 is connected to the non-inverting input terminal 41 a of the comparator 41 and is also connected to the output signal generation circuit 120.

  In the bottom hold circuit 40, the voltage input to the inverting input terminal 41b of the comparator 41 (the voltage of the input signal) is the voltage of the bottom hold circuit 40 input to the non-inverting input terminal 41a (that is, the stored value of the bottom hold circuit 40). ), The voltage of the output terminal 41c becomes high. When the voltage of the output terminal 41c of the comparator 41 is high, an output signal synchronized with the basic clock signal is input from the output terminal 42c of the AND circuit 42 to the DOWN input terminal 43b of the counter circuit 43, and the counter is accompanied by this signal. The counter value stored in the circuit 43 decreases. That is, the counter circuit 43 corresponds to the second storage circuit, and the counter value stored in the counter circuit 43 corresponds to the storage value of the second storage circuit. In the counter circuit 43, when the signal from the output signal generation circuit 120 is input to the first UP input terminal 43c of the counter circuit 43, the counter value of the counter circuit 43 is increased by a third predetermined value along with this signal. To do. When the signal from the compensation signal generation circuit 130 is input to the second UP input terminal 43d of the counter circuit 43, the counter value of the counter circuit 43 increases by a fourth predetermined value along with this signal. In the counter circuit 43, when a reset signal is input from the reset terminal 24 to the RES input terminal 43a of the counter circuit 43, the counter value of the counter circuit 43 is reset to an initial value in accordance with this signal. The D / A conversion circuit 44 reads the counter value of the counter circuit 43, generates a bottom voltage corresponding to the counter value, and outputs the bottom voltage from the output terminal 44a to the output signal generation circuit 120.

In the bottom hold circuit 40, the counter value of the counter circuit 43 is increased in accordance with the signals from the output signal generation circuit 120 and the compensation signal generation circuit 130. Therefore, even when the input voltage includes a long-cycle fluctuation component as well as a short-cycle fluctuation component, and even when the bottom voltage of the input voltage increases slowly, the bottom voltage that changes in the short cycle is converted into the bottom hold circuit 40. Can be memorized. Specifically, the count value of the counter circuit 43 is increased by a third predetermined value in accordance with a bottom hold value increase signal from the output signal generation circuit 120 described later, and the counter is increased in accordance with the compensation signal from the compensation signal generation circuit 130. The counter value of the circuit 43 is increased by a fourth predetermined value.
As will be described later, a bottom hold value increase signal is input when the input voltage changes in a short cycle, and a compensation signal is input when the input voltage does not change in a short cycle. In the bottom hold circuit 40, a signal for increasing the counter value of the counter circuit 43 is switched according to the state of the input voltage.

  The output signal generation circuit 120 is connected to the input terminal 20, the first output terminal 26, the second output terminal 28, the peak hold circuit 30, and the bottom hold circuit 40. FIG. 4 shows a specific configuration of the output signal generation circuit 120. The output signal generation circuit 120 includes a threshold value calculation circuit 50, a first comparison circuit 60, a second comparison circuit 70, a first selection circuit 80, a second selection circuit 90, a third selection circuit 100, and a fourth selection circuit 110. Yes.

The threshold calculation circuit 50 is connected to the peak hold circuit 30, the bottom hold circuit 40, the first comparison circuit 60, and the second comparison circuit 70. A specific configuration of the threshold value calculation circuit 50 is shown on the left side of FIG. As shown in FIG. 4, in the threshold value calculation circuit 50, four resistors R <b> 1 to R <b> 4 are connected in series in this order between the connection terminal 51 to the peak hold circuit 30 and the connection terminal 55 to the bottom hold circuit 40. Yes. A first connection terminal 52 is formed between the resistor R1 and the resistor R2. A second connection terminal 53 is formed between the resistor R2 and the resistor R3. A third connection terminal 54 is formed between the resistors R3 and R4.
The resistance values of the resistors R1 to R4 are the same. Therefore, the voltage of each connection terminal 52, 53, 54 is adjusted to the following value.

Vref = (peak voltage−bottom voltage) × (1/2) + bottom voltage Vu = (peak voltage−bottom voltage) × (3/4) + bottom voltage Vd = (peak voltage−bottom voltage) × (¼) ) + Bottom voltage The voltage Vref of the second connection terminal 53 is an average value of the peak voltage and the bottom voltage, and is used as the intermediate threshold value Vref. The voltage Vu of the first connection terminal 52 is an average value of the peak voltage and the intermediate threshold value Vref, and is used as the high-side offset threshold value Vu. The voltage Vd of the third connection terminal 54 is an average value of the intermediate threshold value Vref and the bottom voltage, and is used as the low-side offset threshold value Vd.

  The first comparison circuit 60 is connected to the input terminal 20, the threshold value calculation circuit 50, the first selection circuit 80, the second selection circuit 90, and the third selection circuit 100. As shown in FIG. 4, the first comparison circuit 60 includes a first transistor S1, a second transistor S2, a first comparator 61, and a NOT circuit 62. The high-side offset threshold value Vu is input to one terminal of the first transistor S1, and the other terminal is connected to the inverting input terminal 61a of the first comparator 61. The output terminal 62b of the NOT circuit 62 is connected to the gate electrode G1 of the first transistor S1. The intermediate threshold value Vref is input to one terminal of the second transistor S 2, and the other terminal is connected to the inverting input terminal 61 a of the first comparator 61. The output terminal 61c of the first comparator 61 is connected to the gate electrode G2 of the second transistor S2. The non-inverting input terminal 61 b of the first comparator 61 is connected to the input terminal 20. The output terminal 61c of the first comparator 61 is connected to the gate electrode G2 of the second transistor S2, and is connected to the input terminal 62a of the NOT circuit 62, the second selection circuit 90, and the third selection circuit 100. The output terminal 62b of the NOT circuit 62 is connected to the gate electrode G1 of the first transistor S1 and to the first selection circuit 80.

  The second comparison circuit 70 is connected to the input terminal 20, the threshold value calculation circuit 50, the first selection circuit 80, the second selection circuit 90, and the fourth selection circuit 110. As shown in FIG. 4, the second comparison circuit 70 includes a third transistor S3, a fourth transistor S4, a second comparator 71, and a NOT circuit 72. The intermediate threshold value Vref is input to one terminal of the third transistor S 3, and the other terminal is connected to the inverting input terminal 71 a of the second comparator 71. The output terminal 72b of the NOT circuit 72 is connected to the gate electrode G3 of the third transistor S3. The low-side offset threshold value Vd is input to one terminal of the fourth transistor S4, and the other terminal is connected to the inverting input terminal 71a of the second comparator 71. The output terminal 71c of the second comparator 71 is connected to the gate electrode G4 of the fourth transistor S4. A non-inverting input terminal 71 b of the second comparator 71 is connected to the input terminal 20. The output terminal 71c of the second comparator 71 is connected to the gate electrode G4 of the fourth transistor S4 and to the input terminal 72a of the NOT circuit 72 and the first selection circuit 80. An output terminal 72b of the NOT circuit 72 is connected to the gate electrode G3 of the third transistor S3 and to the second selection circuit 90 and the fourth selection circuit 110.

  The operation of the first comparison circuit 60 and the second comparison circuit 70 will be described with reference to FIG. FIG. 5 shows a change in the voltage input to the input terminal 20, and FIG. 5 illustrates a case where the peak voltage and the bottom voltage are constant. When the peak voltage and the bottom voltage are constant, the high-side offset threshold value Vu, the intermediate threshold value Vref, and the low-side offset threshold value Vd are also constant. FIG. 5B shows the output voltage that the first comparison circuit 60 outputs to the first selection circuit 80. FIG. 5C shows the output voltage that the second comparison circuit 70 outputs to the second selection circuit 90 and the fourth selection circuit 110. FIG. 5D shows a binarized signal that is the first output signal output from the first selection circuit 80 to the first output terminal 26. FIG. 5E shows a delayed binary signal that is the second output signal output from the second selection circuit 90 to the second output terminal 28.

The operation of the first comparison circuit 60 will be described. The first transistor S1 and the second transistor S2 shown in FIG. 4 are both n-type transistors, and are turned on when a high voltage is applied to the gate electrode. Until the input voltage exceeds the high-side offset threshold Vu (t12), the first transistor S1 is on and the second transistor S2 is off. The high-side offset threshold value Vu is input to the inverting input terminal 61a of the first comparator 61, and a high signal is output to the first selection circuit 80 as shown in FIG.
When the input voltage exceeds the high-side offset threshold Vu (t12), the voltage at the output terminal 61c of the first comparator 61 is switched to high. As a result, the second transistor S2 is turned on. Further, the voltage at the output terminal 62b of the NOT circuit 62 is switched to low. As a result, the first transistor S1 is turned off. As a result, the voltage at the inverting input terminal 61a of the first comparator 61 is switched to the intermediate threshold value Vref, and the signal output to the first selection circuit 80 is switched to low as shown in FIG.
Next, when the input voltage falls below the intermediate threshold value Vref (t13), the voltage at the output terminal 61c of the first comparator 61 is switched to low. As a result, the second transistor S2 is turned off. Further, the voltage at the output terminal 62b of the NOT circuit 62 is switched to high. As a result, the first transistor S1 is turned on. As a result, the voltage at the inverting input terminal 61a of the first comparator 61 is switched to the high-side offset threshold Vu, and the signal output to the first selection circuit 80 is switched to high as shown in FIG. 5B. . Thereafter, this operation is repeated.
In the first comparison circuit 60, the voltage input to the inverting input terminal 61a of the first comparator 61 is switched between the high-side offset threshold value Vu and the intermediate threshold value Vref using the first transistor S1 and the second transistor S2. As a result, a signal that is inverted when the input voltage falls below the intermediate threshold Vref and when the input voltage exceeds the high-side offset threshold Vu is output.

Next, the operation of the second comparison circuit 70 will be described. The third transistor S3 and the fourth transistor S4 shown in FIG. 4 are both n-type transistors and are turned on when a high voltage is applied to the gate electrode. Until the input voltage exceeds the intermediate threshold Vref (t11), the third transistor S3 is on and the fourth transistor S4 is off. The intermediate threshold value Vref is input to the inverting input terminal 71a of the second comparator 71, and a high signal is output to the second selection circuit 90 and the fourth selection circuit 110 as shown in FIG.
When the input voltage exceeds the intermediate threshold value Vref (t11), the voltage at the output terminal 71c of the second comparator 71 is switched to high. As a result, the fourth transistor S4 is turned on. Further, the voltage at the output terminal 72b of the NOT circuit 72 is switched to low. As a result, the third transistor S3 is turned off. As a result, the voltage at the inverting input terminal 71a of the second comparator 71 is switched to the low-side offset threshold value Vd, and is output to the second selection circuit 90 and the fourth selection circuit 110 as shown in FIG. The signal switches to low.
Next, when the input voltage falls below the low-side offset threshold Vd (t14), the voltage at the output terminal 71c of the second comparator 71 is switched to low. As a result, the fourth transistor S4 is turned off. Further, the voltage at the output terminal 72b of the NOT circuit 72 is switched to high. As a result, the third transistor S3 is turned on. As a result, the voltage at the inverting input terminal 71a of the second comparator 71 is switched to the intermediate threshold value Vref, and the signals output to the second selection circuit 90 and the fourth selection circuit 110 as shown in FIG. Switch to high. Thereafter, this operation is repeated.
In the second comparison circuit 70, the voltage input to the inverting input terminal 71a of the second comparator 71 is switched between the intermediate threshold value Vref and the low-side offset threshold value Vd using the third transistor S3 and the fourth transistor S4. As a result, a signal that is inverted when the input voltage falls below the low-side offset threshold Vd and when the input voltage exceeds the intermediate threshold Vref is output.

The first selection circuit 80 is connected to the first comparison circuit 60, the second comparison circuit 70, and the first output terminal 26. As shown in FIG. 4, the first selection circuit 80 includes a flip-flop circuit 81.
The flip-flop circuit 81 has a set terminal 81S, a reset terminal 81R, and an output terminal 81Q. In the flip-flop circuit 81, when the set terminal 81S rises from low to high, the voltage at the output terminal 81Q goes high, and when the reset terminal 81R rises from low to high, the voltage at the output terminal 81Q goes low. It becomes.
The set terminal 81S of the flip-flop circuit 81 is connected to the second comparison circuit 70, and a signal obtained by inverting the signal shown in FIG. The reset terminal 81R of the flip-flop circuit 81 is connected to the first comparison circuit 60, and the signal shown in FIG. The output terminal 81Q of the flip-flop circuit 81 is connected to the first output terminal 26. Due to the input / output signal characteristics of the flip-flop circuit described above, as shown in FIG. 5 (D), when the input voltage falls below the intermediate threshold Vref (t11), the input voltage is reduced from the first output terminal 26. A binarized signal that is a first output signal that is inverted when the intermediate threshold value Vref is exceeded (t13) is output.

The second selection circuit 90 is connected to the first comparison circuit 60, the second comparison circuit 70, and the second output terminal 28. As shown in FIG. 4, the second selection circuit 90 includes a flip-flop circuit 91. The flip-flop circuit 91 has the same terminal and input / output characteristics as the flip-flop circuit 81, and a duplicate description is omitted.
The set terminal 91S of the flip-flop circuit 91 is connected to the first comparison circuit 60, and a signal obtained by inverting the signal shown in FIG. The reset terminal 91R of the flip-flop circuit 91 is connected to the second comparison circuit 70, and the signal shown in FIG. The output terminal 91Q of the flip-flop circuit 91 is connected to the second output terminal 28. Due to the input / output signal characteristics of the flip-flop circuit described above, as shown in FIG. 5E, when the input voltage exceeds the high-side offset threshold Vu (t12), the input from the second output terminal 28 A delayed binary signal that is a second output signal that is inverted when the voltage falls below the low-side offset threshold Vd (t14) is output.

  The third selection circuit 100 is connected to the first comparison circuit 60 and the peak hold circuit 30. As shown in FIG. 4, the third selection circuit 100 includes a rising edge detection circuit 101. A signal obtained by inverting the signal shown in FIG. 5B is input to the input terminal 101 a of the rise detection circuit 101, and the output terminal 101 b of the rise detection circuit 101 is connected to the peak hold circuit 30. The rise detection circuit 101 outputs a signal from the output terminal 101b when the signal input from the input terminal 101a rises from low to high. As described above, when the third selection circuit 100 sends a signal to the peak hold circuit 30, the peak hold circuit 30 subtracts the first predetermined value from the value of the counter circuit 33. The signal that the third selection circuit 100 sends to the peak hold circuit 30 can be referred to as a peak hold value decrease signal.

  The fourth selection circuit 110 is connected to the second comparison circuit 70 and the bottom hold circuit 40. As shown in FIG. 4, the fourth selection circuit 110 includes a falling detection circuit 111. The signal shown in FIG. 5C is input to the input terminal 111 a of the falling detection circuit 111, and the output terminal 111 b of the falling detection circuit 111 is connected to the bottom hold circuit 40. The fall detection circuit 111 outputs a signal from the output terminal 111b when the signal input from the input terminal 111a falls from high to low. As described above, when the fourth selection circuit 110 sends a signal to the bottom hold circuit 40, the bottom hold circuit 40 adds the third predetermined value from the value of the counter circuit 43. The signal sent from the fourth selection circuit 110 to the bottom hold circuit 40 can be referred to as a bottom hold value increase signal.

As described above, the peak hold value decrease signal and the bottom hold value increase signal are output based on the inversion of the signals output from the first comparison circuit 60 and the second comparison circuit 70. The signals output from the first comparison circuit 60 and the second comparison circuit 70 are inverted when the input signal fluctuates in a short cycle and the value fluctuates beyond Vref, Vu, Vd. That is, when the input signal changes in a short cycle, the peak hold value decrease signal and the bottom hold value increase signal are output from the output signal generation circuit 120 to the peak hold circuit 30 and the bottom hold circuit 40.
In the above description, the first comparison circuit 60 is directly connected to the third selection circuit 100, and the second comparison circuit 70 is directly connected to the fourth selection circuit 110. Instead, the first comparison circuit 60 and the second comparison circuit 70 may be connected to the third selection circuit 100 and the fourth selection circuit 110 via the second selection circuit 90.

The compensation signal generation circuit 130 is connected to the input terminal 20, the basic clock terminal 22, the reset terminal 24, the first output terminal 26, the determination clock terminal 27, the peak hold circuit 30, and the bottom hold circuit 40. FIG. 6 shows a specific configuration of the compensation signal generation circuit 130. The compensation signal generation circuit 130 includes NOT circuits 141 to 148, flip-flop circuits 151 to 162, AND circuits 171 to 179, OR circuits 181 and 182, and NAND circuits 191 and 192.
The flip-flop circuits 151 to 162 have a data terminal D, a clock terminal CK, an inversion reset terminal R (inversion set terminal S), an output terminal Q, and an inversion output terminal QB. In the flip-flop circuits 151 to 162, when both the data terminal D and the clock terminal CK are high, the voltage of the output terminal Q becomes high and the voltage of the inverting output terminal QB becomes low. When the inverting reset terminal R falls from high to low, the voltage at the output terminal Q becomes low and the voltage at the inverting output terminal QB becomes high. When the inverting set terminal S falls from high to low, the voltage at the output terminal Q goes high and the voltage at the inverting output terminal QB goes low.

  The operation of the compensation signal generation circuit 130 will be described with reference to FIGS. FIG. 7A shows a binarized signal that is the first output signal. FIG. 7B shows a determination clock signal input to the determination clock terminal 27. FIG. 7C shows an output signal of the AND circuit 175. FIG. 7D shows an output signal of the AND circuit 176. FIG. 7E shows an output signal of the AND circuit 177. FIG. 7F shows an output signal of the AND circuit 178. FIG. 7G shows a compensation signal output from the compensation signal generation circuit 130.

As shown in FIG. 7A, when the binarized signal is inverted from low to high, the signal input to the data terminal D of the flop flip circuits 151 and 153 is inverted from low to high. On the other hand, the signal input to the data terminal D of the flop flip circuits 155 and 157 is inverted from high to low. The binarized signal is input to one input terminal of the AND circuits 171 and 172. A signal obtained by inverting the binarized signal is input to one input terminal of the AND circuits 173 and 174. A signal obtained by inverting the reset signal is input to the other input terminals of the AND circuits 171 to 174. The output terminal of the AND circuit 171 is input to the inverting reset terminal R of the flop flip circuit 151. The output terminal of the AND circuit 172 is input to the inverting reset terminal R of the flop flip circuit 153. The output terminal of the AND circuit 173 is input to the inverting reset terminal R of the flop flip circuit 155. The output terminal of the AND circuit 174 is input to the inverting reset terminal R of the flop flip circuit 157. The determination clock signal is input to the clock terminals CK of the flop flip circuits 151 and 155, and a signal obtained by inverting the determination clock signal is input to the clock terminals CK of the flop flip circuits 153 and 157. The data terminal D of the flop flip circuit 152 is connected to the output terminal Q of the flop flip circuit 151. The data terminal D of the flop flip circuit 154 is connected to the output terminal Q of the flop flip circuit 153. The data terminal D of the flop flip circuit 156 is connected to the output terminal Q of the flop flip circuit 155. The data terminal D of the flop flip circuit 158 is connected to the output terminal Q of the flop flip circuit 157. A determination clock signal is input to the clock terminals CK of the flop flip circuits 154 and 158, and a signal obtained by inverting the determination clock signal is input to the clock terminals CK of the flop flip circuits 152 and 156. As a result, signals shown in FIGS. 7C to 7F are output to the AND circuits 175 to 178.
The output signals of the AND circuits 175 and 177 are input to the OR circuit 181, and the output signal of the OR circuit 181 is input to the flop flip circuits 159 and 160. The output signal of the OR circuit 181 is processed using the basic clock signal in the flop flip circuit 159, and the processed signal is input to the NAND circuit 191. A signal output from the NAND circuit 191 is input to one input terminal of the AND circuit 179.
The output signals of the AND circuits 176 and 178 are input to the OR circuit 182, and the output signal of the OR circuit 182 is input to the flop flip circuits 161 and 162. The output signal of the OR circuit 182 is processed using the basic clock signal in the flop flip circuits 161 and 162, and the processed signal is input to the NAND circuit 192. The signal output from the NAND circuit 192 is input to the other input terminal of the AND circuit 179.
An output signal of the AND circuit 179 is input to the NOT circuit 148. As a result, as shown in FIG. 7G, when the binarized signal is not inverted over the half cycle of the determination clock signal, the binarized signal is inverted during the half cycle of the determination clock signal. In this case, a compensation signal that is not inverted (indicated by a dotted line) is output from the output terminal of the NOT circuit 148.

  As described above, the compensation signal is output based on the inversion of the binarized signal (based on the fact that it is not officially inverted). The binarized signal is inverted when the input signal changes in a short period and the value changes beyond Vref, Vu, Vd. That is, when the input signal does not change in a short period, the compensation signal is output from the compensation signal generation circuit 130 to the peak hold circuit 30 and the bottom hold circuit 40.

  The operation of the binarization circuit 10 will be described with reference to FIGS. In the following description, the compensation method for the stored value of the peak hold circuit 30 using the peak hold value decrease signal and the compensation method for the stored value of the bottom hold circuit 40 using the bottom hold value increase signal are referred to as a first compensation method. A compensation method for the stored values of the peak hold circuit 30 and the bottom hold circuit 40 using the compensation signal is referred to as a second compensation method. The timer signal in FIG. 9 is a signal indicating an operation for monitoring the elapsed time of the timer built in the compensation signal generation circuit 130. The timer signal resets the elapsed time at the inversion timing and monitors the elapsed time from the inversion timing. Further, the drift compensation method of FIG. 9 shows a compensation method selected by the binarization circuit 10 at that time, and shows a state where the first compensation method is selected as a low state. Further, a state where the second compensation method is selected is shown as a high state.

In the binarization circuit 10 of this embodiment, after turning on the power at time t0, the compensation method is set to the first compensation method at time t1 and the timer signal is inverted (S12). After time t1, the binarization circuit 10 monitors the occurrence of inversion of the binarized signal and monitors the elapsed time of the timer signal (S14). While the occurrence of inversion of the binarized signal is not monitored and the elapsed time of the timer signal does not elapse the determination period T10 determined from the half cycle of the determination clock signal ((1) NO (2) NO in S14) , Keep the current state.
As shown at time t2 in FIG. 9, when the period during which the inversion of the binarized signal is not monitored has passed the determination period T10 determined from the half cycle of the determination clock signal (that is, determined as the stop period). ((1) NO (2) YES in S14), the compensation method is switched to the second compensation method and the timer signal is inverted (S16). Thereafter, during the period in which the inversion of the binarized signal is not monitored (that is, the stop period, for example, the period including time t3 in FIG. 9), the compensation method is maintained in the second compensation method, and the determination period T10 has elapsed. The timer signal is inverted every time.

  Next, as shown at time t4 in FIG. 9, when the inversion of the binarized signal is monitored within the determination period T10 (that is, it is determined that the operation period has been switched from the stop period) (in S14). (1) YES), the compensation method is switched to the first compensation method, and the timer signal is inverted (S12). Thereafter, during the period during which the inversion of the binarized signal is monitored (that is, the operation period, for example, the period including times t5 and t6), the compensation method is maintained in the first compensation method, and the binarized signal The timer signal is inverted at every inversion. Changes in the timer signal and the compensation method at times t7, t8, and t9 are the same as those at times t2, t3, and t4, and redundant description is omitted.

  According to the present embodiment, the signal for changing the storage value of the first storage circuit and the storage value of the second storage circuit based on whether or not the binarized signal changes in a cycle shorter than the determination period T10. Switch. As shown at times t4, t5, t6, and t9 in FIG. 9, the peak hold value decrease signal and the bottom hold value increase signal were used in the operation period in which the binarized signal changes in a cycle shorter than the determination period T10. Based on the first compensation method, the first stored value of the peak hold circuit 30 and the second stored value of the bottom hold circuit 40 are compensated. As a result, the input signal can be appropriately binarized during the operation period. Further, as shown at times t2, t3, t7, and t8 in FIG. 9, in the stop period in which the binarized signal does not change in a cycle shorter than the determination period T10, based on the second compensation method using the compensation signal. The first stored value of the peak hold circuit 30 and the second stored value of the bottom hold circuit 40 are compensated. Thereby, the input signal can be appropriately binarized during the rotation period. According to the present embodiment, the input signal can be binarized accurately regardless of the state of the input signal.

  FIG. 10 shows the binarization circuit 210. The difference from the binarization circuit 10 is that it has a compensation clock terminal 29 and that the compensation signal generation circuit 230 includes a stop determination circuit 222 and an AND circuit 220.

The compensation clock terminal 29 is connected to the compensation signal generation circuit 230, and receives a compensation clock signal that changes at intervals of a third predetermined time from an external circuit (not shown).
The AND circuit 220 is connected to the compensation clock terminal 29, the peak hold circuit 30, the bottom hold circuit 40, and the stop determination circuit 222. The stop determination circuit 222 is connected to the basic clock terminal 22, the reset terminal 24, the first output terminal 26, the determination clock terminal 27, and the AND circuit 220. FIG. 11 shows a specific configuration of the stop determination circuit 222. The difference from the compensation signal generation circuit 130 shown in FIG. 6 is that a NOT circuit 147, flip-flop circuits 163 to 166, an AND circuit 180, NAND circuits 193 and 194, and a set reset circuit 167 are provided.

The stop determination circuit 222 shown in FIG. 11 is high when the binarized signal is not inverted over the half cycle of the determination clock signal, and is low when the binarized signal is inverted during the half cycle of the determination clock signal. A stop signal is output. As shown in FIG. 10, the stop signal output from the stop determination circuit 222 is input to one input terminal of the AND circuit 220. The compensation clock terminal 29 is connected to the other input terminal of the AND circuit 220. Therefore, in the compensation signal generation circuit 230 of FIG. 10, a compensation signal synchronized with the compensation clock signal is input to the peak hold circuit 30 and the bottom hold circuit 40.
According to the present embodiment, the period of the determination clock signal for determining whether or not the input signal is inverted with a short period and the period of the compensation signal can be set separately.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In this embodiment, the description has been given using the binarization circuit including the compensation signal generation circuit. However, the binarization circuit does not necessarily include the compensation signal generation circuit. As shown in FIG. 12, based on the binarized signal from the first output terminal 26, a stop signal may be generated using a stop determination circuit partly provided outside.

  Further, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10, 210 Binary circuit 20 Input terminal 22 Basic clock terminal 24 Reset terminal 26 First output terminal 27 Determination clock terminal 28 Second output terminal 29 Compensation clock terminal 30 Peak hold circuit 31 Comparator 33 Counter circuit 34 A / D conversion circuit 40 bottom hold circuit 41 comparator 43 counter circuit 44 A / D conversion circuit 50 threshold calculation circuit 60 first comparison circuit 70 second comparison circuit 80 first selection circuit 90 second selection circuit 100 third selection circuit 110 fourth selection circuit 120 Output signal generation circuit 130, 230 Compensation signal generation circuit 220 AND circuit 222 Stop determination circuit

Claims (5)

A binarization circuit that binarizes an input signal that varies with time,
It has a peak hold circuit, bottom hold circuit, output signal generation circuit, and compensation signal generation circuit.
The peak hold circuit includes a first memory circuit, and increases the memory value of the first memory circuit while the voltage of the input signal is higher than the memory value of the first memory circuit, and compensates for the output signal generation circuit. Changing the storage value of the first storage circuit by a compensation method determined based on the compensation signal from the signal generation circuit, and outputting the storage value of the first storage circuit to the output signal generation circuit;
The bottom hold circuit includes a second memory circuit, and subtracts the memory value of the second memory circuit while the voltage of the input signal is lower than the memory value of the second memory circuit, and compensates with the output signal generation circuit. Changing the stored value of the second memory circuit by a compensation method determined based on the compensation signal from the signal generating circuit, and outputting the stored value of the second memory circuit to the output signal generating circuit;
The output signal generation circuit binarizes the input signal based on a threshold value calculated from the storage value of the first storage circuit and the storage value of the second storage circuit,
The compensation signal generation circuit is a binarization circuit that outputs a compensation signal that switches between when the binarized output is inverted and when it is not inverted within a predetermined period. A binarization circuit that binarizes an input signal that varies with time,
An input terminal for inputting an input signal; a first output terminal for outputting a first output signal; a second output terminal for outputting a second output signal; a peak hold circuit; a bottom hold circuit; and an output signal generation circuit; A compensation signal generation circuit,
The peak hold circuit is connected to the input terminal, the output signal generation circuit, and the compensation signal generation circuit, and includes a first storage circuit. (1) The voltage of the input signal is greater than the storage value of the first storage circuit. (2) When the peak hold value decrease signal is input from the output signal generation circuit, the first predetermined value is subtracted from the storage value of the first storage circuit. ) When the compensation signal is input from the compensation signal generation circuit, the second predetermined value is subtracted from the storage value of the first storage circuit, and (4) the storage value of the first storage circuit is output to the output signal generation circuit.
The bottom hold circuit is connected to the input terminal, the output signal generation circuit, and the compensation signal generation circuit, and includes a second memory circuit. (1) The voltage of the input signal is higher than the memory value of the second memory circuit. Is low, the stored value of the second storage circuit is decreased. (2) When the bottom hold value increase signal is input from the output signal generation circuit, the third predetermined value is added from the stored value of the second storage circuit. ) When a compensation signal is input from the compensation signal generation circuit, the fourth predetermined value is added from the storage value of the second storage circuit, and (4) the storage value of the second storage circuit is output to the output signal generation circuit.
The output signal generation circuit is connected to the input terminal, the first output terminal, the second output terminal, the peak hold circuit, and the bottom hold circuit. (1) The stored value of the first storage circuit and the stored value of the second storage circuit A first output signal obtained by binarizing the input signal based on the threshold value calculated from the first output signal is output to the first output terminal, and (2) a second output signal delayed by a predetermined phase with respect to the first output signal is output to the second output (3) When the second output signal is inverted from one state to the other state, a peak hold value decrease signal is output to the peak hold circuit, and (4) the second output signal is one from the other state. When the state is reversed, the bottom hold value increase signal is output to the bottom hold circuit.
The compensation signal generation circuit is connected to the first output terminal, the peak hold circuit, and the bottom hold circuit, and outputs the compensation signal to the peak hold circuit and the bottom hold circuit when the first output signal is not inverted for a predetermined period. The binarization circuit according to claim 1. A determination clock signal is input, and a determination clock terminal connected to the compensation signal generation circuit is further provided.
3. The binary signal according to claim 1, wherein the compensation signal generation circuit outputs a compensation signal when the first output signal does not invert for a predetermined period determined based on the period of the determination clock signal. Circuit. A compensation clock terminal for inputting a compensation clock signal and connecting to a compensation signal generation circuit is further provided.
The compensation signal generation circuit outputs a compensation signal in synchronization with the compensation clock signal when the first output signal does not invert for a predetermined period determined based on the period of the determination clock signal. 4. The binarization circuit according to 3. The output signal generation circuit includes a threshold value operation circuit, a first comparison circuit, a second comparison circuit, a first selection circuit, a second selection circuit, a third selection circuit, and a fourth selection circuit,
The threshold calculation circuit is connected to the peak hold circuit, the bottom hold circuit, the first comparison circuit, and the second comparison circuit, and an intermediate threshold value between the storage value of the first storage circuit and the storage value of the second storage circuit, and the intermediate value thereof A high-side offset threshold value between the threshold value and the stored value of the first storage circuit, and a low-side offset threshold value between the intermediate threshold value and the stored value of the second storage circuit are calculated, and the intermediate threshold value and the high-side offset threshold value are calculated. Output to the first comparison circuit, output the intermediate threshold and the low-side offset threshold to the second comparison circuit,
The first comparison circuit is connected to the threshold value operation circuit, the input terminal, the first selection circuit, the second selection circuit, and the third selection circuit, and when the voltage of the input terminal falls below the intermediate threshold value, and the voltage of the input terminal Outputs a signal that inverts when exceeds the high-side offset threshold,
The second comparison circuit is connected to the threshold value operation circuit, the input terminal, the first selection circuit, the second selection circuit, and the fourth selection circuit, and when the voltage of the input terminal exceeds the intermediate threshold value, the voltage of the input terminal Outputs a signal that inverts when is below the low-side offset threshold,
The first selection circuit is connected to the first comparison circuit, the second comparison circuit, and the first output terminal. When the voltage of the input terminal falls below the low-side offset threshold and then rises above the intermediate threshold, Outputting a first output signal to the first output terminal that is inverted when the voltage exceeds the high-side offset threshold and then falls below the intermediate threshold;
The second selection circuit is connected to the first comparison circuit, the second comparison circuit, and the second output terminal. When the voltage at the input terminal exceeds the high-side offset threshold value, the voltage at the input terminal is set to the low-side offset threshold value. A second output signal that inverts when the output is below the second output terminal,
The third selection circuit is connected to the first comparison circuit and the peak hold circuit, and outputs to the peak hold circuit a peak hold value decrease signal that is inverted when the voltage at the input terminal exceeds the high-side offset threshold.
The fourth selection circuit is connected to the second comparison circuit and the bottom hold circuit, and outputs a bottom hold value increase signal that is inverted when the voltage of the input terminal falls below the low-side offset threshold value to the bottom hold circuit. The binarization circuit according to claim 1.

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