TWI686877B - 封裝方法以及其元件 - Google Patents
封裝方法以及其元件 Download PDFInfo
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- TWI686877B TWI686877B TW107142835A TW107142835A TWI686877B TW I686877 B TWI686877 B TW I686877B TW 107142835 A TW107142835 A TW 107142835A TW 107142835 A TW107142835 A TW 107142835A TW I686877 B TWI686877 B TW I686877B
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- metal
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- 238000000034 method Methods 0.000 title claims description 81
- 239000000758 substrate Substances 0.000 claims abstract description 97
- 239000004020 conductor Substances 0.000 claims abstract description 49
- 229910052751 metal Inorganic materials 0.000 claims description 75
- 239000002184 metal Substances 0.000 claims description 75
- 230000008569 process Effects 0.000 claims description 47
- 238000007747 plating Methods 0.000 claims description 26
- 238000004806 packaging method and process Methods 0.000 claims description 25
- 238000000151 deposition Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 9
- 238000005272 metallurgy Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 166
- 239000004065 semiconductor Substances 0.000 description 34
- 239000000463 material Substances 0.000 description 33
- 229920002120 photoresistant polymer Polymers 0.000 description 29
- 235000012431 wafers Nutrition 0.000 description 17
- 238000001465 metallisation Methods 0.000 description 13
- 238000007789 sealing Methods 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 229910000679 solder Inorganic materials 0.000 description 10
- 150000001875 compounds Chemical class 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 7
- 239000011521 glass Substances 0.000 description 7
- 239000004593 Epoxy Substances 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- 238000004528 spin coating Methods 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- 239000011162 core material Substances 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000000227 grinding Methods 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910000673 Indium arsenide Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000000109 continuous material Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- -1 tungsten nitride Chemical class 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- JPNWDVUTVSTKMV-UHFFFAOYSA-N cobalt tungsten Chemical compound [Co].[W] JPNWDVUTVSTKMV-UHFFFAOYSA-N 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- ZHPNWZCWUUJAJC-UHFFFAOYSA-N fluorosilicon Chemical class [Si]F ZHPNWZCWUUJAJC-UHFFFAOYSA-N 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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Abstract
在實施例中,一種封裝元件包括:基底,具有第一側面
以及與第一側面相對的第二側面;內連線結構,鄰近基底的第一側面;以及積體電路元件,附接至內連線結構;穿孔,自基底的第一側面延伸至基底的第二側面,穿孔電性連接至積體電路元件;凸塊下金屬,鄰近基底的第二側面且與穿孔相接觸;導電凸塊,位於凸塊下金屬上,導電凸塊以及凸塊下金屬為連續導電材料,導電凸塊自穿孔側向偏移;以及底膠,包圍凸塊下金屬以及導電凸塊。
Description
本發明的實施例是有關於一種封裝方法以及其元件。
由於積體電路(integrated circuit;IC)的發展,半導體產業由於各種電子組件(亦即,電晶體、二極體、電阻器、電容器等)的積集度(integration density)的連續改良而持續地快速增長。主要地,積集度的這些改良源自於最小特徵尺寸的逐漸減小,允許將更多組件集成至給定區域中。
這些積體改良在本質上為基本上二維(two-dimensional;2D)的,此是由於積體式組件佔據的區域基本上在半導體晶圓的表面上。積體電路的區域中的增加密度及對應區域的減小已總體上超過將積體電路晶片直接接合至基底上的能力。插入件已用以將滾珠(ball)接觸區域自晶片的滾珠接觸區域重佈至插入件的更大區域上。另外,插入件已允許包括多個晶片的三維(three-dimensional;3D)封裝。亦已研發其他封裝以結合三維態樣。
一種封裝方法包括:將積體電路元件附接至插入件的第
一側面,插入件包括電性連接至積體電路元件的穿孔;在插入件的第二側面上方沈積介電層;將介電層圖案化以暴露穿孔;在介電層上方形成第一罩幕層,第一罩幕層具有穿孔上方的第一圖案;鍍覆第一罩幕層的第一圖案中的凸塊下金屬;在凸塊下金屬以及第一罩幕層上方形成第二罩幕層,第二罩幕層具有暴露凸塊下金屬的一部分的第二圖案;鍍覆第二罩幕層的第二圖案中的導電凸塊,導電凸塊自穿孔側向偏移;以及移除第一罩幕層以及第二罩幕層。
一種封裝方法包括:在插入件上形成介電層,插入件包括穿孔;在介電層中的圖案化出開口;在開口中以及沿介電層沈積晶種層;鍍覆晶種層上的第一導電材料以形成沿介電層延伸以及延伸至開口內的凸塊下金屬,使用晶種層鍍覆第一導電材料;以及鍍覆第一導電材料上的第二導電材料以形成自穿孔側向偏移的導電凸塊,使用晶種層鍍覆第二導電材料。
一種封裝元件包括:基底,具有第一側面以及與第一側面相對的第二側面;鄰近基底的第一側面的內連線結構;以及附接至內連線結構的積體電路元件;自基底的第一側面延伸至基底的第二側面的穿孔,穿孔電性連接至積體電路元件;凸塊下金屬,鄰近基底的第二側面且與穿孔相接觸;的導電凸塊,位於凸塊下金屬上,導電凸塊以及凸塊下金屬為連續導電材料,導電凸塊自穿孔側向偏移;以及底膠,包圍凸塊下金屬以及導電凸塊。
50:積體電路元件
50A、50B:元件
52、72:基底
54、76:內連線結構
70:晶圓
74:穿孔
100:半導體元件
100A、100B:元件區
102、104、132:導電凸塊
106、136:導電連接件
108:底膠材料
110:密封體
112:載體基底
114:絕緣層
116:介電層
118、124、130:開口
120:晶種層
122:第一光阻
126:凸塊下金屬
128:第二光阻
134:可回焊材料
138:切割道區
140:插入件
200:元件封裝
202:封裝基底
204:焊墊
206:底膠
結合隨附圖式閱讀以下詳細描述會最佳地理解本揭露
的態樣。應注意,根據業界中的標準慣例,各種特徵未按比例繪製。事實上,可出於論述清楚起見而任意地增加或減小各種特徵的尺寸。
圖1為根據一些實施例的積體電路元件的橫截面視圖。
圖2為根據一些實施例的晶圓的橫截面視圖。
圖3至圖18為根據一些實施例的用以形成元件封裝的製程期間的中間步驟的各種視圖。
以下揭露內容提供用以實施本發明的不同特徵的許多不同實施例或實例。以下描述組件以及佈置的特定實例以簡化本揭露內容。當然,這些組件以及佈置僅為實例且並不意欲為限制性的。舉例而言,在以下描述中,第一特徵形成於第二特徵上方或第二特徵上可包括第一特徵以及第二特徵直接接觸地形成的實施例,且亦可包括額外特徵可形成於第一特徵與第二特徵之間以使得第一特徵與第二特徵可不直接接觸的實施例。另外,本揭露可在各種實例中重複附圖標號及/或字母。此重複是出於簡化及清楚的目的,且本身並不指示所論述的各種實施例及/或設置之間的關係。
另外,為便於描述,本文中可使用諸如「在...下面(beneath)」、「在...下方(below)」、「下部(lower)」、「在...上方(above)」、「上部(upper)」及類似者的空間相對術語以描述如在圖式中所示出的一個元件或特徵與另一元件或特徵的關係。除圖式中所描繪的定向之外,空間相對術語意欲涵蓋元件在使用或操
作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向),且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
根據一些實施例,形成凸塊下金屬(under bump metallurgy;UBM)以將隨後形成的導電連接件自插入件的穿孔側向偏移。緩衝層亦可形成於凸塊下金屬與插入件的主基底之間。因此,可減小藉由導電連接件在熱測試期間施加於插入件上的力。另外,根據一些實施例,用以形成凸塊下金屬的製程可使用單個灰化製程,使得製造成本降低。
圖1為根據一些實施例的積體電路元件50的橫截面視圖。積體電路元件50可為邏輯晶粒(例如,中央處理單元(central processing unit;CPU)、圖像處理單元(graphics processing unit;GPU)、系統晶片(system-on-a-chip;SoC)、微控制器等)、記憶體晶粒(例如,動態隨機存取記憶體(dynamic random access memory;DRAM)晶粒、靜態隨機存取記憶體(static random access memory;SRAM)晶粒等)、功率管理晶粒(例如,功率管理積體電路(power management integrated circuit;PMIC)晶粒)、射頻(radio frequency;RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system;MEMS)晶粒、訊號處理晶粒(例如,數位訊號處理(digital signal processing;DSP)晶粒)、前端晶粒(例如,類比前端(analog front-end;AFE)晶粒)、類似者,或其組合。積體電路元件50可形成於晶圓中,所述晶圓可包括在後續步驟中單體化的不同元件區以形成多個積體電路元件50。積體電路元件50包括基底52以及內連線結構54。
基底52可包括塊狀半導體基底、絕緣體上半導體(semiconductor-on-insulator;SOI)基底、多層半導體基底或類似者。基底52的半導體材料可為:矽;鍺;化合物半導體,包括矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦;合金半導體,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP;或其組合。亦可使用其他基底,諸如多層基底或梯度基底。基底52可為摻雜的或未摻雜的。元件(諸如電晶體、電容器、電阻器、二極體,及類似者)可形成於基底52的主動表面(例如,面朝上的表面)中及/或主動表面上。
具有一或多個介電層以及對應金屬化圖案的內連線結構54形成於基底52的主動表面上。所述一或多個介電層可為金屬化間介電(inter-metallization dielectric;IMD)層。金屬化間介電層可由例如低介電常數的介電材料藉由本領域中已知的任何適合的方法形成,所述低介電常數的介電材料諸如未摻雜矽酸鹽玻璃(undoped silicate glass;USG)、磷矽酸鹽玻璃(phosphosilicate glass;PSG)、硼磷矽玻璃(borophosphosilicate glass;BPSG)、氟矽酸鹽玻璃(fluorosilicate glass;FSG)、SiOxCy、旋塗玻璃、旋塗聚合物、碳化矽材料、其化合物、其複合物、其組合或類似者,所述方法諸如旋塗、化學氣相沈積(chemical vapor deposition;CVD)、電漿增強型化學氣相沉積(plasma-enhanced CVD;PECVD)、高密度電漿化學氣相沈積(high-density plasma chemical vapor deposition;HDP-CVD)或類似者。介電層中的金屬化圖案可藉由使用通孔及/或跡線而於元件之間路由(route)電訊號,且亦可含有各種電氣元件,諸如電容器、電阻器、電感器或類似者。
各種元件以及金屬化圖案可內連以執行一或多個功能。功能可包括記憶體結構、處理結構、感測器、放大器、功率分佈、輸入/輸出電路或類似者。此外,諸如導電柱或接觸墊的晶粒連接件形成於內連線結構54中及/或內連線結構54上,以提供外部電連接至電路以及元件。所屬領域中具通常知識者將瞭解,為達成說明的目的,提供以上實例。可根據適合的給定應用目的而使用其他電路。
儘管繪示為積體電路元件50具有單個基底52,但應瞭解,積體電路元件50可包括多個基底52。舉例而言,積體電路元件50可為堆疊元件,諸如混合記憶體立方體(hybrid memory cube;HMC)模組、高頻寬記憶體(high bandwidth memory;HBM)模組或類似者。在此類實施例中,積體電路元件50包括藉由通孔內連的多個基底52。
圖2為根據一些實施例的晶圓70的橫截面視圖。晶圓70包括多個元件區100A以及元件區100B,積體電路元件50將附接於元件區中以形成多個元件。形成於晶圓70中的元件可為插入件、積體電路晶粒或類似者。晶圓70包括基底72、穿孔74以及內連線結構76。
基底72可為塊狀半導體基底、絕緣體上半導體基底、多層半導體基底或類似者。基底72的半導體材料可為:矽;鍺;化合物半導體,包括矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦;合金半導體,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP;或其組合。亦可使用其他基底,諸如多層基底或梯度基底。基底72可為摻雜的或未摻雜
的。在插入件形成於晶圓70中的實施例中,基底72總體而言並不於其中包括主動元件,然而插入件可包括形成於基底72的前表面(例如,面朝上的表面)中及/或基底72的前表面上的被動元件。在積體電路晶粒形成於晶圓70中的實施例中,諸如電晶體、電容器、電阻器、二極體及類似者的元件可形成於基底72的前表面中及/或基底72的前表面上。
形成穿孔74以自基底72的前表面延伸至基底72中。當基底72為矽基底時,穿孔74有時亦稱為基底穿孔或矽穿孔(through-substrate vias/through-silicon vias;TSV)。穿孔74可藉由於基底72中形成凹部而形成,藉由例如蝕刻、碾磨、雷射技術、其組合及/或類似者以形成凹部。薄介電材料可諸如藉由使用氧化技術而形成於凹部中。薄障壁層可諸如藉由化學氣相沉積、原子層沈積(atomic layer deposition;ALD)、物理氣相沈積(physical vapor deposition;PVD)、熱氧化、其組合及/或類似者而均勻地沈積於基底72的前側上方以及開口中。障壁層可由氮化物或氮氧化物形成,所述氮化物或氮氧化物諸如氮化鈦、氮氧化鈦、氮化鉭、氮氧化鉭、氮化鎢、其組合,及/或類似者。導電材料可沈積於薄障壁層上方以及開口中。導電材料可藉由電化學鍍覆製程、化學氣相沉積、原子層沈積、物理氣相沈積、其組合及/或類似者而形成。導電材料的實例為銅、鎢、鋁、銀、金、其組合,及/或類似者。過量的導電材料以及障壁層藉由例如化學機械研磨(cnemical-mechanical polish;CMP)而自基底72的前側移除。因此,穿孔74可包括導電材料,其中薄障壁層位於導電材料與基底72之間。
內連線結構76形成於基底72的前表面上方,且用以將積體電路元件(若存在)及/或穿孔74電性連接在一起,及/或電性連接至外部元件。內連線結構76可包括一或多個介電層以及介電層中的對應金屬化圖案。金屬化圖案可包括通孔及/或跡線以將任何元件及/或穿孔74內連在一起,及/或內連至外部元件。介電層可由氧化矽、氮化矽、碳化矽、氮氧化矽、低介電常數介電材料形成,所述低介電常數介電材料諸如磷矽酸鹽玻璃、硼磷矽玻璃、氟矽酸鹽玻璃、SiOxCy、旋塗玻璃、旋塗聚合物、矽碳材料、其化合物、其複合物、其組合或類似者。介電層可藉由所屬領域中已知的任何適合的方法而沈積,所述方法諸如旋塗、化學氣相沉積、電漿增強型化學氣相沉積、高密度電漿化學氣相沈積或類似者。金屬化圖案可形成於介電層中,例如藉由使用微影技術以在介電層上將光阻材料沈積以及圖案化,以暴露介電層成為金屬化圖案的部分。諸如非等向性乾式蝕刻製程的蝕刻製程可用以於介電層中產生凹部及/或開口,對應地暴露部分的介電層。凹部及/或開口可襯墊有擴散障壁層且使用導電材料填充。擴散障壁層可由藉由原子層沈積或類似者而沈積的氮化鉭、鉭、氮化鈦、鈦、鎢化鈷或類似者的一或多個層而形成,以及導電材料可由銅、鋁、鎢、銀、其組合或類似者形成,且可藉由化學氣相沉積、物理氣相沈積或類似者而沈積。介電層上的任何過量的擴散障壁層及/或導電材料可諸如藉由使用化學機械研磨而移除。
圖3至圖18為根據一些實施例的用以形成元件封裝200的製程期間的中間步驟的各種視圖。圖3至圖18為橫截面視圖。在圖3至圖16中,半導體元件100藉由將各種積體電路元件50
接合至晶圓70的前側而形成。在實施例中,半導體元件100為晶圓上晶片(chip-on-wafer;CoW)封裝,然而應瞭解,實施例可應用於其他三維積體電路(three-dimensional integrated circuit;3DIC)封裝。圖17繪示所得的半導體元件100。在圖18中,元件封裝200藉由將半導體元件100安裝至基底而形成。在實施例中,元件封裝200為基底上晶圓上晶片(chip-on-wafer-on-substrate;CoWoS)封裝,然而應瞭解,實施例可應用於其他三維積體電路封裝。
在圖3中,多個積體電路元件50附接至內連線結構76。積體電路元件50位於元件區100A以及元件區100B中,所述元件區100A以及元件區100B將在後續步驟中單體化以形成半導體元件100。積體電路元件50包括具有不同功能的多個元件50A以及元件50B。元件50A以及元件50B可各具有單個功能(例如,邏輯元件、記憶體晶粒等),或可具有多個功能(例如,系統晶片)。在實施例中,元件50A為諸如中央處理單元的邏輯元件,以及元件50B為諸如高頻寬記憶體模組的記憶體元件。積體電路元件50可使用例如取放工具而附接至內連線結構76。
在所繪示的實施例中,積體電路元件50藉由連接件而附接至內連線結構76,所述連接件包括導電凸塊102以及導電凸塊104,以及導電連接件106。導電凸塊102以及導電凸塊104由諸如銅、鋁、金、鎳、鈀、類似者或其組合的導電材料而形成,以及可藉由濺鍍、列印、電鍍、無電式鍍覆、化學氣相沉積或類似者而形成。導電凸塊102以及導電凸塊104可無焊料(solder-free)且具有實質上豎直的側壁,且可稱為μ凸塊。導電凸塊102電性
地以及實體地連接至內連線結構54,且導電凸塊104電性地以及實體地連接至內連線結構76。導電連接件106接合導電凸塊102以及導電凸塊104。導電連接件106可由諸如焊料的導電材料形成,且可藉由在導電凸塊102或導電凸塊104上初始地形成一層焊料而形成,經由諸如蒸鍍、電鍍、列印、焊料轉移、植球或類似者的方法而初始地形成所述焊料。一旦焊料層形成,則可執行回焊製程以便將導電連接件106塑形為所需的凸塊形狀。
在其他實施例中,積體電路元件50藉由面對面接合而附接至內連線結構76。舉例而言,混合接合、熔合接合、直接接合、介電接合、金屬接合或類似者可用以附接內連線結構54以及內連線結構76,而不使用焊料。另外,可使用接合技術的混合,例如,一些積體電路元件50可藉由導電連接件106而接合至內連線結構76,且其他積體電路元件50可藉由面對面接合而接合至內連線結構76。
在圖4中,底膠材料108配置至積體電路元件50與內連線結構76之間的間隙中。底膠材料108包圍導電凸塊102及導電凸塊104以及導電連接件106,且可沿積體電路元件50的側壁向上延伸。底膠材料108可為任何可接受的材料,諸如聚合物、環氧基、模塑底膠或類似者。底膠材料108可藉由將積體電路元件50附接至內連線結構76之後的毛細管流製程(capillary flow process)而形成,或可藉由附接積體電路元件50之前的適合的沈積方法而形成。
在圖5中,密封體110形成於各種組件上。密封體110可為模塑複合物、環氧基或類似者,且可藉由壓縮模塑、轉移模
塑或類似者而應用。密封體110可形成於內連線結構76上方,以使得積體電路元件50以及底膠材料108被掩埋或覆蓋。密封體110隨後固化。在一些實施例中,密封體110變薄以使得密封體110的頂部表面與積體電路元件50的頂部表面齊平。
在圖6中,中間結構翻轉以準備處理基底72的背側。中間結構可置放於載體基底112上或其他適合的支撐結構上以用於後續處理。舉例而言,載體基底112可附接至密封體110。中間結構可藉由釋放層而附接至載體基底112。釋放層可由聚合物類材料形成,所述聚合物類材料可連同載體基底112一起自上覆結構移除。在一些實施例中,載體基底112為諸如塊狀半導體或玻璃基底的基底,且可具有任何厚度,諸如約30毫米的厚度。在一些實施例中,釋放層為在加熱時失去其黏著特性的環氧類熱釋放材料,諸如光-熱轉換(light-to-heat-conversion;LTHC)釋放塗佈。
在圖7中,基底72變薄以暴露穿孔74,以使得穿孔74自基底72的背側凸起。穿孔74的暴露可於兩步驟薄化製程中完成。首先,可執行研磨製程,直至穿孔74暴露。研磨製程可為例如化學機械研磨或其他可接受的移除製程。在研磨製程之後,基底72的背側與穿孔74可齊平。其次,可執行凹進製程以使穿孔74周圍的基底72凹進。凹進製程可為例如適合的回蝕刻製程。
在圖8中,絕緣層114形成於基底72的背側上,包圍穿孔74的凸起部分。在一些實施例中,絕緣層114由含矽絕緣體形成,諸如氮化矽、氧化矽、氮氧化矽或類似者,且可藉由諸如旋塗、化學氣相沉積、電漿增強型化學氣相沉積、高密度電漿化學氣相沈積或類似者的適合的沈積方法而形成。在沈積之後,可執
行諸如化學機械研磨的平面化製程以移除過量的介電材料,以使得絕緣層114的表面與穿孔74的表面齊平。
在圖9中,介電層116形成於絕緣層114以及穿孔74上方。介電層116可為可使用微影罩幕以圖案化的感光性聚合物材料,諸如聚苯并噁唑(polybenzoxazole;PBO)、聚醯亞胺、苯環丁烯(benzocyclobutene;BCB)或類似者。在其他實施例中,介電層116由氮化物、氧化物或類似者形成,所述氮化物諸如氮化矽,所述氧化物諸如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃(borosilicate glass;BSG)、硼磷矽玻璃。介電層116可藉由旋塗、層壓、化學氣相沉積、類似者或其組合形成。
介電層116隨後圖案化。圖案化形成開口118的圖案以暴露穿孔74的部分。圖案化可藉由可接受的製程而進行,諸如藉由當介電層116為感光性材料時將介電層116曝光,或藉由使用例如非等向性蝕刻的蝕刻。若介電層116為感光性材料,則介電層116可在曝光之後顯影。
在圖10中,晶種層120形成於介電層116上方以及形成於經由介電層116形成的開口118中。在一些實施例中,晶種層為金屬層,所述金屬層可為單層或具有由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層以及鈦層上方的銅層。晶種層可使用例如物理氣相沉積或類似者而形成。
在圖11中,第一光阻122在晶種層120上形成以及圖案化。第一光阻122可藉由旋塗或類似者而形成且可曝光以圖案化。第一光阻122的圖案對應於將隨後形成的凸塊下金屬。圖案化形成穿過第一光阻122的開口124的圖案,從而暴露晶種層120的
部分。開口124亦暴露開口118,且位於穿孔74上方。
在圖12中,導電材料形成於第一光阻122的開口124中,位於晶種層120的暴露部分上。導電材料可藉由鍍覆形成,所述鍍覆諸如電鍍或無電式鍍覆或類似者。導電材料可為金屬,如銅、鈦、鎢、鋁或類似者。導電材料與晶種層120的組合形成凸塊下金屬126。凸塊下金屬126具有延伸穿過介電層116中的開口118的通孔部分以接觸晶種層120,且具有沿介電層116的頂部表面延伸的線部分。
在圖13中,第二光阻128在凸塊下金屬126以及第一光阻122上形成以及圖案化。第二光阻128可藉由旋塗或類似者而形成,且可曝光以圖案化。第二光阻128可由與第一光阻122相同的材料形成。第二光阻128的圖案對應於將隨後形成的導電凸塊。圖案化形成穿過第二光阻128的開口130的圖案,從而暴露凸塊下金屬126的部分。
在圖14中,導電材料形成於第二光阻128的開口130中,位於凸塊下金屬126的暴露部分上,藉此形成導電凸塊132。導電材料可藉由鍍覆形成,所述鍍覆諸如電鍍或無電式鍍覆或類似者。導電材料可為金屬,如銅、鈦、鎢、鋁或類似者。由於凸塊下金屬126藉由開口130而暴露,因此沒有晶種層形成於開口130中。實際上,導電材料直接地以及實體地形成於凸塊下金屬126上。導電材料藉由執行鍍覆製程而形成,所述鍍覆製程與用以形成凸塊下金屬126的導電材料的鍍覆製程具有相同的鍍覆製程參數。值得注意的是,沒有晶種層形成於凸塊下金屬126與導電凸塊132之間。實際上,導電凸塊132的導電材料藉由使用晶種層
120執行鍍覆製程而形成。
另外,可回焊材料134形成於第二光阻128的開口130中的導電凸塊132上。可回焊材料134為諸如焊料、錫、銀或類似者的材料,且可藉由鍍覆、蒸鍍、電鍍、列印、焊料轉移或類似者而形成。由於沒有晶種層形成於凸塊下金屬126與導電凸塊132之間,因此導電凸塊132為自凸塊下金屬126連續延伸至可回焊材料134的導電材料。
在圖15中,第一光阻122以及第二光阻128藉由可接受的灰化製程或剝離製程而移除,諸如使用氧電漿或類似者。值得注意的是,第一光阻122以及第二光阻128在同一移除製程中移除,第二光阻128的移除與第一光阻122的移除之間無介入步驟。在同一製程中移除所述第一光阻以及所述第二光阻允許降低移除成本。一旦移除所述第一光阻以及所述第二光阻,則諸如藉由使用可接受的蝕刻製程(諸如藉由濕式蝕刻或乾式蝕刻)來移除晶種層120的暴露部分。
另外,可執行回焊以便將可回焊材料134塑形成所需凸塊形狀,藉此形成導電連接件136。導電連接件136可為球柵陣列(ball grid array;BGA)連接件、焊料球、受控塌陷晶片連接(controlled collapse chip connection;C4)凸塊或類似者。
凸塊下金屬126使導電凸塊132以及導電連接件136自穿孔74側向偏移。換言之,導電凸塊132以及導電連接件136沿第一軸對準,且穿孔74沿不同的第二軸對準。另外,介電層116的聚合物材料充當絕緣層114與凸塊下金屬126之間的緩衝層。在熱測試期間,元件可循環地加熱以及冷卻,使導電連接件136
反覆膨脹以及收縮。緩衝層吸收由導電連接件136膨脹產生的力,從而降低內連線結構76的各種層在熱測試期間開裂及/或分層的幾率。另外,根據一些實施例,凸塊下金屬126以及導電凸塊132僅使用一個晶種層、一個光阻移除製程以及一個晶種層移除製程而形成。因此,可降低凸塊下金屬126以及緩衝介電層116的製造成本。
在圖16中,執行載體剝離以使載體基底112自密封體110拆離(剝離)。根據一些實施例,剝離包括將諸如雷射光或紫外線(ultraviolet;UV)光的光投射於釋放層上,以使釋放層在光的熱量下分解且可移除載體基底112。所述結構隨後翻轉且置放於載帶(tape)(未示出)上。隨後,晶圓70在鄰近的元件區100A與元件區100B之間沿切割道區138而單體化,以形成半導體元件100。單體化可藉由鋸切、切割或類似者而進行。
圖17繪示在單體化之後所得的半導體元件100。在單體化製程期間,形成插入件140,所述插入件包括晶圓70的單體化部分、絕緣層114、介電層116以及凸塊下金屬126。半導體元件100中的每一者均具有插入件140。藉由單體化製程,插入件140的邊緣與密封體110的邊緣毗連(coterminous)。換言之,插入件140的外側壁與密封體110的外側壁具有相同寬度。
在圖18中,元件封裝200藉由將半導體元件100安裝至封裝基底202而形成。封裝基底202可由諸如矽、鍺或類似者的半導體材料製成。或者,亦可使用化合物材料,諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、矽鍺碳化物、磷化砷化鎵、磷化鎵銦、這些的組合及類似者。此外,封裝基底202可為絕緣體上
半導體基底。一般而言,絕緣體上半導體基底包括半導體材料層,所述半導體材料諸如磊晶矽、鍺、矽鍺、絕緣體上半導體或其組合。在一個替代實施例中,封裝基底202基於諸如玻璃纖維強化樹脂芯的絕緣芯。一個實例芯材料為例如是FR4的玻璃纖維樹脂。芯材料的替代物包括雙馬來亞醯胺三嗪(bismaleimide-triazine;BT)樹脂,或替代地包括其他印刷電路板(printed circuit board;PCB)材料或膜。諸如味素累積膜(Ajinomoto build-up film;ABF)的累積膜或其他疊層物可用於封裝基底202。
封裝基底202可包括主動元件以及被動元件。所屬領域中具通常知識者將認識到,諸如電晶體、電容器、電阻器、這些的組合及類似者的廣泛多種元件可用以生成產生元件封裝200的設計的結構要求以及功能要求。元件可使用任何適合的方法形成。
封裝基底202亦可包括金屬化層以及通孔,以及金屬化層以及通孔上方的焊墊204。金屬化層可形成於主動元件以及被動元件上方,且設計以連接各種元件以形成功能電路。金屬化層可由介電質(例如,低介電常數介電材料)以及導電材料(例如,銅)的交替層形成,其中通孔內連導電材料層,且可經由任何適合的製程(諸如沈積、鑲嵌、雙鑲嵌或類似者)而形成。在一些實施例中,封裝基底202實質上不含主動元件以及被動元件。
導電連接件136回焊以將半導體元件100附接至焊墊204,藉此將插入件140接合至封裝基底202。導電連接件136將封裝基底202(包括封裝基底202中的金屬化層)電性地以及實體地耦接至半導體元件100。在一些實施例中,可在將被動元件(例如,表面安裝元件(surface mount devices;SMD),未示出)安裝
於封裝基底202上之前將被動元件附接至元件封裝200(例如,接合至焊墊204)。在此類實施例中,被動元件可與導電連接件136一樣接合至第二元件封裝200的同一表面。
在使用半導體元件100附接至封裝基底202之後剩餘的環氧基焊劑的環氧基部分中的至少一些回焊導電連接件136之前,導電連接件136可具有環氧基焊劑形成於其上。此剩餘環氧基部分可充當底膠以減小應力且保護由導電連接件136的回焊而產生的接合點。
底膠206可形成於半導體元件100與封裝基底202之間,包圍導電連接件136、導電凸塊132以及凸塊下金屬126。歸因於用以形成凸塊下金屬126的製程,導電連接件136、導電凸塊132以及凸塊下金屬126在形成後未由介電層或絕緣層包圍。如此,底膠206與凸塊下金屬126的側壁直接接觸且沿凸塊下金屬126的側壁延伸。另外,底膠206為自封裝基底202延伸至介電層116的連續材料。底膠206可藉由附接半導體元件100後的毛細管流製程而形成,或可藉由附接半導體元件100前的適合的沈積方法而形成。
視需要,散熱片可附接至元件封裝200,覆蓋以及包圍半導體元件100。散熱片可由諸如鋼、不鏽鋼、銅、類似者或其組合的具有高熱導率的材料形成。散熱片保護半導體元件100且形成熱途徑以自元件封裝200的各種組件傳導熱量。
實施例可達成一些優點。藉由使用凸塊下金屬126以將導電連接件136自穿孔74側向偏移,導電連接件136並不在熱測試(例如,膨脹)期間對穿孔74施加力。另外,介電層116充當
凸塊下金屬126的緩衝層。其結果是,可減小內連線結構76的各種層在熱測試期間裂開及/或分層的幾率。另外,由於凸塊下金屬126以及導電凸塊132僅使用一個晶種層、一個光阻移除製程以及一個晶種層移除製程而形成,因此可降低製造成本。
在實施例中,一種封裝方法包括:將積體電路元件附接至插入件的第一側面,插入件包括電性連接至積體電路元件的穿孔;在插入件的第二側面上方沈積介電層;將介電層圖案化以暴露穿孔;在介電層上方形成第一罩幕層,第一罩幕層具有穿孔上方的第一圖案;鍍覆第一罩幕層的第一圖案中的凸塊下金屬;在凸塊下金屬以及第一罩幕層上方形成第二罩幕層,第二罩幕層具有暴露凸塊下金屬的一部分的第二圖案;鍍覆第二罩幕層的第二圖案中的導電凸塊,導電凸塊自穿孔側向偏移;以及移除第一罩幕層以及第二罩幕層。
在所述封裝方法的一些實施例中,在同一移除製程中移除第一罩幕層以及第二罩幕層。在一些實施例中,所述方法更包括:在積體電路元件與插入件之間形成底膠材料。在一些實施例中,所述方法更包括:使用模塑化合物密封積體電路元件以及底膠材料,模塑化合物與插入件毗連。在所述方法的一些實施例中,將介電層圖案化以形成暴露穿孔的第一開口,且所述方法更包括:在介電層上方以及第一開口中沈積晶種層,第一罩幕層形成於晶種層上方,第一圖案暴露晶種層。在所述方法的一些實施例中,沒有晶種層形成於凸塊下金屬與導電凸塊之間。在所述方法的一些實施例中,使用第一鍍覆製程鍍覆凸塊下金屬,使用第二鍍覆製程鍍覆導電凸塊,且第一鍍覆製程與第二鍍覆製程以相同
鍍覆製程參數執行。在一些實施例中,所述方法更包括:鍍覆第二罩幕層的第二圖案中的導電凸塊上的可回焊材料。在一些實施例中,所述方法更包括:在移除第一罩幕層以及第二罩幕層之後,將可回焊材料回焊以在導電凸塊上形成導電連接件。
在實施例中,一種封裝方法包括:在插入件上形成介電層,插入件包括穿孔;在介電層中的圖案化出開口;在開口中以及沿介電層沈積晶種層;鍍覆晶種層上的第一導電材料以形成沿介電層延伸以及延伸至開口內的凸塊下金屬,使用晶種層鍍覆第一導電材料;以及鍍覆第一導電材料上的第二導電材料以形成自穿孔側向偏移的導電凸塊,使用晶種層鍍覆第二導電材料。
在一些實施例中,所述方法更包括:在介電層上方形成第一罩幕層,第一罩幕層具有暴露晶種層的第一圖案,第一導電材料在第一圖案中鍍覆;以及在凸塊下金屬以及第一罩幕層上方形成第二罩幕層,第二罩幕層具有暴露凸塊下金屬的一部分的第二圖案,在第二圖案中鍍覆第二導電材料。在一些實施例中,所述方法更包括:在同一移除製程中移除第一罩幕層以及第二罩幕層。在所述方法的一些實施例中,在鍍覆第二導電材料之前沒有晶種層形成於凸塊下金屬上。在一些實施例中,所述方法更包括:使用導電連接件將導電凸塊接合至封裝基底;以及形成包圍凸塊下金屬、導電凸塊以及導電連接件的底膠。
在實施例中,一種封裝元件包括:基底,具有第一側面以及與第一側面相對的第二側面;鄰近基底的第一側面的內連線結構;以及附接至內連線結構的積體電路元件;自基底的第一側面延伸至基底的第二側面的穿孔,穿孔電性連接至積體電路元
件;凸塊下金屬,鄰近基底的第二側面且與穿孔相接觸;的導電凸塊,位於凸塊下金屬上,導電凸塊以及凸塊下金屬為連續導電材料,導電凸塊自穿孔側向偏移;以及底膠,包圍凸塊下金屬以及導電凸塊。
在所述元件的一些實施例中,底膠與凸塊下金屬的側面以及導電凸塊的側面相接觸。在一些實施例中,所述元件更包括:鄰近基底的第二側面的介電層,凸塊下金屬延伸穿過介電層。在一些實施例中,所述元件更包括:晶種層,延伸穿過介電層以與穿孔相接觸,凸塊下金屬與晶種層相接觸,其中沒有晶種層安置於導電凸塊與凸塊下金屬之間。在一些實施例中,所述元件更包括:封裝基底;以及導電連接件,將封裝基底接合至導電凸塊,底膠包圍導電連接件。在所述元件的一些實施例中,底膠為自封裝基底延伸至介電層的連續材料。
前文概述若干實施例的特徵,以使所屬領域中具通常知識者可更好地理解本揭露的態樣。所屬領域中具通常知識者應理解,其可易於使用本揭露作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優勢的其他製程以及結構的基礎。所屬領域中具通常知識者亦應認識到,此類等效構造並不脫離本揭露的精神及範疇,且所屬領域中具通常知識者可在不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
70:晶圓
72:基底
74:穿孔
76:內連線結構
100A、100B:元件區
Claims (10)
- 一種封裝方法,包括:將積體電路元件附接至插入件的第一側面,所述插入件包括穿孔,所述穿孔電性連接至所述積體電路元件;在所述插入件的第二側面上方沈積介電層;將所述介電層圖案化以暴露所述穿孔;在所述介電層上方形成第一罩幕層,所述第一罩幕層在所述穿孔上方具有第一圖案;鍍覆所述第一罩幕層的所述第一圖案中的凸塊下金屬;在所述凸塊下金屬以及所述第一罩幕層上方形成第二罩幕層,所述第二罩幕層具有暴露所述凸塊下金屬的一部分的第二圖案;鍍覆所述第二罩幕層的所述第二圖案中的導電凸塊,所述導電凸塊自所述穿孔側向偏移;以及移除所述第一罩幕層以及所述第二罩幕層。
- 如申請專利範圍第1項所述的封裝方法,其中在同一移除製程中移除所述第一罩幕層以及所述第二罩幕層。
- 如申請專利範圍第1項所述的封裝方法,其中沒有晶種層形成於所述凸塊下金屬與所述導電凸塊之間。
- 一種封裝方法,包括:在插入件上形成介電層,所述插入件包括穿孔;在所述介電層中圖案化出開口;在所述開口中以及沿所述介電層沈積晶種層;鍍覆所述晶種層上的第一導電材料以形成凸塊下金屬,所述 凸塊下金屬沿所述介電層延伸以及延伸穿過所述開口,使用所述晶種層鍍覆所述第一導電材料;以及鍍覆所述第一導電材料上的第二導電材料以形成自所述穿孔側向偏移的導電凸塊,使用所述晶種層鍍覆所述第二導電材料。
- 如申請專利範圍第4項所述的封裝方法,更包括:在所述介電層上方形成第一罩幕層,所述第一罩幕層具有暴露所述晶種層的第一圖案,在所述第一圖案中鍍覆所述第一導電材料;以及在所述凸塊下金屬以及所述第一罩幕層上方形成第二罩幕層,所述第二罩幕層具有暴露所述凸塊下金屬的一部分的第二圖案,在所述第二圖案中鍍覆所述第二導電材料。
- 如申請專利範圍第5項所述的封裝方法,更包括:在同一移除製程中移除所述第一罩幕層以及所述第二罩幕層。
- 如申請專利範圍第5項所述的封裝方法,其中在所述鍍覆所述第二導電材料之前,沒有晶種層形成於所述凸塊下金屬上。
- 一種封裝元件,包括:基底,具有第一側面以及與所述第一側面相對的第二側面;內連線結構,鄰近所述基底的所述第一側面;以及積體電路元件,附接至所述內連線結構;穿孔,自所述基底的所述第一側面延伸至所述基底的所述第二側面,所述穿孔電性連接至所述積體電路元件;凸塊下金屬,鄰近所述基底的所述第二側面且與所述穿孔相接觸; 導電凸塊,位於所述凸塊下金屬上,所述導電凸塊以及所述凸塊下金屬為連續導電材料,所述導電凸塊自所述穿孔側向偏移;晶種層,設置於所述穿孔上且所述凸塊下金屬藉由所述晶種層與所述穿孔連接;以及底膠,包圍所述凸塊下金屬以及所述導電凸塊。
- 如申請專利範圍第8項的封裝元件,更包括:介電層,鄰近所述基底的所述第二側面,所述凸塊下金屬延伸穿過所述介電層。
- 如申請專利範圍第9項的封裝元件,其中所述晶種層延伸穿過所述介電層以與所述穿孔相接觸,所述凸塊下金屬與所述晶種層相接觸,其中沒有晶種層安置於所述導電凸塊與所述凸塊下金屬之間。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11625523B2 (en) | 2016-12-14 | 2023-04-11 | iCometrue Company Ltd. | Logic drive based on standard commodity FPGA IC chips |
US10489544B2 (en) | 2016-12-14 | 2019-11-26 | iCometrue Company Ltd. | Logic drive based on standard commodity FPGA IC chips |
US10447274B2 (en) | 2017-07-11 | 2019-10-15 | iCometrue Company Ltd. | Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells |
US10957679B2 (en) | 2017-08-08 | 2021-03-23 | iCometrue Company Ltd. | Logic drive based on standardized commodity programmable logic semiconductor IC chips |
US10630296B2 (en) | 2017-09-12 | 2020-04-21 | iCometrue Company Ltd. | Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells |
US10608642B2 (en) | 2018-02-01 | 2020-03-31 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells |
US10623000B2 (en) | 2018-02-14 | 2020-04-14 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips |
US10608638B2 (en) | 2018-05-24 | 2020-03-31 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips |
KR102538178B1 (ko) * | 2018-08-22 | 2023-05-31 | 삼성전자주식회사 | 유기 인터포저를 포함하는 반도체 패키지 |
US11309334B2 (en) | 2018-09-11 | 2022-04-19 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells |
US10892011B2 (en) | 2018-09-11 | 2021-01-12 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells |
US10937762B2 (en) | 2018-10-04 | 2021-03-02 | iCometrue Company Ltd. | Logic drive based on multichip package using interconnection bridge |
US11616046B2 (en) | 2018-11-02 | 2023-03-28 | iCometrue Company Ltd. | Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip |
US11211334B2 (en) | 2018-11-18 | 2021-12-28 | iCometrue Company Ltd. | Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip |
US11158552B2 (en) | 2018-12-26 | 2021-10-26 | AP Memory Technology Corp. | Semiconductor device and method to manufacture the same |
US11380614B2 (en) | 2018-12-26 | 2022-07-05 | AP Memory Technology Corp. | Circuit assembly |
US10811402B2 (en) | 2018-12-26 | 2020-10-20 | AP Memory Technology Corp. | Memory device and microelectronic package having the same |
US11672111B2 (en) | 2018-12-26 | 2023-06-06 | Ap Memory Technology Corporation | Semiconductor structure and method for manufacturing a plurality thereof |
US11417628B2 (en) | 2018-12-26 | 2022-08-16 | Ap Memory Technology Corporation | Method for manufacturing semiconductor structure |
US11133282B2 (en) * | 2019-05-31 | 2021-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | COWOS structures and methods forming same |
US10985154B2 (en) | 2019-07-02 | 2021-04-20 | iCometrue Company Ltd. | Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits |
US11227838B2 (en) | 2019-07-02 | 2022-01-18 | iCometrue Company Ltd. | Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits |
DE102019211371A1 (de) * | 2019-07-30 | 2021-02-04 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zum Herstellen eines elektronischen Schaltungsbauelements und elektronisches Schaltungsbauelement |
US11887930B2 (en) | 2019-08-05 | 2024-01-30 | iCometrue Company Ltd. | Vertical interconnect elevator based on through silicon vias |
US11637056B2 (en) | 2019-09-20 | 2023-04-25 | iCometrue Company Ltd. | 3D chip package based on through-silicon-via interconnection elevator |
US11282772B2 (en) * | 2019-11-06 | 2022-03-22 | Advanced Semiconductor Engineering, Inc. | Package structure, assembly structure and method for manufacturing the same |
KR20210087337A (ko) * | 2020-01-02 | 2021-07-12 | 삼성전자주식회사 | 반도체 패키지와 이를 구비하는 전자 장치 및 반도체 패키지의 제조방법 |
US11600526B2 (en) | 2020-01-22 | 2023-03-07 | iCometrue Company Ltd. | Chip package based on through-silicon-via connector and silicon interconnection bridge |
US11495472B2 (en) * | 2020-04-16 | 2022-11-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semicondutor packages and methods of forming same |
CN113629048A (zh) * | 2020-05-07 | 2021-11-09 | 爱普科技股份有限公司 | 半导体结构及制造多个半导体结构的方法 |
US11728254B2 (en) * | 2020-05-22 | 2023-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Giga interposer integration through chip-on-wafer-on-substrate |
US11502015B2 (en) * | 2020-05-28 | 2022-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and manufacturing method thereof |
KR20220000294A (ko) | 2020-06-25 | 2022-01-03 | 삼성전자주식회사 | 반도체 패키지 |
US11424191B2 (en) * | 2020-06-30 | 2022-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices and methods of manufacture |
US11652037B2 (en) * | 2020-07-31 | 2023-05-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method of manufacture |
US11990443B2 (en) * | 2020-08-17 | 2024-05-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor die package and method of manufacture |
US11469197B2 (en) * | 2020-08-26 | 2022-10-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit package and method |
TWI778615B (zh) * | 2021-05-06 | 2022-09-21 | 強茂股份有限公司 | 晶圓等級半導體封裝元件的製作方法及其所製作的半導體封裝元件 |
US11901256B2 (en) * | 2021-08-31 | 2024-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device, semiconductor package, and methods of manufacturing the same |
CN116845038B (zh) * | 2023-08-29 | 2023-12-22 | 之江实验室 | 一种针对晶圆级处理器的散热装置及其制备方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201724382A (zh) * | 2015-12-31 | 2017-07-01 | 矽品精密工業股份有限公司 | 電子封裝件及其製法與基板結構 |
TWM548889U (zh) * | 2017-04-26 | 2017-09-11 | 宏濂科技股份有限公司 | 埋入式基板封裝結構 |
TW201737455A (zh) * | 2016-04-11 | 2017-10-16 | 南亞科技股份有限公司 | 半導體裝置及其製造方法 |
Family Cites Families (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3440070B2 (ja) * | 2000-07-13 | 2003-08-25 | 沖電気工業株式会社 | ウェハー及びウェハーの製造方法 |
JP4130158B2 (ja) * | 2003-06-09 | 2008-08-06 | 三洋電機株式会社 | 半導体装置の製造方法、半導体装置 |
JP3929966B2 (ja) * | 2003-11-25 | 2007-06-13 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
WO2008105535A1 (ja) * | 2007-03-01 | 2008-09-04 | Nec Corporation | 半導体装置及びその製造方法 |
US8759964B2 (en) * | 2007-07-17 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level package structure and fabrication methods |
US8039303B2 (en) * | 2008-06-11 | 2011-10-18 | Stats Chippac, Ltd. | Method of forming stress relief layer between die and interconnect structure |
US7928534B2 (en) * | 2008-10-09 | 2011-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bond pad connection to redistribution lines having tapered profiles |
US7956442B2 (en) * | 2008-10-09 | 2011-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside connection to TSVs having redistribution lines |
US7838337B2 (en) * | 2008-12-01 | 2010-11-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming an interposer package with through silicon vias |
US7741148B1 (en) * | 2008-12-10 | 2010-06-22 | Stats Chippac, Ltd. | Semiconductor device and method of forming an interconnect structure for 3-D devices using encapsulant for structural support |
US8736050B2 (en) * | 2009-09-03 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Front side copper post joint structure for temporary bond in TSV application |
US8531015B2 (en) * | 2009-03-26 | 2013-09-10 | Stats Chippac, Ltd. | Semiconductor device and method of forming a thin wafer without a carrier |
US8759949B2 (en) | 2009-04-30 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer backside structures having copper pillars |
US8445329B2 (en) * | 2009-09-30 | 2013-05-21 | Ati Technologies Ulc | Circuit board with oval micro via |
US10297550B2 (en) * | 2010-02-05 | 2019-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D IC architecture with interposer and interconnect structure for bonding dies |
CN102169875B (zh) * | 2010-02-26 | 2013-04-17 | 台湾积体电路制造股份有限公司 | 半导体装置及其制造方法 |
US8283781B2 (en) * | 2010-09-10 | 2012-10-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having pad structure with stress buffer layer |
US8993377B2 (en) * | 2010-09-29 | 2015-03-31 | Stats Chippac, Ltd. | Semiconductor device and method of bonding different size semiconductor die at the wafer level |
US8105875B1 (en) * | 2010-10-14 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Approach for bonding dies onto interposers |
US8338945B2 (en) * | 2010-10-26 | 2012-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Molded chip interposer structure and methods |
US8797057B2 (en) | 2011-02-11 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Testing of semiconductor chips with microbumps |
US8829676B2 (en) * | 2011-06-28 | 2014-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for wafer level package |
US20130040423A1 (en) * | 2011-08-10 | 2013-02-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of Multi-Chip Wafer Level Packaging |
US9142510B2 (en) * | 2011-10-28 | 2015-09-22 | Intel Corporation | 3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach |
US8643148B2 (en) | 2011-11-30 | 2014-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip-on-Wafer structures and methods for forming the same |
US8680647B2 (en) * | 2011-12-29 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with passive devices and methods of forming the same |
US8698308B2 (en) * | 2012-01-31 | 2014-04-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structural designs to minimize package defects |
US8741691B2 (en) * | 2012-04-20 | 2014-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating three dimensional integrated circuit |
US9142517B2 (en) * | 2012-06-05 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding mechanisms for semiconductor wafers |
US9443783B2 (en) | 2012-06-27 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC stacking device and method of manufacture |
KR101411813B1 (ko) * | 2012-11-09 | 2014-06-27 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
US9299649B2 (en) | 2013-02-08 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US8993380B2 (en) | 2013-03-08 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for 3D IC package |
US9087821B2 (en) * | 2013-07-16 | 2015-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding with through substrate via (TSV) |
US9633869B2 (en) | 2013-08-16 | 2017-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with interposers and methods for forming the same |
US9543373B2 (en) * | 2013-10-23 | 2017-01-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and manufacturing method thereof |
US9184128B2 (en) * | 2013-12-13 | 2015-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC package and methods of forming the same |
US9281254B2 (en) | 2014-02-13 | 2016-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming integrated circuit package |
US9418877B2 (en) * | 2014-05-05 | 2016-08-16 | Qualcomm Incorporated | Integrated device comprising high density interconnects in inorganic layers and redistribution layers in organic layers |
US9425126B2 (en) | 2014-05-29 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy structure for chip-on-wafer-on-substrate |
US9496189B2 (en) | 2014-06-13 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked semiconductor devices and methods of forming same |
US9425096B2 (en) * | 2014-07-14 | 2016-08-23 | Qualcomm Incorporated | Air gap between tungsten metal lines for interconnects with reduced RC delay |
US9449908B2 (en) * | 2014-07-30 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package system and method |
US10325853B2 (en) * | 2014-12-03 | 2019-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor packages having through package vias |
KR101654518B1 (ko) * | 2015-01-30 | 2016-09-06 | 앰코 테크놀로지 코리아 주식회사 | 칩 적층형 반도체 패키지 및 이의 제조 방법 |
US9461018B1 (en) | 2015-04-17 | 2016-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out PoP structure with inconsecutive polymer layer |
US9666502B2 (en) | 2015-04-17 | 2017-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Discrete polymer in fan-out packages |
US9735131B2 (en) | 2015-11-10 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-stack package-on-package structures |
US9786617B2 (en) * | 2015-11-16 | 2017-10-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip packages and methods of manufacture thereof |
US10147682B2 (en) * | 2015-11-30 | 2018-12-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure for stacked logic performance improvement |
US9899342B2 (en) * | 2016-03-15 | 2018-02-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated fan-out package, redistribution circuit structure, and method of fabricating the same |
US9793246B1 (en) * | 2016-05-31 | 2017-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Pop devices and methods of forming the same |
-
2018
- 2018-07-25 US US16/045,522 patent/US10510634B2/en active Active
- 2018-11-22 CN CN201811396075.0A patent/CN110034026B/zh active Active
- 2018-11-30 KR KR1020180152233A patent/KR20190064521A/ko active Application Filing
- 2018-11-30 TW TW107142835A patent/TWI686877B/zh active
-
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- 2019-09-30 US US16/588,473 patent/US10957616B2/en active Active
-
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- 2021-03-22 US US17/208,431 patent/US20210210399A1/en active Pending
- 2021-05-26 KR KR1020210067759A patent/KR102454016B1/ko active IP Right Grant
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201724382A (zh) * | 2015-12-31 | 2017-07-01 | 矽品精密工業股份有限公司 | 電子封裝件及其製法與基板結構 |
TW201737455A (zh) * | 2016-04-11 | 2017-10-16 | 南亞科技股份有限公司 | 半導體裝置及其製造方法 |
TWM548889U (zh) * | 2017-04-26 | 2017-09-11 | 宏濂科技股份有限公司 | 埋入式基板封裝結構 |
Also Published As
Publication number | Publication date |
---|---|
US20190164860A1 (en) | 2019-05-30 |
KR20190064521A (ko) | 2019-06-10 |
US20200027806A1 (en) | 2020-01-23 |
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US10510634B2 (en) | 2019-12-17 |
US10957616B2 (en) | 2021-03-23 |
KR102454016B1 (ko) | 2022-10-12 |
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