TWI664617B - 像素電路及其驅動方法、顯示裝置 - Google Patents
像素電路及其驅動方法、顯示裝置 Download PDFInfo
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Abstract
本發明公開一種像素電路及其驅動方法、顯示裝置,像素電路包括:第一薄膜電晶體、第二薄膜電晶體、第三薄膜電晶體、第四薄膜電晶體、第五薄膜電晶體、第六薄膜電晶體、第七薄膜電晶體、第八薄膜電晶體、第九薄膜電晶體、第一電容、第二電容以及發光二極體。本發明提供的像素電路中,補償電壓訊號線提供的補償電壓可以在像素電路的發光階段,對電源電壓進行部分補償,使流經發光二極體的電流由補償電壓以及電源電壓共同決定,而可在一定程度上減少電源電壓降對流經發光二極體電流的影響,進而減少電源電壓降對顯示裝置顯示不均勻性的影響。
Description
本發明涉及顯示技術領域,尤其涉及一種像素電路及其驅動方法、顯示裝置。
現有的有機發光顯示裝置中,通常可以包含多個像素電路,多個像素電路通常由同一電源提供電源電壓,電源電壓可以決定流經像素電路中發光二極體的電流。
然而,在實際應用中,電源電壓在多個像素電路間傳輸時不可避免的產生電源電壓降(IR drop),導致作用在每一個像素電路的實際電源電壓不同,進而導致流經每一個發光二極體的電流不同,顯示裝置顯示的亮度不均勻。
本發明的主要目的是提供一種像素電路及其驅動方法、顯示裝置,旨在解決現有的顯示裝置中,由於電源電壓降導致的流經發光二極體的電流不同,顯示裝置顯示的亮度不均勻的問題。
為實現上述目的,本發明提出的像素電路,包括:第一薄膜電晶體、第二薄膜電晶體、第三薄膜電晶體、第四薄膜電晶體、第五薄膜電晶體、第六薄膜電晶體、第七薄膜電晶體、第八薄膜電晶體、第九薄膜電晶體、第一電容、第二電容以及發光二極體,其中:
第一薄膜電晶體的柵極分別與第三薄膜電晶體的源極、第四薄膜電晶體的源極、第一電容的第一端以及第二電容的第一端連接,第四薄膜電晶體的漏極分別與第九薄膜電晶體的漏極以及參考電壓訊號線連接,第一電容的第二端分別與第七薄膜電晶體的漏極以及第八薄膜電晶體的漏極連接,第七薄膜電晶體的源極與補償電壓訊號線連接,第二電容的第二端與控制訊號線連接;
第一薄膜電晶體的源極分別與第二薄膜電晶體的漏極、第五薄膜電晶體的漏極以及第八薄膜電晶體的源極連接,第二薄膜電晶體的源極與資料電壓訊號線連接,第五薄膜電晶體的源極與第一電源連接;以及
第一薄膜電晶體的漏極分別與第三薄膜電晶體的漏極以及第六薄膜電晶體的源極連接,第六薄膜電晶體的漏極分別與第九薄膜電晶體的源極以及發光二極體的陽極連接,發光二極體的陰極與第二電源連接。
根據本發明的一實施方式,上述第一電源,用於為第一薄膜電晶體提供電源電壓;發光二極體發光時電流流入第二電源。
根據本發明的一實施方式,上述參考電壓訊號線用於提供參考電壓,參考電壓為負電壓,並用於對第一薄膜電晶體的柵極以及發光二極體的陽極進行初始化;以及
控制訊號線用於提供控制訊號,控制訊號提供交變電壓,用於改變第二電容的第二端的電壓。
根據本發明的一實施方式,上述補償電壓訊號線用於提供補償電壓,補償電壓用於對第一電源提供的電源電壓進行部分補償,其中,
補償電壓為正電壓,補償電壓大於第一電源提供的電源電壓;或,
補償電壓為負電壓,補償電壓與參考訊號線提供的參考電壓由同一電源提供。
根據本發明的一實施方式,上述第四薄膜電晶體的柵極與第一掃描線連接,第一掃描線提供的第一掃描訊號控制第四薄膜電晶體處於導通狀態時,對第一薄膜電晶體的柵極進行初始化;
第二薄膜電晶體的柵極、第三薄膜電晶體的柵極以及第七薄膜電晶體的柵極與第二掃描線連接,第二掃描線提供的第二掃描訊號控制第二薄膜電晶體、第三薄膜電晶體以及第七薄膜電晶體處於導通狀態時,對第一薄膜電晶體的閾值電壓進行補償;
第九薄膜電晶體的柵極與第三掃描線連接,第三掃描線提供的第三掃描訊號控制第九薄膜電晶體處於導通狀態時,對發光二極體的陽極進行初始化;以及
第五薄膜電晶體的柵極、第六薄膜電晶體的柵極以及第八薄膜電晶體的柵極與發光控制線連接,發光控制線提供的發光控制訊號控制第五薄膜電晶體、第六薄膜電晶體以及第八薄膜電晶體處於導通狀態時,電流流經發光二極體。
根據本發明的一實施方式,上述第二掃描訊號控制第七薄膜電晶體處於導通狀態時,補償電壓訊號線與第一電容的第二端連接,補償電壓向第一電容施加電壓;以及
發光控制訊號控制第五薄膜電晶體以及第八薄膜電晶體處於導通狀態時,第一電源通過第五薄膜電晶體以及第八薄膜電晶體與第一電容的第二端連接,在第一電容以及第二電容的作用下,流經發光二極體的電壓與補償電壓以及第一電源有關,對第一電源進行部分補償。
根據本發明的一實施方式,上述與第二電容的第二端連接的控制訊號線為第二掃描線。
根據本發明的一實施方式,上述第一電容的電容值大於第二電容的電容值,第一電容的電容值在第二電容的電容值的十倍與第二電容的電容值的一百倍之間。
本發明實施例提供一種像素電路的驅動方法,驅動方法用於驅動上述記載的像素電路,驅動方法包括:
第一階段,第一掃描訊號控制第四薄膜電晶體由截止狀態變為導通狀態,參考電壓訊號線提供的參考電壓對第一薄膜電晶體的柵極、第一電容的第一端以及第二電容的第一端進行初始化,第二掃描訊號控制第二薄膜電晶體、第三薄膜電晶體以及第七薄膜電晶體處於截止狀態,第三掃描訊號控制第九薄膜電晶體處於截止狀態,發光控制訊號控制第五薄膜電晶體、第六薄膜電晶體以及第八薄膜電晶體處於截止狀態,控制訊號線向第二電容的第二端施加高電平;
第二階段,第一掃描訊號控制第四薄膜電晶體由導通狀態變為截止狀態,第二掃描訊號控制第二薄膜電晶體、第三薄膜電晶體以及第七薄膜電晶體由截止狀態變為導通狀態,對第一薄膜電晶體的閾值電壓進行補償,補償電壓訊號線提供的補償電壓向第一電容的第二端施加電壓,第三掃描訊號控制第九薄膜電晶體由截止狀態變為導通狀態,參考電壓對發光二極體的陽極進行初始化,發光控制訊號控制第五薄膜電晶體、第六薄膜電晶體以及第八薄膜電晶體處於截止狀態,控制訊號線向第二電容的第二端施加低電平;以及
第三階段,第一掃描訊號控制第四薄膜電晶體處於截止狀態,第二掃描訊號控制第二薄膜電晶體、第三薄膜電晶體以及第七薄膜電晶體由導通狀態變為截止狀態,第三掃描訊號控制第九薄膜電晶體由導通狀態變為截止狀態,發光控制訊號控制第五薄膜電晶體、第六薄膜電晶體以及第八薄膜電晶體由截止狀態變為導通狀態,發光二極體發光,控制訊號線向第二電容的第二端施加高電平,在第一電容以及第二電容的作用下,流經發光二極體的電壓與補償電壓以及第一電源有關,對第一電源進行部分補償。
本發明實施例還提供一種顯示裝置,該顯示裝置包括上述記載的像素電路。
本發明實施例採用的上述至少一個技術方案能夠達到以下有益效果:
本發明實施例提供的像素電路中,補償電壓訊號線提供的補償電壓可以在像素電路的發光階段,對電源電壓進行部分補償,使得流經發光二極體的電流由補償電壓以及電源電壓共同決定,進而可以在一定程度上減少電源電壓降對流經發光二極體的電流的影響,進而減少電源電壓降對顯示裝置顯示不均勻性的影響。
此外,本發明實施例提供的像素電路還可以實現對驅動薄膜電晶體閾值電壓的補償,有效避免由於驅動薄膜電晶體閾值電壓的不同導致的顯示裝置顯示不均勻的問題。
下面結合本發明具體實施例及相應的附圖對本發明技術方案進行清楚、完整地描述。
需要說明的是,在本發明實施例提供的像素電路中,第一薄膜電晶體為驅動薄膜電晶體,具體可以為P型薄膜電晶體;第二薄膜電晶體、第三薄膜電晶體、第四薄膜電晶體、第五薄膜電晶體、第六薄膜電晶體、第七薄膜電晶體、第八薄膜電晶體以及第九薄膜電晶體可以是均為P型薄膜電晶體,也可以是均為N型薄膜電晶體,還可以是其中至少一個為P型薄膜電晶體,其餘的為N型薄膜電晶體,本發明實施例不做具體限定。
發光二極體可以是LED,也可以是OLED,這裡也不做具體限定。
以下結合附圖,詳細說明本發明各實施例提供的技術方案。
圖1為本發明實施例提供的一種像素電路的結構示意圖。像素電路如下所述。
如圖1所示,像素電路包括第一薄膜電晶體M1、第二薄膜電晶體M2、第三薄膜電晶體M3、第四薄膜電晶體M4、第五薄膜電晶體M5、第六薄膜電晶體M6、第七薄膜電晶體M7、第八薄膜電晶體M8、第九薄膜電晶體M9、第一電容C1、第二電容C2以及發光二極體D1。
其中,圖1所示的像素電路中,第一薄膜電晶體M1、第二薄膜電晶體M2、第三薄膜電晶體M3、第四薄膜電晶體M4、第五薄膜電晶體M5、第六薄膜電晶體M6、第七薄膜電晶體M7、第八薄膜電晶體M8以及第九薄膜電晶體M9均為P型薄膜電晶體,發光二極體D1為OLED。
圖1所示的像素電路的電路連接結構如下所述:
第一薄膜電晶體M1的柵極分別與第三薄膜電晶體M3的源極、第四薄膜電晶體M4的源極、第一電容C1的第一端(圖1所示的B點,第一電容C1的下極板)以及第二電容C2的第一端(圖1所示的D點,第二電容C2的右極板)連接,源極分別與第二薄膜電晶體M2的漏極、第五薄膜電晶體M5的漏極以及第八薄膜電晶體M8的源極連接,漏極分別與第三薄膜電晶體M3的漏極以及第六薄膜電晶體M6的源極連接;
第二薄膜電晶體M2的源極與資料電壓訊號線連接;
第四薄膜電晶體M4的漏極分別與第九薄膜電晶體M9的漏極以及參考電壓訊號線連接;
第五薄膜電晶體M5的源極與第一電源VDD連接;
第六薄膜電晶體M6的漏極分別與第九薄膜電晶體M9的源極以及發光二極體D1的陽極連接;
第七薄膜電晶體M7的源極與補償電壓訊號線連接,漏極分別與第八薄膜電晶體M8的漏極以及第一電容C1的第二端(圖1所示的A點,第一電容C1的上極板)連接;
發光二極體D1的陰極與第二電源VSS連接。
需要說明的是,在實際應用中,圖1所示的第三薄膜電晶體M3可以由兩個共柵極的薄膜電晶體代替,這樣,在像素電路的工作過程中,兩個共柵極的薄膜電晶體可以降低第三薄膜電晶體M3所在支路的漏電流。同理,第四薄膜電晶體M4也可以由兩個共柵極的薄膜電晶體代替,以降低第四薄膜電晶體M4所在支路的漏電流。此外,針對圖1中的其他可以視為開關管的薄膜電晶體而言,也可以根據實際需要將其中一個或多個薄膜電晶體分別由兩個共柵極的薄膜電晶體代替,以降低其所在支路的漏電流,本發明實施例不做具體限定。
本發明實施例中,第一電源VDD可以是正電壓,並用於為第一薄膜電晶體M1提供電源電壓,第一薄膜電晶體M1在第一電源VDD的作用下,可以輸出電流,該電流流入發光二極體D1,使得發光二極體D1發光,在發光二極體D1發光時,該電流流入第二電源VSS,第二電源VSS可以是負電壓。
資料電壓訊號線可以用於提供資料電壓Vdata,參考電壓訊號線可以用於提供參考電壓VREF。本發明實施例中,參考電壓VREF可以為負電壓,並用於對第一薄膜電晶體M1的柵極以及發光二極體D1的陽極進行初始化,其中,參考電壓VREF可以是比第二電源VSS還要低的負壓,這樣,在參考電壓VREF對發光二極體D1的陽極進行初始化時,可以保證發光二極體D1不發光。
補償電壓訊號線可以提供補償電壓VIN,補償電壓VIN可以用於對第一電源VDD提供的電源電壓進行部分補償。
需要說明的是,本發明實施例中,補償電壓VIN可以是正電壓,也可以是負電壓,其中,當補償電壓VIN為正電壓時,補償電壓VIN可以大於第一電源VDD;當補償電壓VIN為負電壓時,補償電壓VIN與參考電壓VREF可以由同一電源提供,即可以將補償電壓訊號線與參考電壓訊號線合併為一條訊號線,此時,資料電壓Vdata可以是負電壓,且可以小於補償電壓VIN。
圖1所示的像素電路中,S1為第一掃描線提供的第一掃描訊號,S2為第二掃描線提供的第二掃描訊號,S3為第三掃描線提供的第三掃描訊號,EM為發光控制線提供的發光控制訊號,其中:
第四薄膜電晶體M4的柵極與第一掃描線連接,第一掃描線提供的第一掃描訊號S1可以控制第四薄膜電晶體M4處於導通狀態或截止狀態;
第二薄膜電晶體M2的柵極、第三薄膜電晶體M3以及第七薄膜電晶體M7的柵極與第二掃描線連接,第二掃描線提供的第二掃描訊號S2可以控制第二薄膜電晶體M2、第三薄膜電晶體M3以及第七薄膜電晶體M7處於導通狀態或截止狀態;
第九薄膜電晶體M9的柵極與第三掃描線連接,第三掃描線提供的第三掃描訊號S3可以控制第九薄膜電晶體M9處於導通狀態或截止狀態;
第五薄膜電晶體M5的柵極、第六薄膜電晶體M6的柵極以及第八薄膜電晶體M8的柵極與發光控制線連接,發光控制線提供的發光控制訊號EM可以控制第五薄膜電晶體M5、第六薄膜電晶體M6以及第八薄膜電晶體M8處於導通狀態或截止狀態。
本發明實施例中,第二電容C2的第二端(圖1所示的C點,第二電容C2的左極板)還可以與第二掃描線連接,第二掃描訊號S2可以用於改變第二電容C2的第二端的電壓(即第二電容C2的左極板電壓),其中,第二掃描訊號S2可以提供交變電壓,即第二掃描訊號S2可以從高電平變為低電平,並從低電平變為高電平,以便於改變第二電容C2的左極板電壓。
需要說明的是,在實際應用中,與圖1中第二電容C2的第二端C點連接的還可以是其他控制訊號線,其中,控制訊號線可以提供控制訊號,控制訊號可以提供交變電壓,並具有第二掃描訊號S2的電壓變化特性,控制訊號可以用於改變第二電容C2的左極板電壓。本申請實施例中,作為一種優選地方式,第二電容C2的第二端C點可以與第二掃描線連接,以減少圖元電路中的控制線的個數。
本發明實施例中,在第一掃描訊號S1控制第四薄膜電晶體M4處於導通狀態時,參考電壓VREF可以通過第四薄膜電晶體M4向第一薄膜電晶體M1的柵極施加電壓,並對第一薄膜電晶體M1的柵極進行初始化;
在第二掃描訊號S2控制第二薄膜電晶體M2、第三薄膜電晶體M3以及第七薄膜電晶體M7處於導通狀態時,針對第一薄膜電晶體M1而言,第一薄膜電晶體M1的柵極與漏極連接,資料電壓Vdata通過第二薄膜電晶體M2向第一薄膜電晶體M1的源極施加電壓,電路狀態穩定後,第一薄膜電晶體M1的源極電壓為Vdata,柵極電壓以及漏極電壓均為Vdata-Vth,這樣,可以實現對第一薄膜電晶體M1閾值電壓的補償,其中,Vth為第一薄膜電晶體M1的閾值電壓;
針對第一電容C1而言,補償電壓VIN可以通過第七薄膜電晶體M7向第一電容C1的上極板(圖1所示的A點)施加電壓,使得第一電容C1的上極板電壓為VIN。
在第三掃描訊號S3控制第九薄膜電晶體M9處於導通狀態時,參考電壓VREF可以通過第九薄膜電晶體M9向發光二極體D1的陽極施加電壓,對發光二極體D1的陽極進行初始化。
在發光控制訊號EM控制第五薄膜電晶體M5、第六薄膜電晶體M6以及第八薄膜電晶體M8處於導通狀態時,第一電源VDD可以通過第五薄膜電晶體M5向第一薄膜電晶體M1的源極施加電壓,第一薄膜電晶體M1可以產生電流,該電流流經發光二極體D1,使得發光二極體D1發光。
此外,發光控制訊號EM在控制第五薄膜電晶體M5以及第八薄膜電晶體M8處於導通狀態時,第一電源VDD還可以與第一電容C1的第二端(圖1所示的A點,即第一電容C1的上極板)連接,使得第一電容C1的上極板電壓由VIN變為VDD,這樣,在第一電容C1以及第二電容C2的作用下,使得流經發光二極體D1的電流與補償電壓VIN以及第一電源VDD有關,這樣,可以對第一電源VDD進行部分補償,減少第一電源VDD對流經發光二極體D1的電流的影響,進而減少第一電源VDD對顯示裝置顯示均勻性的影響。
本發明實施例中,第一電容C1的電容值可以大於第二電容C2的電容值的十倍,優選地,第一電容C1的電容值與第二電容C2的電容值的比值約為10~100倍。這樣,可以相對增加補償電壓VIN對流經發光二極體D1的電流的影響,相對減少第一電源VDD對流經發光二極體D1的電流的影響,相較于現有技術而言,可以有效改善顯示裝置顯示的均勻性。
圖2為本發明實施例提供的一種像素電路的驅動方法的時序圖,像素電路的驅動方法可以用於驅動圖所示的像素電路。
圖2所示的時序圖在驅動圖1所示的像素電路時,工作週期可以包括三個階段:第一階段t1、第二階段t2以及第三階段t3,其中,S1為第一掃描線提供的第一掃描訊號,可以用於控制圖1所示的第四薄膜電晶體M4處於導通狀態或截止狀態,S2為第二掃描線提供的第二掃描訊號,可以用於控制圖1所示的第二薄膜電晶體M2、第三薄膜電晶體M3以及第七薄膜電晶體M7處於導通狀態或截止狀態,S3為第三掃描線提供的第三掃描訊號,可以用於控制圖1所示的第九薄膜電晶體M9處於導通狀態或截止狀態,EM為發光控制線提供的發光控制訊號,可以用於控制圖1所示的第五薄膜電晶體M5、第六薄膜電晶體M6以及第八薄膜電晶體M8處於導通狀態或截止狀態,Vdata為資料電壓訊號線提供的資料電壓。
下面分別針對上述三個階段進行說明:
針對第一階段t1:
由於第一掃描訊號S1由高電平變為低電平,第二掃描訊號S2保持高電平,第三掃描訊號S3保持高電平,發光控制訊號EM由低電平變為高電平,因此,第四薄膜電晶體M4處於導通狀態,第二薄膜電晶體M2、第三薄膜電晶體M3以及第七薄膜電晶體M7處於截止狀態,第九薄膜電晶體M9處於截止狀態,第五薄膜電晶體M5、第六薄膜電晶體M6以及第八薄膜電晶體M8處於截止狀態。
此時,參考電壓VREF通過第四薄膜電晶體M4向第一薄膜電晶體M1的柵極、第一電容C1的下極板以及第二電容C2的右極板(圖2所示的B點)施加電壓,對第一薄膜電晶體M1的柵極、第一電容C1的下極板以及第二電容C2的右極板進行初始化。
在初始化後,第一薄膜電晶體M1的柵極電壓等於VREF,第一電容C1的下極板電壓以及第二電容C2的右極板電壓均為VREF。
需要說明的是,此時,由於第二掃描線S2為高電平,因此,第二電容C2的左極板(圖2所示的C點)的電壓為高電平。在實際應用中,由於第二掃描線S2的高電平電壓通常為7V,因此,在第一階段t1,第二電容C2的左極板電壓可以是7V。
針對第二階段t2:
由於第一掃描訊號S1由低電平變為高電平,第二掃描訊號S2由高電平變為低電平,第三掃描訊號S3由高電平變為低電平,發光控制訊號EM保持高電平,因此,第四薄膜電晶體M4由導通狀態變為截止狀態,第二薄膜電晶體M2、第三薄膜電晶體M3以及第七薄膜電晶體M7由截止狀態變為導通狀態,第九薄膜電晶體M9由截止狀態變為導通狀態,第五薄膜電晶體M5、第六薄膜電晶體M6以及第八薄膜電晶體M8仍處於截止狀態。
此時,第一薄膜電晶體M1的柵極與漏極連接,資料電壓Vdata通過第二薄膜電晶體M2向第一薄膜電晶體M1的源極施加電壓,此時,第一薄膜電晶體M1的源極電壓為Vdata,由於在第一階段t1第一薄膜電晶體M1的柵極電壓為VREF,因此,第一薄膜電晶體M1處於導通狀態,資料電壓Vdata經過第一薄膜電晶體M1以及第三薄膜電晶體M3作用在第一薄膜電晶體M1的柵極,最終使得第一薄膜電晶體M1的柵極電壓和漏極電壓均為Vdata-Vth,第一薄膜電晶體M1處於截止狀態,這樣,可以實現對第一薄膜電晶體M1閾值電壓的補償,其中,Vth為第一薄膜電晶體M1的閾值電壓。
針對第一電容C1而言,補償電壓VIN通過第七薄膜電晶體M7向第一電容C1的上極板施加電壓,使得第一電容C1的上極板電壓變為VIN。此時,由於第一電容C1的下極板電壓等於第一薄膜電晶體M1的柵極電壓,因此,第一電容C1的下極板電壓為Vdata-Vth,第一電容C1的下極板與上極板之間的壓差為Vdata-Vth-VIN。
針對第二電容C2而言,第二電容C2的右極板電壓等於第一電容C1的下極板電壓,即為Vdata-Vth,左極板電壓等於第二掃描線S2提供的低電平。在實際應用中,由於第二掃描線S2提供的低電平通常為-7V,因此,第二電容C2的左極板電壓變為-7V,第二電容C2的左極板與右極板之間的壓差為-7-Vdata+Vth。
此外,參考電壓VREF通過第九薄膜電晶體M9向發光二極體D1的陽極施加電壓,可以對發光二極體D1的陽極進行初始化,使得發光二極體D1不發光。這樣,可以使得像素電路在第二階段t2顯示純黑,從而增加整個顯示裝置顯示的對比度。
針對第三階段t3:
由於第一掃描訊號S1保持高電平,第二掃描訊號S2由低電平變為高電平,第三掃描訊號S3由低電平變為高電平,發光控制訊號EM由高電平變為低電平,因此,第四薄膜電晶體M4仍處於截止狀態,第二薄膜電晶體M2、第三薄膜電晶體M3以及第七薄膜電晶體M7由導通狀態變為截止狀態,第九薄膜電晶體M9由導通狀態變為截止狀態,第五薄膜電晶體M5、第六薄膜電晶體M6以及第八薄膜電晶體M8由截止狀態變為導通狀態。
此時,第一電源VDD通過第五薄膜電晶體M5以及第八薄膜電晶體M8向第一電容C1的上極板施加電壓,使得第一電容C1的上極板電壓由VIN變為VDD,同時,第二掃描線S2由低電平變為高電平,使得第二電容C2的左極板電壓由-7V變為7V,此階段,由於第一電容C1以及第二電容C2的串聯作用,因此,第一電容C1上極板電壓的變化量VDD-VIN給第一電容C1下極板電壓帶來的變化量為,第二電容C2左極板電壓的變化量14V給第一電容C1下極板電壓帶來的變化量為,這樣,第一電容C1的下極板電壓,即第二電容C2的右極板電壓由Vdata-Vth變為,其中,c1為第一電容C1的電容值,c2為第二電容C2的電容值。
在第三階段t3,第一薄膜電晶體M1導通,電流流經發光二極體D1,發光二極體D1發光,其中,流經發光二極體D1的電流可以表示為:,
其中,μ
為第一薄膜電晶體M1的電子遷移率,Cox
為第一薄膜電晶體M1單位面積的柵氧化層電容,W/L為第一薄膜電晶體M1的寬長比。
由上述公式可知,流經發光二極體D1的電流與補償電壓VIN以及第一電源VDD有關,與第一薄膜電晶體M1的閾值電壓無關,實現了對第一電源VDD的部分補償,減少了第一電源VDD的電源電壓降對顯示效果的影響,在一定程度上增加了顯示裝置顯示的均勻性,同時,實現了對第一薄膜電晶體M1的閾值電壓的補償,避免了由於第一薄膜電晶體M1的閾值電壓的不同導致的顯示裝置顯示不均勻的問題。
需要說明的是,在本發明實施例中,第一電容C1的電容值可以大於第二電容C2的電容值的十倍,優選地,第一電容C1的電容值與第二電容C2的電容值的比值約為10~100倍。這樣,第一電源VDD對IOLED
的影響將小於補償電壓VIN對IOLED
的影響,這樣,即使第一電源VDD存在較大的電源電壓降,由於第一電源VDD對IOLED
的影響比較小,因此,第一電源VDD對顯示裝置顯示均勻性的影響也比較小,進而實現對第一電源VDD的部分補償,改善顯示裝置的顯示效果。在實際應用中,還可以通過改變第一電容C1以及第二電容C2的大小,改變第一電源VDD以及補償電壓VIN對IOLED
的影響。
還需要說明的是,在實際應用中,補償電壓VIN也存在一定的壓降,但是,由於補償電壓VIN僅需要給第一電容C1充電,不參與對像素電路的驅動,因此,補償電壓VIN產生的電流遠小於第一電源VDD產生的電流,進而產生的壓降也遠小於第一電源VDD產生的壓降,也就是說,本發明實施例由補償電壓VIN以及第一電源VDD共同決定流經發光二極體D1的電流,可以有效改善電源電壓將導致的顯示裝置顯示的不均勻性。
本發明實施例提供的像素電路中,補償電壓訊號線提供的補償電壓可以在像素電路的發光階段,對電源電壓進行部分補償,使得流經發光二極體的電流由補償電壓以及電源電壓共同決定,進而可以在一定程度上減少電源電壓降對流經發光二極體的電流的影響,進而減少電源電壓降對顯示裝置顯示不均勻性的影響。
此外,本發明實施例提供的像素電路還可以實現對驅動薄膜電晶體閾值電壓的補償,有效避免由於驅動薄膜電晶體閾值電壓的不同導致的顯示裝置顯示不均勻的問題。
本發明實施例還提供一種顯示裝置,顯示裝置可以包括上述記載的像素電路。
本領域的技術人員應明白,儘管已描述了本發明的優選實施例,但本領域內的技術人員一旦得知了基本創造性概念,則可對這些實施例作出另外的變更和修改。所以,所附請求項意欲解釋為包括優選實施例以及落入本發明範圍的所有變更和修改。
顯然,本領域的技術人員可以對本發明進行各種改動和變型而不脫離本發明的範圍。這樣,倘若本發明的這些修改和變型屬於本發明申請專利範圍及其等同技術的範圍之內,則本發明也意圖包含這些改動和變型在內。
M1‧‧‧第一薄膜電晶體
M2‧‧‧第二薄膜電晶體
M3‧‧‧第三薄膜電晶體
M4‧‧‧第四薄膜電晶體
M5‧‧‧第五薄膜電晶體
M6‧‧‧第六薄膜電晶體
M7‧‧‧第七薄膜電晶體
M8‧‧‧第八薄膜電晶體
M9‧‧‧第九薄膜電晶體
C1‧‧‧第一電容
C2‧‧‧第二電容
D1‧‧‧發光二極體
VDD‧‧‧第一電源
VSS‧‧‧第二電源
VERF‧‧‧參考電壓
Vdata‧‧‧資料電壓
VIN‧‧‧補償電壓
EM‧‧‧發光控制訊號
S1‧‧‧第一掃描訊號
S2‧‧‧第二掃描訊號
S3‧‧‧第三掃瞄訊號
t1‧‧‧第一階段
t2‧‧‧第二階段
t3‧‧‧第三階段
圖1為本發明實施例提供的一種像素電路的結構示意圖;
圖2為本發明實施例提供的一種像素電路的驅動方法的時序圖。
本發明目的的實現、功能特點及優點將結合實施例,參照附圖做進一步說明。
Claims (10)
- 一種像素電路,包括:一第一薄膜電晶體、一第二薄膜電晶體、一第三薄膜電晶體、一第四薄膜電晶體、一第五薄膜電晶體、一第六薄膜電晶體、一第七薄膜電晶體、一第八薄膜電晶體、一第九薄膜電晶體、一第一電容、一第二電容以及一發光二極體,其中:該第一薄膜電晶體的柵極分別與該第三薄膜電晶體的源極、該第四薄膜電晶體的源極、該第一電容的第一端以及該第二電容的第一端連接,該第四薄膜電晶體的漏極分別與該第九薄膜電晶體的漏極以及一參考電壓訊號線連接,該第一電容的第二端分別與該第七薄膜電晶體的漏極以及該第八薄膜電晶體的漏極連接,該第七薄膜電晶體的源極與一補償電壓訊號線連接,該第二電容的第二端與一控制訊號線連接;該第一薄膜電晶體的源極分別與該第二薄膜電晶體的漏極、該第五薄膜電晶體的漏極以及該第八薄膜電晶體的源極連接,該第二薄膜電晶體的源極與一資料電壓訊號線連接,該第五薄膜電晶體的源極與一第一電源連接;以及該第一薄膜電晶體的漏極分別與該第三薄膜電晶體的漏極以及該第六薄膜電晶體的源極連接,該第六薄膜電晶體的漏極分別與該第九薄膜電晶體的源極以及該發光二極體的陽極連接,該發光二極體的陰極與一第二電源連接。
- 如請求項第1項所述之像素電路,其中,該第一電源,用於為該第一薄膜電晶體提供電源電壓;以及該發光二極體發光時電流流入該第二電源。
- 如請求項第2項所述之像素電路,其中,該參考電壓訊號線用於提供一參考電壓,該參考電壓為負電壓,並用於對該第一薄膜電晶體的柵極以及該發光二極體的陽極進行初始化;以及該控制訊號線用於提供控制訊號,該控制訊號提供交變電壓,用於改變該第二電容的第二端的電壓。
- 如請求項第3項所述之像素電路,其中,該補償電壓訊號線用於提供補償電壓,該補償電壓用於對該第一電源提供的電源電壓進行部分補償,其中,該補償電壓為正電壓,該補償電壓大於該第一電源提供的電源電壓;或,該補償電壓為負電壓,該補償電壓與該參考訊號線提供的參考電壓由同一電源提供。
- 如請求項第4項所述之像素電路,其中,該第四薄膜電晶體的柵極與一第一掃描線連接,該第一掃描線提供的第一掃描訊號控制該第四薄膜電晶體處於導通狀態時,對該第一薄膜電晶體的柵極進行初始化;該第二薄膜電晶體的柵極、該第三薄膜電晶體的柵極以及該第七薄膜電晶體的柵極與一第二掃描線連接,該第二掃描線提供的第二掃描訊號控制該第二薄膜電晶體、該第三薄膜電晶體以及該第七薄膜電晶體處於導通狀態時,對該第一薄膜電晶體的閾值電壓進行補償;該第九薄膜電晶體的柵極與一第三掃描線連接,該第三掃描線提供的第三掃描訊號控制該第九薄膜電晶體處於導通狀態時,對該發光二極體的陽極進行初始化;以及該第五薄膜電晶體的柵極、該第六薄膜電晶體的柵極以及該第八薄膜電晶體的柵極與一發光控制線連接,該發光控制線提供的發光控制訊號控制該第五薄膜電晶體、該第六薄膜電晶體以及該第八薄膜電晶體處於導通狀態時,電流流經該發光二極體。
- 如請求項第5項所述之像素電路,其中,該第二掃描訊號控制該第七薄膜電晶體處於導通狀態時,該補償電壓訊號線與該第一電容的第二端連接,該補償電壓向該第一電容施加電壓;以及該發光控制訊號控制該第五薄膜電晶體以及該第八薄膜電晶體處於導通狀態時,該第一電源通過該第五薄膜電晶體以及該第八薄膜電晶體與該第一電容的第二端連接,在該第一電容以及該第二電容的作用下,流經該發光二極體的電壓與該補償電壓以及該第一電源有關,對該第一電源進行部分補償。
- 如請求項第6項所述之像素電路,其中,與該第二電容的第二端連接的該控制訊號線為該第二掃描線。
- 如請求項第7項所述之像素電路,其中,該第一電容的電容值大於該第二電容的電容值,該第一電容的電容值在該第二電容的電容值的十倍與該第二電容的電容值的一百倍之間。
- 一種如請求項1至8項任一項所述的像素電路的驅動方法,包括:第一階段,第一掃描訊號控制該第四薄膜電晶體由截止狀態變為導通狀態,該參考電壓訊號線提供的參考電壓對該第一薄膜電晶體的柵極、該第一電容的第一端以及該第二電容的第一端進行初始化,第二掃描訊號控制該第二薄膜電晶體、該第三薄膜電晶體以及該第七薄膜電晶體處於截止狀態,第三掃描訊號控制該第九薄膜電晶體處於截止狀態,發光控制訊號控制該第五薄膜電晶體、該第六薄膜電晶體以及該第八薄膜電晶體處於截止狀態,該控制訊號線向該第二電容的第二端施加高電平;第二階段,該第一掃描訊號控制該第四薄膜電晶體由導通狀態變為截止狀態,該第二掃描訊號控制該第二薄膜電晶體、該第三薄膜電晶體以及該第七薄膜電晶體由截止狀態變為導通狀態,對該第一薄膜電晶體的閾值電壓進行補償,該補償電壓訊號線提供的補償電壓向該第一電容的第二端施加電壓,該第三掃描訊號控制該第九薄膜電晶體由截止狀態變為導通狀態,該參考電壓對發光二極體的陽極進行初始化,該發光控制訊號控制該第五薄膜電晶體、該第六薄膜電晶體以及該第八薄膜電晶體處於截止狀態,該控制訊號線向該第二電容的第二端施加低電平;以及第三階段,該第一掃描訊號控制該第四薄膜電晶體處於截止狀態,該第二掃描訊號控制該第二薄膜電晶體、該第三薄膜電晶體以及該第七薄膜電晶體由導通狀態變為截止狀態,該第三掃描訊號控制該第九薄膜電晶體由導通狀態變為截止狀態,該發光控制訊號控制該第五薄膜電晶體、該第六薄膜電晶體以及該第八薄膜電晶體由截止狀態變為導通狀態,該發光二極體發光,該控制訊號線向該第二電容的第二端施加高電平,在該第一電容以及該第二電容的作用下,流經該發光二極體的電壓與該補償電壓以及該第一電源有關,對該第一電源進行部分補償。
- 一種顯示裝置,包括:如請求項第1至8項任一項所述的像素電路。
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