TWI661323B - 模擬方法，模擬程式，製程控制系統，模擬器，製程設計方法及光罩設計方法 - Google Patents

模擬方法，模擬程式，製程控制系統，模擬器，製程設計方法及光罩設計方法 Download PDF

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Publication number
TWI661323B
TWI661323B TW103136187A TW103136187A TWI661323B TW I661323 B TWI661323 B TW I661323B TW 103136187 A TW103136187 A TW 103136187A TW 103136187 A TW103136187 A TW 103136187A TW I661323 B TWI661323 B TW I661323B
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TW
Taiwan
Prior art keywords
wafer
mask
etching
aperture ratio
rate
Prior art date
Application number
TW103136187A
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English (en)
Chinese (zh)
Other versions
TW201520803A (zh
Inventor
Nobuyuki Kuboi
久保井信行
Takashi Kinoshita
木下隆
Original Assignee
Sony Semiconductor Solutions Corporation
索尼半導體解決方案公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corporation, 索尼半導體解決方案公司 filed Critical Sony Semiconductor Solutions Corporation
Publication of TW201520803A publication Critical patent/TW201520803A/zh
Application granted granted Critical
Publication of TWI661323B publication Critical patent/TWI661323B/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32917—Plasma diagnostics
    • H01J37/32926—Software, data control or modelling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Plasma Technology (AREA)
TW103136187A 2013-11-28 2014-10-20 模擬方法，模擬程式，製程控制系統，模擬器，製程設計方法及光罩設計方法 TWI661323B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013245647A JP6173889B2 (ja) 2013-11-28 2013-11-28 シミュレーション方法、シミュレーションプログラム、加工制御システム、シミュレータ、プロセス設計方法およびマスク設計方法
JP2013-245647 2013-11-28

Publications (2)

Publication Number Publication Date
TW201520803A TW201520803A (zh) 2015-06-01
TWI661323B true TWI661323B (zh) 2019-06-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW103136187A TWI661323B (zh) 2013-11-28 2014-10-20 模擬方法，模擬程式，製程控制系統，模擬器，製程設計方法及光罩設計方法

Country Status (3)

Country Link
US (1) US9431310B2 (enExample)
JP (1) JP6173889B2 (enExample)
TW (1) TWI661323B (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7802917B2 (en) * 2005-08-05 2010-09-28 Lam Research Corporation Method and apparatus for chuck thermal calibration
JP6516603B2 (ja) * 2015-04-30 2019-05-22 東京エレクトロン株式会社 エッチング方法及びエッチング装置
US9865471B2 (en) * 2015-04-30 2018-01-09 Tokyo Electron Limited Etching method and etching apparatus
US10534257B2 (en) * 2017-05-01 2020-01-14 Lam Research Corporation Layout pattern proximity correction through edge placement error prediction
KR102644214B1 (ko) * 2018-02-23 2024-03-07 에이에스엠엘 네델란즈 비.브이. 컴퓨테이션 리소그래피를 위한 머신 러닝 모델을 트레이닝시키기 위한 방법
US10572697B2 (en) 2018-04-06 2020-02-25 Lam Research Corporation Method of etch model calibration using optical scatterometry
CN112005347B (zh) 2018-04-10 2025-04-04 朗姆研究公司 抗蚀剂和蚀刻建模
CN111971551B (zh) 2018-04-10 2025-02-28 朗姆研究公司 机器学习中的光学计量以表征特征
WO2020050072A1 (ja) 2018-09-03 2020-03-12 株式会社Ｐｒｅｆｅｒｒｅｄ Ｎｅｔｗｏｒｋｓ 学習装置、推論装置及び学習済みモデル
KR102513707B1 (ko) 2018-09-03 2023-03-23 가부시키가이샤 프리퍼드 네트웍스 학습 장치, 추론 장치, 학습 모델 생성 방법 및 추론 방법
JP7345382B2 (ja) * 2018-12-28 2023-09-15 東京エレクトロン株式会社 プラズマ処理装置及び制御方法
EP3850628B1 (en) * 2019-01-28 2023-10-18 Yangtze Memory Technologies Co., Ltd. Systems and methods for designing dummy patterns

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030015660A1 (en) * 2001-07-19 2003-01-23 Chie Shishido Method and system for monitoring a semiconductor device manufacturing process
US20030230551A1 (en) * 2002-06-14 2003-12-18 Akira Kagoshima Etching system and etching method
US7363099B2 (en) * 2002-06-07 2008-04-22 Cadence Design Systems, Inc. Integrated circuit metrology
US20110082577A1 (en) * 2009-08-24 2011-04-07 Sony Corporation Shape simulation apparatus, shape simulation program, semiconductor production apparatus, and semiconductor device production method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5050830B2 (ja) * 2007-12-19 2012-10-17 ソニー株式会社 ドライエッチング装置および半導体装置の製造方法
JP5732843B2 (ja) * 2010-12-21 2015-06-10 ソニー株式会社 シミュレータ、加工装置、ダメージ評価方法、及び、ダメージ評価プログラム

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030015660A1 (en) * 2001-07-19 2003-01-23 Chie Shishido Method and system for monitoring a semiconductor device manufacturing process
US7363099B2 (en) * 2002-06-07 2008-04-22 Cadence Design Systems, Inc. Integrated circuit metrology
US20030230551A1 (en) * 2002-06-14 2003-12-18 Akira Kagoshima Etching system and etching method
US20110082577A1 (en) * 2009-08-24 2011-04-07 Sony Corporation Shape simulation apparatus, shape simulation program, semiconductor production apparatus, and semiconductor device production method

Also Published As

Publication number Publication date
TW201520803A (zh) 2015-06-01
JP6173889B2 (ja) 2017-08-02
US20150149970A1 (en) 2015-05-28
JP2015103769A (ja) 2015-06-04
US9431310B2 (en) 2016-08-30

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