JP6173889B2 - シミュレーション方法、シミュレーションプログラム、加工制御システム、シミュレータ、プロセス設計方法およびマスク設計方法 - Google Patents

シミュレーション方法、シミュレーションプログラム、加工制御システム、シミュレータ、プロセス設計方法およびマスク設計方法 Download PDF

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JP6173889B2
JP6173889B2 JP2013245647A JP2013245647A JP6173889B2 JP 6173889 B2 JP6173889 B2 JP 6173889B2 JP 2013245647 A JP2013245647 A JP 2013245647A JP 2013245647 A JP2013245647 A JP 2013245647A JP 6173889 B2 JP6173889 B2 JP 6173889B2
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Japan
Prior art keywords
wafer
mask
aperture ratio
calculated
etch rate
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Japanese (ja)
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JP2015103769A5 (enExample
JP2015103769A (ja
Inventor
信行 久保井
信行 久保井
木下　隆
隆 木下
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Priority to JP2013245647A priority Critical patent/JP6173889B2/ja
Priority to TW103136187A priority patent/TWI661323B/zh
Priority to US14/522,065 priority patent/US9431310B2/en
Publication of JP2015103769A publication Critical patent/JP2015103769A/ja
Publication of JP2015103769A5 publication Critical patent/JP2015103769A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32917—Plasma diagnostics
    • H01J37/32926—Software, data control or modelling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Plasma Technology (AREA)
JP2013245647A 2013-11-28 2013-11-28 シミュレーション方法、シミュレーションプログラム、加工制御システム、シミュレータ、プロセス設計方法およびマスク設計方法 Active JP6173889B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2013245647A JP6173889B2 (ja) 2013-11-28 2013-11-28 シミュレーション方法、シミュレーションプログラム、加工制御システム、シミュレータ、プロセス設計方法およびマスク設計方法
TW103136187A TWI661323B (zh) 2013-11-28 2014-10-20 模擬方法，模擬程式，製程控制系統，模擬器，製程設計方法及光罩設計方法
US14/522,065 US9431310B2 (en) 2013-11-28 2014-10-23 Simulation method, simulation program, process control system, simulator, process design method, and mask design method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013245647A JP6173889B2 (ja) 2013-11-28 2013-11-28 シミュレーション方法、シミュレーションプログラム、加工制御システム、シミュレータ、プロセス設計方法およびマスク設計方法

Publications (3)

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JP2015103769A JP2015103769A (ja) 2015-06-04
JP2015103769A5 JP2015103769A5 (enExample) 2016-04-14
JP6173889B2 true JP6173889B2 (ja) 2017-08-02

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US (1) US9431310B2 (enExample)
JP (1) JP6173889B2 (enExample)
TW (1) TWI661323B (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7802917B2 (en) * 2005-08-05 2010-09-28 Lam Research Corporation Method and apparatus for chuck thermal calibration
JP6516603B2 (ja) * 2015-04-30 2019-05-22 東京エレクトロン株式会社 エッチング方法及びエッチング装置
US9865471B2 (en) * 2015-04-30 2018-01-09 Tokyo Electron Limited Etching method and etching apparatus
US10534257B2 (en) * 2017-05-01 2020-01-14 Lam Research Corporation Layout pattern proximity correction through edge placement error prediction
US20200380362A1 (en) * 2018-02-23 2020-12-03 Asml Netherlands B.V. Methods for training machine learning model for computation lithography
US10572697B2 (en) 2018-04-06 2020-02-25 Lam Research Corporation Method of etch model calibration using optical scatterometry
CN111971551B (zh) 2018-04-10 2025-02-28 朗姆研究公司 机器学习中的光学计量以表征特征
WO2019199697A1 (en) 2018-04-10 2019-10-17 Lam Research Corporation Resist and etch modeling
CN112640037A (zh) 2018-09-03 2021-04-09 首选网络株式会社 学习装置、推理装置、学习模型的生成方法及推理方法
JP7190495B2 (ja) 2018-09-03 2022-12-15 株式会社Preferred Networks 推論方法、推論装置、モデルの生成方法及び学習装置
JP7345382B2 (ja) * 2018-12-28 2023-09-15 東京エレクトロン株式会社 プラズマ処理装置及び制御方法
CN109891414B (zh) 2019-01-28 2023-07-04 长江存储科技有限责任公司 用于设计虚设图案的系统和方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6909930B2 (en) * 2001-07-19 2005-06-21 Hitachi, Ltd. Method and system for monitoring a semiconductor device manufacturing process
US7363099B2 (en) * 2002-06-07 2008-04-22 Cadence Design Systems, Inc. Integrated circuit metrology
JP3639268B2 (ja) * 2002-06-14 2005-04-20 株式会社日立製作所 エッチング処理方法
JP5050830B2 (ja) * 2007-12-19 2012-10-17 ソニー株式会社 ドライエッチング装置および半導体装置の製造方法
JP5440021B2 (ja) * 2009-08-24 2014-03-12 ソニー株式会社 形状シミュレーション装置、形状シミュレーションプログラム、半導体製造装置及び半導体装置の製造方法
JP5732843B2 (ja) * 2010-12-21 2015-06-10 ソニー株式会社 シミュレータ、加工装置、ダメージ評価方法、及び、ダメージ評価プログラム

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Publication number Publication date
JP2015103769A (ja) 2015-06-04
US9431310B2 (en) 2016-08-30
US20150149970A1 (en) 2015-05-28
TW201520803A (zh) 2015-06-01
TWI661323B (zh) 2019-06-01

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