TWI652817B - 形成具有奈米線的半導體結構的方法與具有奈米線的半導體結構 - Google Patents

形成具有奈米線的半導體結構的方法與具有奈米線的半導體結構 Download PDF

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TWI652817B
TWI652817B TW104113734A TW104113734A TWI652817B TW I652817 B TWI652817 B TW I652817B TW 104113734 A TW104113734 A TW 104113734A TW 104113734 A TW104113734 A TW 104113734A TW I652817 B TWI652817 B TW I652817B
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nanowire
semiconductor
fin
forming
contact pad
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TW201630182A (zh
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陳俊仁
蔡濱祥
温在宇
林鈺書
楊進盛
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聯華電子股份有限公司
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Abstract

本發明所提供之形成奈米線的方法，首先先形成一半導體鰭狀結構具有交替的鰭以及淺溝渠隔離。接著移除鰭的一頂面部以形成鰭凹部，並在鰭凹部中沈積鍺基半導體以形成鍺基插栓。後續，移除部分的淺溝渠隔離以暴露出鍺基插栓的側面，隨即進行一退火製程即可形成具有高載子傳輸率的奈米線結構。藉由對鍺基插栓選擇性的氧化或沈積製程，本發明之奈米線結構還可以具有不同尺寸。此外，不同尺寸的奈米線也可藉由形成不同寬度的鰭，或是不同寬度的鰭凹部來達成。

Description

形成具有奈米線的半導體結構的方法與具有奈米線的半導體結構
本發明是關於一種半導體結構，特別來說，是關於一種具有奈米線的半導體結構。
本發明是關於一種形成包含有鰭狀結構(fin structure)半導體積體電路中形成奈米線(nanowire)的方法。由於現今的積體電路正朝向更高積集度的方向發展，三維結構的鰭狀結構已逐漸取代習知的平面電晶體(planar transistor)，藉以增加電子電路的積集度。除此之外，奈米線也較多採用鍺(germanium)材質，相較於習知的矽(silicon)，可以獲得較佳的載子移動率(carrier mobility)。
現今已有一些使用鍺奈米線的鰭狀結構。然而，由於鍺奈米線的尺寸極為精細，其中的製作步驟如磊晶成長製程(epitaxial growth)則有許多限制且難以控管，這提高了製作上述鍺奈米線之困難度。
本發明提供了一種在半導體基底上形成奈米線的新穎方法。根據本發明其中一個實施例，可以在半導體基底上形成不同尺寸的半導體奈米線。本 發明的方法包含：形成一半導體鰭狀結構，半導體鰭狀結構包含複數個具有半導體材料的鰭，以及一淺溝渠隔離設置在鰭之間。接著形成複數個鰭凹部，包含移除鰭之一上部分，以使鰭的一上表面低於淺溝渠隔離的一上表面。後續在鰭凹部中形成一鍺基半導體材料，以形成複數鍺基插栓。形成鍺基插栓後，移除部分的淺溝渠隔離的一上部分，以暴露出鍺基插栓的一側壁。進行一退火製程，以使鍺基插栓的周圍形成一氧化層，形成氧化層包覆的奈米線，並使淺溝渠隔離的至少一部分形成一絕緣層。
根據本發明的另外一個實施例，係提供一種半導體結構，包含一基底、一第一奈米線、一第二奈米線、一第一接觸墊、一第二接觸墊與一閘極結構。第一奈米線設置在基底上。第二奈米線設置在基底上。第一接觸墊設置在第一奈米線的一第一端與該第二奈米線的一第一端。第二接觸墊設置在第一奈米線的一第二端與第二奈米線的一第二端，其中第一接觸墊、第二接觸墊的材質與第一奈米線、第二奈米線的材質不同。閘極結構包圍第一奈米線的一部份與第二奈米線的一部份。
10‧‧‧基底
18‧‧‧絕緣層
11‧‧‧光阻層
12L、12L’‧‧‧線圖案
12S‧‧‧溝槽
13T‧‧‧溝槽
13F,13F’,13F”‧‧‧鰭
13R‧‧‧鰭
14‧‧‧淺溝渠隔離
15、15’‧‧‧鍺基插栓
16、16’‧‧‧外殼
17、17’‧‧‧奈米線
1‧‧‧源極
2‧‧‧汲極
3‧‧‧閘極結構
3’‧‧‧通道區
4‧‧‧接觸墊
5‧‧‧接觸墊
20‧‧‧蓋氧化物
30‧‧‧矽接墊
40‧‧‧遮罩
第1A圖、第1B圖、第1C圖、第1D圖、第1E圖、第1F圖、第1G圖、第1H圖、第1I圖與第1J圖，所繪示為本發明一種形成半導體結構的其中一實施例的示意圖。
第2A圖、第2B圖、第2C圖、第2D圖、第2E圖、第2F圖、第2G圖、第2H圖、第2I圖、第2J圖、第2K圖與第2L圖，所繪示為本發明一種形成半導體結構的另一實施例的示意圖。
第3A圖、第3B圖、第3C圖、第3D圖，所繪示為本發明一種形成半導體結構的另一實施例的示意圖。
第4A圖、第4B圖、第4C圖、第4D圖，所繪示為本發明一種形成半導體結構的另一實施例的示意圖。
第5A圖、第5B圖、第5C圖，所繪示為本發明一種形成半導體結構的另一實施例的示意圖。
第6A圖、第6B圖、第6C圖、第6D圖、第6E圖、第6F圖、第6G圖、第6H圖、第6I圖、第6J圖，所繪示為本發明一種形成半導體結構的另一實施例的示意圖。
第7A圖、第7B圖、第7C圖、第7D圖、第7E圖、第7F圖、第7G圖、第7H圖、第7I圖、第7J圖、第7K圖、第7L圖與第7M圖，所繪示為本發明一種形成半導體結構的另一實施例的示意圖。
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明，下文特列舉本發明之數個較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效。
請參考第1A圖至第1J圖，所繪示為本發明一種形成半導體結構的其中一實施例的示意圖。請先參考第1A圖與第1B圖。首先，在一基底10的表面上覆蓋一光阻層11。基底10可以包含各種形式之元素矽或鍺、III/V族複合材料如砷化鎵(GaAs)、矽覆絕緣(silicon on insulator,SOI)或埋入氧化物半導體層(buried oxide semiconductor,BOX)，但並不以此為限。接著圖案化光阻層11以形成一陣列圖案(array)，其包含複數條平行之線圖案12L以及溝槽12S。如第1C圖所示，進行一乾蝕刻製程，蝕刻未被圖案化光阻層11覆蓋之基底10，以形成複數個溝 渠13T。於一實施例中，可使用六氟化硫(sulfur hexafluoride,SF6)作為蝕刻氣體以形成溝渠13T，使該溝渠13T被鰭(fin)13F分隔。如第1D圖所示，在溝渠13T中形成淺溝渠隔離(shallow trench isolation,STI)14，其材質較佳包含介電材料如氧化矽(silicon oxide)。如第1E圖，進行一平坦化製程以形成半導體鰭狀結構，其包含複數個鰭13F以及位於鰭13F之間的淺溝渠隔離14。平坦化製程主要施加在介電材料上，於一實施例中，平坦化製程可以是化學機械研磨(chemical mechanical polish,CMP)、回蝕刻製程或是兩者的組合。在圖式中僅繪示了兩個鰭13F，但本領域具有通常知識者皆應了解，本發明也可能包含兩個以上之鰭13F以及位於其中的淺溝渠隔離14，以構成半導體鰭狀結構。
此外，本發明形成前述鰭狀結構的方法並不限於前述實施例，而也可包含其他不同方法或改良之實施方式。
在形成半導體鰭狀結構後，移除半導體鰭狀結構之頂部以形成鰭凹部(fin recess)13R。藉由圖案化以及蝕刻步驟，可移除具有半導體材質的鰭的部份。於一實施例中，將一光阻層(圖未示)圖案化後，隨之可利用此圖案化光阻層進行例如一乾蝕刻步驟，以移除部分的鰭13F，如第1F圖所示。除前述以六氟化硫為蝕刻氣體的實施方式外，蝕刻氣體也可包含溴化氫(HBr)、氯氣(Cl2)、氧氣(O2)、氦氣(He)或其結合。乾蝕刻步驟會移除未被覆蓋或是暴露出來的基底10的部份。於其他實施例中，蝕刻氣體也可以包含如碳氟化合物(fluorocarbon)、硼(boron)、三氯化合物(trichloride)或其他適合的蝕刻氣體。
形成鰭凹部13R後，在此鰭凹部13R中形成鍺質(germanium-based)的半導體材質，以形成一鍺質插栓(germanium-based plug)15，如第1G所示。於一 實施例中，鍺質半導體材質可以包含如鍺(Ge)、矽鍺(SiGe)或鍺錫(GeSn)，但並不以此為限。鍺質半導體材質可以用任何適合的方式形成，例如是磊晶成長製程，舉例來說，以磊晶成長形成如矽鍺Si1-xGex，其中.05<x<.15，或.15<x<.25或是.25<x<.35。磊晶成長製程可沿著不同軸向生長，其較佳沿著暴露的鰭表面的晶格方向(crystal lattice)成長。此外，藉由移除基底時的半導體晶格方向控制，亦可調控磊晶成長製程。因鍺基插栓15的尺寸範圍是由鰭凹部13R的區域所界定，故可忽略矽基底10晶格方向的影響。於本發明之一實施例中，鍺基插栓15的尺寸範圍是由微影步驟來控制，相較於單純以磊晶成長製成，微影步驟的控制力較佳。
鍺基插栓15後續進行一氧化/退火階段，以使之後形成奈米線具有高載子遷移率(carrier mobility)。由於退火製程可能可以改變鍺基插栓15的尺寸或形狀，因此，於一實施例中，所形成的鰭13F的寬度和鰭凹部13R的深度，較佳還須考慮到鍺基插栓15之材料。
例如，當使用鍺沈積以形成鍺基插栓15時，退火製程並不會改變太多其體積；故如果預計形成的奈米線的直徑為10奈米，在設計上，鰭凹部13R的深度(或寬度)將接近或稍大於10nm。另一方面，如果以矽鍺沈積作為鍺基插栓15時，退火之後所得到的奈米線的大小取決於鍺的濃度。例如，在50%的鍺含量的情況下，若欲形成的奈米線直徑為10nm，則鰭凹部13R的深度(或寬度)應接近或稍大於20nm。
當鰭凹部13R的寬度與深度比大約為1：1時，在退火製程後，將形成具有近似圓形橫截面之奈米線。如果寬度與深度比偏離1：1，得到的奈米線將 具有橢圓形橫截面。於本發明之一實施例中，鍺基插栓15包含鍺，且形成鰭凹部13R時，該鰭凹部13R的寬度與深度比為1：1。而在本發明另外一個實施例中，鍺基插栓15包含鍺錫，且形成鰭凹部13R時，鰭凹部13R的寬度與深度比為1：2。
如第1H圖所示，在磊晶成長形成鍺基插栓15後，部分地移除淺溝渠隔離14，以暴露鍺基插栓15的側面。此淺溝渠隔離14的回蝕刻可以包含濕蝕刻或乾蝕刻。於一實施例中，蝕刻淺溝渠隔離14至一預定深度為止，以暴露鍺基插栓15，可使用含有氫原子之蝕刻氣體，例如氫氟酸(HF)或氨(NH3)，但並不以此為限。於另一實施例中，亦可使用選擇性材料去除技術，例如由應用材料公司(Applied Material)所提供之SiCoNiTM，以去除淺溝渠隔離14並控制剩餘材料的高度。
如第1I圖所示，進行氧化/退火步驟，以露出鍺基插栓15和淺溝渠隔離14。於一實施例中，氧化和退火可以同時進行，或是先進行氧化再進行退火。於一實施例中，可在進行數次的氧化循環之後進行適當溫度的退火製程，故在鍺基插栓15為SiGe的實施例中，可調控鍺達到一定的比例。一實施例中，氧化/退火是在低於鍺基插栓15熔點的溫度下進行，例如，在約950ºC時，會產生的具有黏稠流動氧化矽。
於一實施例中，氧化製程包含使用氧氣(dry oxygen)並搭配一稀釋氣體或載氣(carrier gas)。在一實施例中，稀釋氣體或載氣是非氧化性氣體，如氮氣(N2)或氫氣/氮氣(H2/N2)。另一實施例中，稀釋氣體或載氣是惰性氣體，如氬氣或氦氣。另一方面，退火製程若是在次大氣壓或半真空的環境下進行，其使用的氣體可包含如前述氧化製程的稀釋氣體或是載氣。
當鍺基插栓15為鍺矽材質時，鍺和矽在氧化和退火製程中具有特殊的重新分配機制。在鍺與矽的比例與含量在一特定值時，氧相較於鍺在氧化製程中在表面處較容易被氧化。因此，當在矽鰭13F上鍺基插栓15接受加熱時，如第1J圖所示，矽會朝著氧化表面(向外)擴散，形成具有氧化矽的外殼(shell)16，而鍺則遠離表面(向內)擴散，而形成鍺奈米線通道。在一般情況下，矽的重新分配速率隨溫度的增加而增加，而隨著壓力增加而減小。如圖所示，氧化/退火製程形成鍺奈米線通道17，並且鰭狀結構也被氧化，而形成在基底10上的絕緣層18。
於一實施例中，可用習知的蝕刻步驟以挖深氧化材料，使前述奈米線通道形成奈米線，並懸浮遠離基底。請參考第2A圖至第2L圖，所繪示為本發明一種形成半導體結構的另一實施例的示意圖。其中，本實施例在第2A圖至第2G圖與前實施例中第1A圖至第1G圖大致相同，在此不加以贅述。和前述實施例中中的第1H圖與第1J圖相比，本實施例去除淺溝渠隔離14的量可以變化，以利後續形成一個獨立的奈米線。如第2H圖，將淺溝渠隔離14蝕刻至一較深的深度。第2I圖中進行將鍺基插栓15與暴露的鰭13F的氧化步驟。第2J圖中移除氧化部分，以形成懸浮之半導體插栓15。第2L圖表示退火後形成之懸浮的奈米線17。第2L圖中雖然繪示了殘留的鰭13F”，但於另一實施例中，在第2H圖的步驟中亦可完成移除淺溝渠隔離14而暴露鰭的整個側面，故在第2L圖中不會有殘留的鰭部分。
此外，奈米線所暴露的長度也可藉由形成鰭凹部13R之蝕刻步驟(如第2F圖)來決定。請參考第3A圖與第4A圖，其對應了在第2E圖中的鰭13F的上視 圖。在一實施例中，形成如第2F圖的鰭凹部所使用的遮罩會覆蓋整個鰭13F，如第3B圖所示。而於另一實施例中，僅有部分的鰭13被遮罩覆蓋，如第4B圖所示。
在進行完第3B圖和第4B圖以形成鰭凹部的步驟後，接著形成鍺基插栓(第2G圖)。在懸浮的奈米線的實施例中，當形成鍺基插栓形成後，形成一蓋氧化物(cap oxide)20並暴露出其中央部(如第3C圖與第4C圖中的虛線表示)。此中央的開口部是藉由微影與蝕刻製程來形成。當開口部被暴露出來後，透過如第2I圖至第2J圖的步驟來移除鍺基插栓15下方的具有矽材質的鰭，接著如第2K圖進行氧化/退火製程，以形成懸浮之奈米線，最後再移除蓋氧化物20。第3C圖與第4C圖對應顯示了鍺基插栓15進行氧化/退火製程後形成奈米線17之步驟，而第3D圖與第4D圖則是沿著第3C圖與第4C圖的Y切線所繪製的剖面示意圖。如第3D圖的實施例，整個奈米線17會被暴露出來，但在第4D圖的實施例中，則僅有部分的奈米線17被暴露出來。在第3D圖中，此奈米線17連接位在底下的矽接墊(silicon pad)30，且需注意的是為了繪圖之簡潔，第3D圖並沒有顯示出外殼16。在第4D圖中，奈米線之兩終端點連接至矽接墊30。
本發明所示之鍺基奈米線結構可作為一閘極結構3中的通道3’部位，其位在一汲極1與一源極2之間，而構成了如第5A圖與第5B圖所示的場效電晶體(field effect transistor,FET)結構。第5A圖繪示了一立體示意圖，第5B圖則繪示了上視圖。在第5B圖中，共用源極墊4與共用汲極墊5使用了與奈米線17不同的材料。於本發明之一實施例中，奈米線17包含了矽材質的一源極區1與一汲極區2，以及鍺材質的的通道區3’。而根據半導體產品的設計不同，其源極區與汲極區也可各自包含相同或不同的材料。第5A圖顯示了奈米線兩端終點延伸終點為矽接墊4和5；第5C圖顯示了奈米線設置在矽接墊4和5的上方。
上文中描述了一種形成半導體結構的方法，由此形成的奈米線大致相同的直徑。然而，具有奈米線的FET結構，需要考慮不同的驅動電流強度和不同閾值電壓，而在具有全部相同直徑的奈米線若需要呈現不同的驅動電流強度和不同閥值電壓，則必須各別調控其閘極功函數。這對於裝置的設計以及製作流程都是極大的考驗，也增加了製作的成本。
本發明的另外之實施例中，提供了具有不同直徑的奈米線結構與其製作方法。不同直徑的奈米線可以被用來連接具有不同的半導體特性或類似的半導體特性的場效電晶體中的的源極和汲極區。
請參考第6A圖至第6J圖，其繪示了本發明中用來形成有不同奈米線的實施例示意圖，其中部分步驟與實施方式與前述實施例中第1A圖至第1J圖相同或類似，故重複之部分不再加以描述。本實施例特別之處在於，鰭13F與鰭13F’具有不同的寬度，這可以藉由圖案化遮罩11的微影或蝕刻步驟來定義。舉例來說，在第6B圖中，兩大體上平行之線圖案12L與12L’具有不同的寬度，並藉由微影步驟之調控，後續形成之鰭13F與鰭13F’之寬度即可不同。並且，由於鰭凹部的深度可以調控，經過退火後之奈米線的尺寸也可以被精確控制，而各自形成所欲之不同直徑的奈米線。是故，這些不同直徑比例的奈米線可根據產品設計而形成。第6I圖顯示了不同尺寸形成之鍺基插栓15與鍺基插栓15’，故在第6J圖中所形成的奈米線17與奈米線17’也具有不同的尺寸。於本發明之一實施例中，奈米線17與奈米線17’的截面的尺寸具有一預定比值，且此比值可為一整數。
由於鰭13F與鰭13F’存在著寬度上的差異，故氧化/退火製程必需也有 調整。一般來說，氧化/退火過程是由時間和濃度來控制。如果鰭13F'的寬度與鰭13F的寬度比例為2：1，在兩者都在相同氧化回火的環境下，則兩者充分完成退火的時間會正比於其寬度，也就是近似於2：1。在本發明一個實施例中，可以控制退火時間以個別控制每個奈米線的退火程度。而在本發明較佳實施例中，退火時間以能滿足最寬的鍺基插栓15’或奈米線17’為主，故能使所有的奈米線都被完全退火。以此方式，鍺基插栓15的尺寸主要是由鰭凹部13R的寬度來決定，而非由退火製程之製程變異來決定。
請參考第7A圖至第7M圖，其繪示了本發明一種形成具有不同直徑的奈米線的半導體結構的步驟示意圖。本實施例一開始的步驟大致上與前述實施例的第1A圖至第1H圖相同。然而，在進行如第7H圖的回蝕刻氧化物後，額外的進行一遮罩(masking)步驟。如第7I圖所示，一遮罩40會覆蓋在鰭13F與鍺基插栓15以及部分位在淺溝渠隔離14中的氧化層上，但會暴露鰭13F’、鍺基插栓15’與部分位在淺溝渠隔離14的氧化層。遮罩40可避免鰭13F與鍺基插栓15接受其他製程之修飾。遮罩40可以是光阻層或是硬遮罩的材質，例如氮化矽(Si3N4)。而未被遮罩40覆蓋而暴露之鰭13F’與鍺基插栓15’，則施加一處理，例如是氧化處理或是蝕刻步驟。如第7J圖所示，氧化處理使一部分的鰭13F’以及部分的鍺基插栓15’形成二氧化矽。由於鰭13F與鍺基插栓15被遮罩40覆蓋，故其並不會被氧化所消耗。因此如第7K圖所示，鰭13F’與鍺基插栓15’，相較於鰭13F與鍺基插栓15而言，具有較小的尺寸。這種尺寸的差異將會導致後續奈米線的不同。如第7L圖所示，進行一氧化/退火步驟以部分地氧化半導體鰭狀結構，詳細的步驟如前述實施例的第1I圖所示。最後第7M圖所示，即可形成具有不同尺寸的奈米線17與17’。值得注意的是，前述以薄化暴露之鰭13F’與鍺基插栓15’的步驟可以用一次性的步驟完成，或者透過複數次的工序來完成，以達到選擇性薄化尺寸的目的。
於本發明另外一個實施例中，前述未被遮罩40覆蓋的鰭13F’與鍺基插栓15’也可進行一額外的處理以增加其尺寸。舉例賴說，此處理包含一清洗步驟(以剝離原生氧化物)以及一選擇性磊晶生長製程。在選擇性磊晶成長製程中，可以使用含氯的矽前驅物，如四氯化矽(SiCl4)和二氯矽烷(H2SiCl2)，或是使用矽烷(SiH4)和鹽酸(HCl)的混合物。選擇性磊晶成長的溫度取決於所使用的矽前驅物材料。
本發明具有不同尺寸的奈米線可以具有不同的驅動電流和/或不同的閾值電壓。如此一來，可以藉由此種控制不同氧化處理後之插栓的相對尺寸的方式，而進行調控由鍺基插栓15與15’所生成的奈米線的電路特性。
另一方面，也可參考搭配第2A圖至第2L圖的實施方式，而形成具有懸浮結構且不同尺寸的奈米線結構。
綜上所述，本發明提供了一種鍺基質的奈米線結構，以增加其載子傳輸率。本發明還提供一種得以形成不同尺寸的奈米線結構的方法，並可藉由適當的製程調控彼此之間尺寸的比例。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。

Claims (16)

  1. 一種在半導體基底上形成奈米線的方法，包含：形成一半導體鰭狀結構，該半導體鰭狀結構包含複數個具有半導體材料的鰭，以及一淺溝渠隔離設置在該等鰭之間；形成複數個鰭凹部，包含移除該等鰭之一上部分，以使各該鰭的一上表面低於該淺溝渠隔離的一上表面；在各該鰭凹部中形成一鍺基半導體材料，以形成複數鍺基插栓；形成該等鍺基插栓後，移除部分的該淺溝渠隔離的一上部分，以暴露出該等鍺基插栓的一側壁；以及進行一退火製程，以使該等鍺基插栓的周圍形成一氧化層，形成被該氧化層包覆的奈米線，並使該淺溝渠隔離的至少一部分形成一絕緣層。
  2. 如申請專利範圍第1項所述的在半導體基底上形成奈米線的方法，其中在形成該半導體鰭狀結構的步驟中，包含使其中一個該鰭的寬度與其他該等鰭的寬度不同。
  3. 如申請專利範圍第1項所述的在半導體基底上形成奈米線的方法，在移除部分的該淺溝渠隔離的一上部分以暴露出該等鍺基插栓的一側壁之後，以及進行該退火製程之前，還包含：形成一遮罩，覆蓋在至少一個該鍺基插栓上，並暴露至少一個該鍺基插栓，以形成一部分遮罩之半導體鰭狀結構；對該部分遮罩之半導體鰭狀結構進行一氧化製程；以及進行該氧化製程後，移除該遮罩。
  4. 如申請專利範圍第1項所述的在半導體基底上形成奈米線的方法，其中該鍺基插栓包含鍺(Ge)或鍺錫(GeSn)。
  5. 如申請專利範圍第4項所述的在半導體基底上形成奈米線的方法，其中該鍺基插栓包含鍺，且形成該鰭凹部時，該鰭凹部的寬度與深度比為1：1。
  6. 如申請專利範圍第4項所述的在半導體基底上形成奈米線的方法，其中該鍺基插栓包含鍺錫，且形成該鰭凹部時，該鰭凹部的寬度與深度比為1：2。
  7. 如申請專利範圍第1項所述的在半導體基底上形成奈米線的方法，在形成該半導體鰭狀結構之前，更包含決定其中一個奈米線的一第一目標尺寸，並根據該第一目標尺寸以形成該半導體鰭狀結構中的該等鰭的尺寸，以及該等鰭凹部的尺寸。
  8. 如申請專利範圍第7項所述的在半導體基底上形成奈米線的方法，在形成該半導體鰭狀結構之前，更包含決定其中一個奈米線的一第二目標尺寸，並根據該第一目標尺寸與該第二目標尺寸以形成該半導體鰭狀結構中的該等鰭的尺寸，以及該等鰭凹部的尺寸，其中該第一目標尺寸與該第二目標尺寸不同。
  9. 一種半導體結構，包含：一基底；一第一奈米線設置在該基底上；一第二奈米線設置在該基底上；一第一接觸墊設置在該第一奈米線的一第一端與該第二奈米線的一第一端； 一第二接觸墊設置在該第一奈米線的一第二端與該第二奈米線的一第二端，其中該第一接觸墊、該第二接觸墊的材質與該第一奈米線、該第二奈米線的材質不同；以及一閘極結構包圍該第一奈米線的部份與該第二奈米線的部份，其中該第一奈米線包含一源極區、一汲極區以及一通道區，該通道區在該源極區和該汲極區之間，其中該通道區的材質與該源極區與該汲極區的不同。
  10. 如申請專利範圍第9項所述之半導體結構，其中該第一奈米線的剖面具有一第一尺寸，該第二奈米線的剖面具有一第二尺寸，該第一尺寸不同於該第二尺寸，且兩者的比值為一預定值。
  11. 如申請專利範圍第10項所述之半導體結構，其中該預定值為一整數。
  12. 如申請專利範圍第9項所述之半導體結構，其中該第一接觸墊與該第二接觸墊共用(common)該第一奈米線與該第二奈米線，且設置在該第一奈米線與該第二奈米線的兩端。
  13. 如申請專利範圍第9項所述之半導體結構，其中第一奈米線與該第二奈米線透過其端點介面(end faces)電性連接該第一接觸墊與該第二接觸墊。
  14. 如申請專利範圍第9項所述之半導體結構，其中該第一奈米線與該第二奈米線設置在該第一接觸墊與該第二接觸墊的頂面上。
  15. 如申請專利範圍第9項所述之半導體結構，其中該第一接觸墊、該第 二接觸墊的材質與該第一奈米線、該第二奈米線具有不同的半導體材質。
  16. 如申請專利範圍第9項所述之半導體結構，其中該基底具有一鰭，對應該第一奈米線與該第二奈米線。
TW104113734A 2015-02-03 2015-04-29 形成具有奈米線的半導體結構的方法與具有奈米線的半導體結構 TWI652817B (zh)

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