TWI651812B - 半導體裝置與其形成方法 - Google Patents

半導體裝置與其形成方法 Download PDF

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TWI651812B
TWI651812B TW104116909A TW104116909A TWI651812B TW I651812 B TWI651812 B TW I651812B TW 104116909 A TW104116909 A TW 104116909A TW 104116909 A TW104116909 A TW 104116909A TW I651812 B TWI651812 B TW I651812B
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Taiwan
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forming
semiconductor structure
patterned mask
mask layer
patterns
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TW104116909A
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TW201642397A (zh
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洪慶文
羅偉銓
陳明瑞
呂佳霖
吳家榮
李怡慧
劉盈成
吳奕寬
黃志森
陳意維
殷旦雅
黃家緯
王淑如
鄭永豐
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聯華電子股份有限公司
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Priority to TW104116909A priority Critical patent/TWI651812B/zh
Priority to US14/793,714 priority patent/US9613969B2/en
Publication of TW201642397A publication Critical patent/TW201642397A/zh
Priority to US15/434,067 priority patent/US9859170B2/en
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Publication of TWI651812B publication Critical patent/TWI651812B/zh

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Abstract

本發明提供一種半導體結構，包含一基底、複數個鰭狀結構、複數個閘極結構、一介電層以及複數個接觸插栓。基底具有一記憶體區。鰭狀結構設置於基底上之記憶體區內，各鰭狀結構沿著一第一方向延伸。閘極結構設置於鰭狀結構上，各閘極結構沿著一第二方向延伸。介電層設置在閘極結構以及鰭狀結構上。接觸插栓設置在介電層中，各接觸插栓與鰭狀結構中的一源極/汲極區電性接觸，且接觸插栓從上視圖來看為一梯形或五邊形。本發明還提供了一種形成前述半導體結構的方法。

Description

半導體裝置與其形成方法
本發明是關於一種半導體裝置與其形成方法，特別來說，是關於一種具有接觸差栓的半導體裝置與其形成方法。
在習知半導體產業中，多晶矽係廣泛地應用於半導體元件如金氧半導體(metal-oxide-semiconductor，MOS)電晶體中，作為標準的閘極填充材料選擇。然而，隨著MOS電晶體尺寸持續地微縮，傳統多晶矽閘極因硼穿透(boron penetration)效應導致元件效能降低，及其難以避免的空乏效應(depletion effect)等問題，使得等效的閘極介電層厚度增加、閘極電容值下降，進而導致元件驅動能力的衰退等困境。因此，半導體業界更嘗試以新的閘極填充材料，例如利用功函數(work function)金屬來取代傳統的多晶矽閘極，用以作為匹配高介電常數(high-k)閘極介電層的控制電極。
一般而言，傳統平面型金屬閘極電晶體通常採用離子佈植的方式來同時調整電晶體的閾值電壓。然而隨著場效電晶體(field effect transistors，FETs)元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭 狀場效電晶體(fin field effect transistor，Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。然而現今鰭狀場效電晶體的製程已無法單純藉由離子佈植來調整電晶體的閾值電壓，因此如何在鰭狀電晶體的架構下改良此缺點即為現今一重要課題。
本發明於是提供一種半導體結構，其製程簡單，也可以提昇產品之良率。
根據本發明其中一個實施方式，係提供一種半導體結構，包含一基底、複數個鰭狀結構、複數個閘極結構、一介電層以及複數個接觸插栓。基底具有一記憶體區。鰭狀結構設置於基底上之記憶體區內，各鰭狀結構沿著一第一方向延伸。閘極結構設置於鰭狀結構上，各閘極結構沿著一第二方向延伸。介電層設置在閘極結構以及鰭狀結構上。接觸插栓設置在介電層中，各接觸插栓與鰭狀結構中的一源極/汲極區電性接觸，且接觸插栓從上視圖來看為一梯形或五邊形。
根據本發明另一個實施方式，係提供一種形成半導體結構的方法。首先，提供一基底，具有一記憶體區。接著於基底之記憶體區中形成複數個鰭狀結構，各鰭狀結構沿著一第一方向延伸，並在鰭狀結構上形成複數個閘極結構，各閘極結構沿著一第二方向延伸。然後於閘極結構以及鰭狀結構上形成一介電層。後續，於介電層上形成一第一圖案化遮罩層，第一圖案化遮罩層具有複數個第一溝渠，且從上視圖來看，各第一溝渠沿伸於第二方向且會穿越記憶體區；於第一圖案化遮罩層上形成一第二圖案化遮罩層，第二圖案化遮罩層具 有複數個第二圖案延伸於第一方向，且從上試圖來看，各第二圖案沿伸於第一方向且會穿越該記憶體區。然後以第一圖案化遮罩層以及第二圖案化遮罩層為遮罩，圖案化介電層以形成複數個接觸孔。最後於接觸孔中填入一導電材料，以形成複數個接觸插栓。
本發明所提供之半導體結構以及形成所述半導體結構的方法，由於在第一圖案化遮罩層以第二圖案化遮罩層中使用了較容易形成的圖案，因此可以增加良率。且根據不同實施方式，也可以形成特殊形狀的接觸插栓。
300‧‧‧基底
302‧‧‧淺溝渠隔離
304‧‧‧鰭狀結構
306‧‧‧閘極結構
308‧‧‧電晶體
308N,308N’‧‧‧N型電晶體
308P‧‧‧P型電晶體
310‧‧‧蓋層
312‧‧‧閘極層
314‧‧‧閘極介電層
316‧‧‧側壁子
317‧‧‧源極/汲極區
318‧‧‧輕摻雜汲極區
319‧‧‧第一內層介電層
321‧‧‧第二內層介電層
320‧‧‧第一圖案化遮罩層
322‧‧‧第一溝渠
324,324’‧‧‧第二圖案化遮罩層
326‧‧‧第一圖案
328,328A,328B,328’‧‧‧第二圖案
330‧‧‧第三圖案
332‧‧‧接觸通孔
334,334A,334B,334C,334D‧‧‧接觸插栓
400‧‧‧記憶體區
400A,400B,400C,400D‧‧‧邊界
402‧‧‧記憶胞區
404‧‧‧第一方向
406‧‧‧第二方向
408‧‧‧第三方向
410‧‧‧第四方向
第1A圖、第1B圖、第2A圖、第2B圖、第3A圖、第3B圖、第4A圖與第4B圖為本發明其中一個實施例中一種製作半導體結構的步驟示意圖。
第5圖與第6圖為本發明另外一個實施例中一種製作半導體結構的步驟示意圖。
第7圖為本發明一種半導體結構其中一種實施例的示意圖。
第8圖為本發明一個記憶胞區中六電晶體的等效電路圖。
為使熟習本發明所屬技術領域的一般技藝者能更進一步了解本發明，下文特列舉本發明的數個較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成的功效。
請參考第1A圖、第1B圖、第2A圖、第2B圖、第3A圖、第3B圖、第 4A圖與第4B圖，所繪示為本發明一種製作半導體結構的步驟示意圖，其中第1A圖、第2A圖、第3A圖、第4A圖為上視圖，而第1B圖、第2B圖、第3B圖與第4B圖分別為沿著上述第1A圖、第2A圖、第3A圖、第4A圖之AA’切線所繪製的剖面示意圖。
請先參考第1A圖與第1B圖。首先提供一基底300，其係用來在其上形成所需之元件或電路。基底300較佳具有含矽材質，例如是矽、單晶矽(single crystal silicon)、單晶矽鍺(single crystal silicon germanium)、非晶矽(amorphous silicon)或是上述的組合。於另一實施例中，基底300也可以包含其他半導體材質，例如是鍺或III/V族的複合半導體材料，如鍺砷等。於另一實施例中，基底300也可以包含其他介電材料，例如是矽覆絕緣基底(silicon on insulator,SOI)。於本發明之一實施例中，基底300上具有一記憶體區400。請參考第7圖，所繪示為本發明一種半導體結構其中一種實施例的示意圖。如第7圖所示，晶片1000上具有一記憶體區400。於本發明之一實施例中，記憶體區400是一靜態隨機存取記憶體(Static Random-Access Memory,SRAM)區。於本發明其中實施例中，晶片1000上還可以具有其他邏輯(logic)或是非邏輯的區域，例如是中央處理器(central processing unit,CPU)區500或是射頻(radio frequency,RF)區600，且並不以上述為限。請再次參考第1A圖與第1B圖，如第1A圖與第1B圖所示，在基底300之記憶體區400中形成複數個淺溝渠隔離302、複數個鰭狀結構(fin structure)304以及複數個閘極結構306。如第1A圖之上視圖所示，淺溝渠隔離302包圍了每個鰭狀結構304，鰭狀結構304彼此之間平行，且沿著一第一方向404延伸；每個閘極結構306跨越鰭狀結構304以及淺溝渠隔離302，每個閘極結構306彼此之間平行，且沿著一第二方向406延伸。於一實施例中，第一方向404大體上與第二方向406垂直。形成鰭狀結構304的步驟，例如在基底300上形成一圖案化遮罩層(圖未示) 後，以該圖案化遮罩層為遮罩蝕刻基底300，以形成複數個溝渠(圖未示)，後續以絕緣材料如二氧化矽(SiO2)填入溝渠中，並利用平坦化及回蝕刻等步驟，使得位在溝渠中的絕緣材料形成淺溝渠隔離(shallow trench isolation,STI)302，而突出於淺溝渠隔離302之基底300的部份，則形成複數個鰭狀結構304。後續，則接續形成閘極結構306。形成閘極結構306的方式例如在鰭狀結構304(或基底300)上依序沈積一閘極介電材料層(圖未示)、閘極材料層(圖未示)、蓋層材料層(圖未示)，接著圖案化上述材料層，以形成該閘極結構306。彼此交錯之鰭狀結構304以及閘極結構306於是形成了複數個電晶體308。於本發明之一實施例中，此記憶體區400是一靜態隨機存取記憶體區並包含複數個記憶胞區402，更詳細來說，記憶體區400為六電晶體儲存胞(6T)之靜態隨機存取記憶體區，因此在一記憶胞區402中，會具有6個電晶體，包含有兩個P型電晶體308P、兩個N型電晶體308N與兩個N型電晶體308N’。請參考第8圖，所繪示為本發明一個記憶胞區中六電晶體的等效電路圖。如第8圖所示，兩個電晶體308N是作為記憶胞中的傳輸電晶體(passage transistor,PG)，兩個電晶體308N’是作為記憶胞中的下拉電晶體(pull-down transistor,PD)，兩個電晶體308P是作為記憶胞中的上拉電晶體(pull-up transistor,PL)，以構成一位元(bit)之儲存空間。然而，前述記憶胞區402之配置僅為本發明其中一種實施方式，根據產品設計的不同，也有可能有其他布局的記憶胞型態。
關於電晶體308的詳細說明，請參考第1B圖。電晶體308包含一閘極結構306、一側壁子316、一源極/汲極區317以及一淺摻雜汲極區(light doped region,LDD)318。於一實施例中，閘極結構306由上而下依序包含一蓋層310、一閘極層312以及一閘極介電層314。蓋層310包含氮化矽(silicon nitride,SiN)、碳化矽(silicon carbide,SiC)或氮氧化矽(silicon oxynitride,SiON)。於一實施例中， 蓋層310可以具有多層結構且各層由不同材料組成，例如蓋層310可以包含一第一蓋層(圖未示)包含氮化矽，以及一第二蓋層(圖未示)包含氧化矽。閘極層312可以包含各種導電材質，例如是多晶矽或者是金屬，例如是鋁(Al)、鈦(Ti)、鉭(Ta)、鎢(W)、鈮(Nb)、鉬(Mo)、銅(Cu)、氮化鈦(TiN)、碳化鈦(TiC)、氮化鉭(TaN)、鈦鎢(Ti/W)或鈦與氮化鈦(Ti/TiN)等複合金屬層料，但不以此為限。閘極介電層314例如是氧化矽或是各種高介電常數材料，前述高介電常數材料的介電常數大約大於4，可以是稀土金屬氧化物層或鑭系金屬氧化物層，例如氧化鉿(hafnium oxide,HfO2)、矽酸鉿氧化合物(hafnium silicon oxide,HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化鋁(aluminum oxide,Al2O3)、氧化鑭(lanthanum oxide,La2O3)、鋁酸鑭(lanthanum aluminum oxide,LaAlO)、氧化鉭(tantalum oxide,Ta2O5)、氧化鋯(zirconium oxide,ZrO2)、矽酸鋯氧化合物(zirconium silicon oxide,ZrSiO4)、鋯酸鉿(hafnium zirconium oxide,HfZrO)、氧化鐿(yttrium oxide,Yb2O3)、氧化矽鐿(yttrium silicon oxide,YbSiO)、鋁酸鋯(zirconium aluminate,ZrAlO)、鋁酸鉿(hafnium aluminate,HfAlO)、氮化鋁(aluminum nitride,AlN)、氧化鈦(titanium oxide,TiO2)，氮氧化鋯(zirconium oxynitride,ZrON)、氮氧化鉿(hafnium oxynitride,HfON)、氮氧矽鋯(zirconium silicon oxynitride,ZrSiON)、氮氧矽鉿(hafnium silicon oxynitride,HfSiON)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)或鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)，但不以上述為限。側壁子316設置在閘極結構306的側壁，可為一複合膜層之結構，其材料包含高溫氧化矽層(high temperature oxide，HTO)、氮化矽、氧化矽或使用六氯二矽烷(hexachlorodisilane，Si2Cl6)形成的氮化矽(HCD-SiN)。輕摻雜汲極區318設置在閘極結構306兩側的鰭狀結構304中，並具有適當導電型的摻質。源極/汲極區317設置在側壁子316(或閘極結構306)兩側的鰭狀結構304 中，並具有適當導電型的摻質。若為N型電晶體308N，則輕摻雜汲極區318與源極/汲極區317具有N型摻質，例如是硼(B)及/或硼氟(BF)；若為P型電晶體308P，則輕摻雜汲極區318與源極/汲極區317具有P型摻質，例如砷(As)及/或磷(P)及/或銻(Sb)，但並不以此為限。於一實施例中，蓋層310、側壁子316或輕摻雜汲極區318可以選擇性的省略。
後續，在基底300上形成一第一內層介電層(inter dielectric layer,ILD layer)319覆蓋在電晶體308上。於一實施例中，第一內層介電層319例如是二氧化矽，其可以由前軀體為四乙氧基矽烷(tetraethyl orthosilicate,TEOS)或是電漿輔助四乙氧基矽烷(plasma enhanced tetraethyl orthosilicate,PETEOS)形成。在形成內層介電層319後，可選擇性的進行一金屬閘極置換製程(metal gate replacement process)，例如包含進行一化學機械研磨製程(chemical mechanical replacement,CMP)以移除蓋層310後，移除閘極層312(或是更移除閘極介電層314)並填入適當的金屬材料(或是還具有閘極介電材料)。接著，在第一內層介電層319上形成一第二內層介電層321，其中第二內層介電層321的材質可以和第一內層介電層319的材質相同也可以不同。於一實施例中，第二內層介電層321也可以省略，但此實施例中第一內層介電層319的頂面較佳高於閘極結構306之頂面。
如第2A圖與第2B圖所示，在第二內層介電層321上形成一第一圖案化遮罩層320。於一實施例中，第一圖案化遮罩層320與第二內層介電層321以及第一內層介電層319具有蝕刻選擇比，其材質例如是氮化鈦(TiN)、氮化鉭(TaN)、氮化矽(silicon nitride,SiN)、氮氧化矽(silicon oxynitride,SiON)、碳化矽(silicon carbide,SiC)或是應用材料公司提供之進階圖案化薄膜(advanced pattern film,APF)、或上述者的任意組合、或上述者與其他材料的任意組合。形成第一圖案 化遮罩層320的方法，例如先在第二內層介電層321上全面形成一遮罩材料層(圖未示)，再其上形成一光阻層，並進行一微影暨蝕刻製程(photo-etching-process,PEP)，即可在第一圖案化光阻層320中形成複數個第一溝渠322。如第2A圖的上視圖所示，第一溝渠322彼此之間平行且延伸於第二方向406，且與下方的閘極結構306交替排列。本發明其中一個特點在於，第一溝渠322延伸的範圍為整個記憶體區400，若從第7圖來看，每個第一溝渠322都會自記憶體區400的邊界400A延伸到邊界400C，也就是每個第一溝渠322的長度和記憶體區400的長度(或寬度)相同。
接著，請參考第3A圖與第3B圖，在第一圖案化遮罩層320以及第二介電層321上形成一第二圖案化遮罩層324。如第3A圖的上視圖所示，本發明的第二圖案化遮罩層324包含複數個第一圖案326、複數個第二圖案328以及複數個第三圖案330。第一圖案326沿著第一方向404延伸，且每個第一圖案會跨過三個第一溝渠322；第二圖案328沿著第一方向404延伸，且呈現規律蜿蜒(serpent)的情況，更詳細的說，第二圖案328在第二方向406上的投影會在一固定範圍R內。第二圖案328(例如第二圖案328A)會與相鄰的第二圖案328(例如第二圖案328B)鏡相對稱。此外，第二圖案328延伸的範圍為整個記憶體區400，從第7圖來看，第二圖案328會自記憶體區400的邊界400B延伸到邊界400D，也就是每個第二圖案328的長度和記憶體區400的長度(或寬度)相同；第三圖案則是呈現塊狀(block)，其僅會跨會一個第一溝渠322，且會對應設置在第二圖案328蜿蜒之轉折處並位在蜿蜒之凹處中。在一個記憶胞區402中，包含有兩個第一圖案326之部分、一個第二圖案328之部分以及兩個第三圖案330之部分。如第3B圖之剖面圖所示，第二圖案化遮罩層324僅會填入部分的第一溝渠322中，而有些第二溝渠322則沒有被第二圖案化遮罩層324填入，因而還是暴露出下方的第二介電層 321。第二圖案化遮罩層324的材料會與第一圖案化遮罩層320、第二內層介電層321與第一內層介電層319具有蝕刻選擇比。於一實施例中，第二圖案化遮罩層324包含是氮化鈦、氮化鉭、氮化矽、氮氧化矽、碳化矽或是應用材料公司提供之進階圖案化薄膜、或上述者的任意組合、或上述者與其他材料的任意組合。
請參考第4A圖與第4B圖，以第一圖案化遮罩層320與第二圖案化遮罩層324為遮罩，移除未被第一圖案化遮罩層320與第二圖案化遮罩層324覆蓋之第二內層介電層321以及第一內層介電層319，以形成複數個接觸孔(contact via)332，接觸孔332會暴露電晶體308的源極/汲極區317。後續，在接觸孔332中填入一層或多層的金屬材料，以形成一接觸插栓334。金屬材料例如是，鈦(titanium,Ti)、氮化鈦(titanium nitride,TiN)、tantalum nitride(TaN)、鋁(aluminum,Al)、鈦(titanium,Ti)、鉭(tantalum,Ta)、鎢(tungsten,W)、鈮(niobium,Nb)、鉬(molybdenum,Mo)、銅(copper,Cu)或是上述的組合，但並不以上述為限。
後續，可繼續進行其他的半導體製程，例如在第二內層介電層321中形成複數個通孔插栓(via plug)(圖未示)以各自電性連接電晶體308之閘極結構306的閘極層312。然後形成一金屬內連線系統(metal interconnection system)電性連接接觸插栓334或其他通孔插栓，以提供電晶體308適當的輸出/輸入訊號。
本發明其中一個特點在於，所使用的第一圖案化遮罩層320之第一溝渠322以及第二圖案化遮罩層324之第二圖案328，都為橫跨整個記憶體區400的圖案，相較於習知散落的塊狀圖案或溝渠，本發明的第一溝渠322以及第二圖案328相對容易形成，並且所形成的接觸插栓334從上視圖來看，可以是矩形或正方形等形狀，具有較平整的邊界。
請參考第5圖與第6圖，所繪示為本發明第二實施例的示意圖。此實施例的前段步驟和前述實施例的第1A圖至第2A圖相同，在此不再重複贅述步驟。在形成了第2A圖的第一圖案化遮罩層320後，請見第5圖，形成一第二圖案化遮罩層324’。和第一實施例相比，請見第3A圖，第二圖案328與下方第一溝渠322重疊處的邊界，大體上平行於第一方向404，而有在沒有和第一溝渠322重疊處，其邊界則大體和蜿蜒的方向平行，即平行一第三方向408與一第四方向410。而在本實施例中，第二圖案328’的邊界則完全和蜿蜒的方向平行，並在蜿蜒之轉彎處具有尖角。因此，如第6圖之上視圖所示，所形成之接觸插栓334，在記憶胞區402內則具有四種形態：接觸插栓334A為五邊形，具有一組平行邊平行第二方向406，且具有具有一內角α大於180度；接觸插栓334B為梯形，僅具有一組平行邊平行第二方向406；接觸插栓334C為矩形；接觸插栓334D為五邊形，具有一組平行邊平行第二方向406，且具有一內角β小於180度，且α+β=180度。當然，上述的圖案可能因為實際製程而產生變化，例如其尖角可能具有圓弧，邊界可以具有弧度，但其大體上之形狀仍應屬於本發明的所涵蓋的範圍。
綜上所述，本發明提供了一種半導體結構以及形成所述半導體結構的方法。由於在第一圖案化遮罩層以第二圖案化遮罩層中使用了較容易形成的圖案，因此可以增加良率。且根據不同實施方式，也可以形成特殊形狀的接觸插栓。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。

Claims (20)

  1. 一種半導體結構，包含： 一基底，具有一記憶體區； 複數個鰭狀結構，設置於該基底上之該記憶體區內，各該鰭狀結構沿著一第一方向延伸； 複數個閘極結構，設置於該等鰭狀結構上，各該閘極結構沿著一第二方向延伸； 一介電層設置在該等閘極結構以及該等鰭狀結構上；以及 複數個接觸插栓設置在該介電層中，各該接觸插栓與該鰭狀結構中的一源極/汲極區電性接觸，且該等接觸插栓從上視圖來看為梯形或五邊形。
  2. 根據申請專利範圍第1項所述之半導體結構，其中一個該接觸插栓從上試圖來看為矩形。
  3. 根據申請專利範圍第1項所述之半導體結構，其中一個該接觸插栓從上試圖來看為梯形，僅具有一組平行邊平行於該第二方向。
  4. 根據申請專利範圍第1項所述之半導體結構，其中一個該接觸插栓從上試圖來看為一五邊形，具有一組平行邊平行於該第二方向，且具有一內角大於180度。
  5. 根據申請專利範圍第1項所述之半導體結構，其中一個該接觸插栓從上試圖來看為一五邊形，具有一組平行邊平行於該第二方向，且具有一內角小於180度。
  6. 根據申請專利範圍第1項所述之半導體結構，其中該記憶體區為一靜態隨機存取記憶體(Static Random-Access Memory, SRAM)區。
  7. 根據申請專利範圍第6項所述之半導體結構，其中該靜態隨機存取記憶體區為六電晶體(6T)靜態隨機存取記憶體區。
  8. 一種形成半導體結構的方法，包含： 提供一基底，具有一記憶體區； 於該基底之該記憶體區中形成複數個鰭狀結構，各該鰭狀結構沿著一第一方向延伸； 於該等鰭狀結構上形成複數個閘極結構，各該閘極結構沿著一第二方向延伸； 於該等閘極結構以及該等鰭狀結構上形成一介電層； 於該介電層上形成一第一圖案化遮罩層，該第一圖案化遮罩層具有複數個第一溝渠，且從上視圖來看，各該第一溝渠沿伸於該第二方向且會穿越該記憶體區； 於該第一圖案化遮罩層上形成一第二圖案化遮罩層，該第二圖案化遮罩層具有複數個第二圖案延伸於該第一方向，且從上試圖來看，各該第二圖案沿伸於該第一方向且會穿越該記憶體區；以及 以該第一圖案化遮罩層以及該第二圖案化遮罩層為遮罩，圖案化該介電層以形成複數個接觸孔；以及 於該等接觸孔中填入一導電材料，以形成複數個接觸插栓。
  9. 如申請專利範圍第8項所述之形成半導體結構的方法，其中從上視圖來看，各該第一溝渠與各該閘極結構交替排列。
  10. 如申請專利範圍第8項所述之形成半導體結構的方法，其中該第二圖案化遮罩層還包含複數個第一圖案，從上視圖來看，每個該第一圖案與三個該第一溝渠重疊。
  11. 如申請專利範圍第8項所述之形成半導體結構的方法，其中該第二圖案化遮罩層還包含複數個第三圖案，從上視圖來看，每個該第三圖案與一個該第一溝渠重疊。
  12. 如申請專利範圍第8項所述之形成半導體結構的方法，其中從上視圖來看，各該第二圖案朝一第三方向與一第四方向來回蜿蜒(serpent)。
  13. 如申請專利範圍第12項所述之形成半導體結構的方法，其中從上視圖來看，各該第二圖案與該等第一溝渠重疊處的邊界平行於該第一方向。
  14. 如申請專利範圍第12項所述之形成半導體結構的方法，其中從上視圖來看，各該第二圖案的邊界平行與該第三方向或該第四方向。
  15. 如申請專利範圍第12項所述之形成半導體結構的方法，其中從上視圖來看，該第二圖案與相鄰的該第二圖案鏡相對稱。
  16. 如申請專利範圍第8項所述之形成半導體結構的方法，其中該第一圖案化遮罩層、該第二圖案化遮罩層與該介電層，三者具有蝕刻選擇比。
  17. 如申請專利範圍第8項所述之形成半導體結構的方法，其中該等接觸插栓從上視圖來看為一梯形或五邊形。
  18. 如申請專利範圍第8項所述之形成半導體結構的方法，還包含在該介電層中形成複數個通孔插拴，以電性連接各該閘極結構。
  19. 如申請專利範圍第8項所述之形成半導體結構的方法，其中該記憶體區為一靜態隨機存取記憶體區。
  20. 如申請專利範圍第19項所述之形成半導體結構的方法，其中該靜態隨機存取記憶體區為六電晶體(6T)靜態隨機存取記憶體區。
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