TWI636376B - 用於保全一電子文件之裝置 - Google Patents

用於保全一電子文件之裝置 Download PDF

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TWI636376B
TWI636376B TW101149160A TW101149160A TWI636376B TW I636376 B TWI636376 B TW I636376B TW 101149160 A TW101149160 A TW 101149160A TW 101149160 A TW101149160 A TW 101149160A TW I636376 B TWI636376 B TW I636376B
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current
component
microcircuit card
passive
passive component
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TW201342114A (zh
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克利斯多夫 吉哈德
尼可拉斯 莫琳
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歐貝特科技
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/86—Secure or tamper-resistant housings
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/12—Measuring electrostatic fields or voltage-potential
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/77—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/86—Secure or tamper-resistant housings
    • G06F21/87—Secure or tamper-resistant housings by means of encapsulation, e.g. for integrated circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
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    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07363—Means for preventing undesired reading or writing from or onto record carriers by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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Abstract

此裝置(10)包括：- 至少一個被動元件(40)，其能夠在存在一電場或一磁場之情況下產生一電流；及- 觸發構件(50)，其係為偵測到該電流之後在該電流之強度超過一預定臨限值時之一保護措施。

Description

用於保全一電子文件之裝置
本發明係關於保全電子組件之領域。
故障注入之攻擊眾所周知，此等攻擊由實體上擾動組件以在執行期間修改碼或修改正處置之變量之值組成。
對應錯誤輸出允許攻擊者獲得關於儲存於組件中之秘密之資訊。
用於擾動一組件之一有效構件係使用一光源(舉例而言，一雷射)，該光源對該組件之撞擊之效應係在矽中產生局部光電流以產生一故障。
光擾動之攻擊係半侵入式攻擊，具體而言，其係需要曝露組件之一表面以使得光射線可撞擊該表面之攻擊。
熟習此項技術者藉由一組件之表達「製備」知曉此操作。
有時必須製備一組件之事實使此等攻擊變得困難，舉例而言，此乃因其封裝之性質(一陶瓷覆蓋物難以刺穿)或經實施以防止拆封之對策。
用於擾動一嵌入式組件之另一構件係在矽附近發射一強磁或電脈衝。磁場或電場在組件之表面處在積體電路之金屬層之層級處產生局部電流，此可產生擾動。
與光擾動之攻擊相比，稱為EMFA(電磁故障攻擊)之此等攻擊並不需要製備組件。
舉例而言，在一智慧卡之情形中，注入在卡後方之電磁 擾動可容易透過卡擾動組件。
電磁故障攻擊之記號「EMFA」係實際上涵蓋磁或電類型之注入之一泛用名稱。
在磁擾動之情形中，擾動探針包括發送一局部強大之磁場之一小線圈。被攻擊之組件之敷金屬線接收擾動其操作之感應電流。探針利用感應耦合來注入一擾動電流。
在電擾動之情形中，擾動探針可係到達相對於待攻擊之組件之接地之彼電位之相當大電位之一金屬點(或一小金屬平面)。由探針施加之此電位誘發一電場，該電場之變化在敷金屬線中產生一電流。該探針使用電容性耦合來注入擾動電流。
本發明提出保護一組件免受EMFA類型之攻擊之不同解決方案。
更精確而言，且根據一第一態樣，本發明係關於一種裝置，該裝置包括：-至少一個被動元件，其能夠在存在一電場或一磁場之情況下產生電流；及-在偵測到該電流之後當該電流之強度超過一預定臨限值時即刻觸發模組之一保護措施之構件。
此裝置能夠偵測EMFA(電磁故障攻擊)擾動。
在一較佳實施例中，在本發明之此第一態樣中所使用之被動元件專用於電或磁擾動之偵測。此等元件並不參與對該裝置進行供應。當該裝置與另一裝置(舉例而言，一智 慧卡)交換有用資料(舉例而言，呈命令或回應之形式之訊息)時，本發明之被動元件不同於裝置之介面且並不參與此等有用資料之傳遞。換言之，在此實施例中，被動元件不同於裝置之輸入/輸出。
兩個主要變型係可行的。
在一第一變型中，根據本發明之裝置包括一支撐件(舉例而言，一圓釘(thumbnail))及一組件，其中該被動元件或該等被動元件配置於該支撐件中。
在本發明之一實施例中，配置於該支撐件中之該等被動元件中之至少一者係能夠在存在一磁場之情況下產生電流之一天線。
眾所周知，此電流之強度與磁場之強度實質上成比例。
熟習此項技術者將理解，天線之設計固定可由本發明偵測到之波之頻寬之寬度。
在本發明之一特定實施例中，天線組織於一網路中，較佳地在支撐件之整個表面上方，每一天線充當一磁感測器。
較佳地，該網路之天線具有達成對不同頻寬之磁場之偵測之不同特性。
在另一實施例中，配置於該支撐件中之該等被動元件中之至少一者係能夠在存在一電場之情況下產生電流之一金屬平面。
在此實施例中，金屬平面藉由加強與擾動源之電容耦合來擷取電場。
如在天線之情形中，由金屬平面遞送之電流之強度隨著電場之強度增加。更精確而言，電流之強度等於存在於擾動探針(電場之發送者)與金屬平面之間的電位之導數乘以該探針與該平面之間的等效電容。
金屬平面亦可配置於一網路中，較佳地在支撐件之整個表面上方，每一金屬平面充當一電感測器。
該網路之金屬平面亦可經設計以偵測不同類型之電場。
在本發明之另一變型中，根據本發明之裝置係一組件，該被動元件或該等被動元件(天線或金屬平面)配置於該組件之一敷金屬層中。
此敷金屬層較佳地位於作用部分之一保護層下方。以一已知方式，此保護層(「保護遮蔽物」)構成在該組件經更改時防止其起作用之第一層。
有利地保護此實施例免受力圖移除包括被動元件之該層之一攻擊。
根據本發明，在兩種變型中，根據本發明之裝置包括在電流之強度超過一臨限值時觸發一對策之構件。
可根據電磁相容性標準(CEM)定義此臨限值。
在一特定實施例中，觸發一對策之此等構件包括一熔絲，該熔絲經放置與被動元件串聯且經定尺寸以在強度大於以上臨限值之一電流通過其時熔融。
在另一實施例中，觸發一對策之構件包括用於比較與由被動元件產生之電流成比例之一第一電壓與一電壓臨限值之構件。
在一特定實施例中，該對策由附著一介面信號與併入有該裝置之一微電路卡組成。
特定而言，本發明在該裝置併入至一智慧卡中時應用於附著根據標準ISO7816之一介面信號，舉例而言，一時脈信號、一輸入/輸出信號或一重新初始化信號。
本發明亦規定包括諸如上文所提及之一裝置之一微電路卡。
在一實施例中，該裝置係一積體電路。
此積體電路可經設計以在一電話中使用。特定而言，其可係一用戶至行動電話網路之一識別電路。舉例而言，該裝置係一SIM卡。
作為一變體，該裝置配置於一銀行卡或一身份證件內部。
舉例而言，該裝置遵循FIPS標準或共同準則。
根據一第二態樣，本發明係關於一種包括一支撐件及一組件之裝置，該組件之一作用部分包括電連接至該裝置之連接接針之連接接針，此裝置之特徵在於其包括擱置在該支撐件上之一金屬罩，此罩覆蓋該組件及該裝置之該等連接接針。
本發明之此第二態樣旨在保護卡免受EMFA攻擊且並不旨在偵測此等攻擊。
金屬壁保護該組件之側。
本發明之此態樣極令人感興趣之處在於：其迫使攻擊者準備(舉例而言)藉由在壁中(通常在作用部分上方)挖一洞 而使該卡遭受一EMFA攻擊。
在一特定實施例中，此金屬罩包括包封組件及該裝置之連接接針之至少一個側壁、擱置在該支撐件上的此側壁之一邊緣、及形成該等側壁之一覆蓋物之一壁。
在一特定實施例中，該組件固定至該支撐件，該裝置之連接接針直接配置於該支撐件上。
在另一特定實施例中，該金屬罩構成一封閉外殼，該封閉外殼之一個外部壁固定至該支撐件，該組件及模組之連接接針固定至該外殼之內部。該外殼包括用於使連接導線通過之儘可能小之孔。
此實施例保護自身免受成功移除該支撐件之一攻擊者攻擊該組件。
在一特定實施例中，意欲連接至接地之作用部分之一連接接針連接至該罩，該罩自身連接至該裝置之一接地接針。
此實施例增強本發明之此第二態樣之安全性。
本發明亦規定一種包括根據本發明之第二態樣之免受一攻擊之保護構件及根據本發明之第一態樣之用於偵測及反擊之構件之裝置。
本發明之其他模式及優點將自沒有任何限制特性的本發明之特定實施例之說明顯現。
圖1圖解說明根據本發明之第一態樣之一裝置10。
此裝置10包括一支撐件12及一組件14，被動元件40配置 於支撐件12中能夠在存在一磁場或一電場之情況下產生電流。
此等被動元件40可包括能夠在存在一磁場之情況下產生電流之天線或能夠在存在一電場之情況下產生電流之金屬平面。
在此處所闡述之實施例中，該支撐件包括天線及金屬平面兩者以使得其可同時偵測一磁場及一電場。
圖2圖解說明根據本發明之第一態樣之另一裝置10。
在此實施例中，裝置10係一組件，被動元件40配置於該組件之一敷金屬層15b中。舉例而言，該組件係一積體電路且層15b係在製造期間藉由一個或若干個光微影步驟獲得之積體電路之一層。
在圖中，明顯地，包括被動元件之層15b放置於一保護層15a下方。
僅以實例之方式，此圖圖解說明構成一個(或多個)功能性敷金屬層之一層15c及一矽層18(半導體元件(電晶體、二極體...)位於其上在表面處)。
根據本發明之此第一態樣，裝置10包括在由被動元件產生之電流超過一預定臨限值時觸發一保護措施之構件。
圖3圖解說明其中一天線40連接至一熔絲55之一第一配置，熔絲55經放置與該天線串聯以使得由該天線發送之電流直接傳遞至熔絲中。
此熔絲經定尺寸以便在天線擷取源自組件自身之電磁放射或源自外部之電磁擾動時不熔融。
在該兩種情況下熔絲皆不必須熔融，此乃因由一磁場感應之電流具有小於CEM標準之振幅。
相反，熔絲55必須經定尺寸以在天線感測較強擾動(與一MFA攻擊同義)時熔融。針對該裝置設定之臨限值與熔絲之特性有關。
在圖3之實施例中，在正常模式中，亦即，當熔絲55未熔融時，天線40使電阻R2短路且僅源自該天線之電流之變化形式到達電阻R2。源自外部磁場或源自組件之電磁波之此等變化形式在電阻R2之端子處感應電壓，該等電壓弱得不足以超過電晶體M之臨限電壓以使得電阻R2之端子保持阻擋且不擾動在偵測到故障之情形中待附著之一SIG信號。
若由天線40發射大於該臨限值之電流，則考量到外場超過CEM特性及此係一MFA攻擊：正確地定尺寸之熔絲55熔融。
此起始非正常模式。電阻R1及R2形成一分壓器橋且發送至電晶體M之電壓等於VCC×R2/(R1+R2)。
R1必須經定尺寸以使得此分壓器橋輸出電壓大於電晶體M之臨限電壓。
由於電晶體M接通，因此其形成一閉合斷續器且SIG信號藉助於電晶體M附著至接地。
圖4闡述其中被動元件40係一金屬平面之一實施例。
在此實施例中，在正常模式中，亦即，當熔絲55未熔融時，平面40-熔絲55總成藉由對電晶體M之控制電壓施加零 U電壓而使電晶體NMOS M之柵極與源極短路。電晶體M保持阻擋且不作用於待附著之SiG信號。
若一電場施加至平面，則電容性耦合產生借用最小電阻路徑行進至接地且經由熔絲傳遞之一電場。若對應於一EFA攻擊之偵測之此電流過強，則熔絲55熔融。電壓U經由電阻R1拉至VCC電位。電晶體M接通且將信號SiG附著於0 V處。
圖5闡述可在積體電路中實施之另一保護性系統。
在此實施例中，反應系統並非基於一熔絲之大小而是基於一電壓位準。
此第二實施例較易於執行。
感測器40對應於一天線。其將其電流直接釋放至電阻R，電阻R根據歐姆定律將電流轉換成與由被動元件產生之電流成比例之U電壓。
電壓U施加至一電壓差動比較器60之正端子。
舉例而言，由一分壓器橋產生之臨限電壓TS施加至此比較器之負端子。
若電壓U不超過此臨限值，則比較器60之輸出保持等於「0」。比較器60之輸出直接連接至一非同步RS正反器之SET輸入且DET偵測停留於「0」處。
若電壓U超過該臨限值，則比較器60之輸出在整個過衝期間達到「1」。此足以將一「1」隱形邏輯放置於RS正反器之SET輸入上且因此將DET輸出阻擋於1狀態中；RS正反器非同步操作。
放置於「1」處之此位元可然後用於參與對組件之安全動作。
為確保在組件啟動時DET信號在0處且為避免無法預料之安全動作，每次重新初始化組件介面ISO7816(連接至RS正反器之RESET輸入)之RESET信號之添加迫使DET信號為0。
在圖6之實施例中，被動元件40係一金屬平面。如在圖5之情形中，退出金屬平面40之電流傳遞至電阻R且在比較器60之前強加U電壓。在一積體電路中實施此偵測方法係簡單的；藉助一分壓器橋調節偵測臨限值，執行此係尤其簡單的。
圖7A至圖7C圖解說明旨在保護組件10免受MFA攻擊的本發明之一第二態樣。
在此實施例中，裝置10包括一支撐件12及一組件14，組件14之一作用部分15包括電連接至裝置10之連接接針17之連接接針16。
此裝置10之出眾之處在於：其包括擱置在支撐件12上且覆蓋組件14及連接接針17之一金屬罩30。
在圖7A之模式中，金屬罩30包括封裝組件及模組之連接接針之四個側壁31、擱置在支撐件12上的此側壁之一邊緣及其形成一覆蓋物之一壁32。
當然，舉例而言，具有係為圓形剖面之一單個側壁31之實施例係可行的。
在圖7B之實施例中，且高度有利地，應連接至接地之一 連接接針16a直接連接至罩30，該罩自身連接至裝置之一接地接針17a。
在圖7C之實施例中，罩30係一封閉外殼。此外殼之一壁33固定至支撐件，組件14及模組之連接接針固定於外殼內部。
本發明亦規定組合其中一裝置能夠偵測攻擊且抵抗其的本發明之第一態樣與第二態樣之一實施例(如參考圖1至圖6所闡述)亦受諸如圖7A至圖7C中所展示之一外殼保護。
10‧‧‧裝置/組件
12‧‧‧支撐件
14‧‧‧組件
15‧‧‧作用部分
15a‧‧‧保護層
15b‧‧‧敷金屬層/層
15c‧‧‧層
16‧‧‧連接接針
16a‧‧‧連接接針
17‧‧‧連接接針
17a‧‧‧接地接針
18‧‧‧矽層
30‧‧‧金屬罩/罩
31‧‧‧側壁
32‧‧‧壁
33‧‧‧壁
40‧‧‧被動元件/天線/平面/感測器/金屬平面
50‧‧‧觸發構件
55‧‧‧熔絲
60‧‧‧電壓差動比較器/比較器
DET‧‧‧偵測/輸出/信號
M‧‧‧電晶體
R‧‧‧電阻
R1‧‧‧電阻
R2‧‧‧電阻
SiG‧‧‧信號/重要信號
TS‧‧‧臨限電壓
圖1及圖2圖解說明根據本發明之第一態樣之兩個裝置；圖3至圖6圖解說明用於觸發圖1及圖2之裝置之一保護措施之構件；及圖7A至圖7C圖解說明根據本發明之第二態樣之裝置。

Claims (10)

  1. 一種併有一裝置(10)之一微電路卡，該裝置包括：至少一個被動元件(40)，其能夠在存在一電場或一磁場之情況下產生一電流；及觸發構件(50)，其偵測到該電流之後且作為針對該微電路卡之一電磁故障攻擊的一結果而在該電流之強度超過一預定臨限值時觸發一保護措施，其中該保護措施由附著該裝置之一介面之一重要信號(SIG)組成，以當該保護措施被觸發時將該重要信號接地。
  2. 如請求項1之併有一裝置(10)之微電路卡，其中其包括該等被動元件之一網路。
  3. 如請求項2之併有一裝置(10)之微電路卡，其中該網路之該等被動元件以不同方式校準以偵測不同類型之電場或磁場。
  4. 如請求項1至3中任一項之併有一裝置(10)之微電路卡，其包括一支撐件(12)及一組件(14)，其中該至少一個被動元件(40)配置於該支撐件(12)中。
  5. 如請求項1至3中任一項之併有一裝置(10)之微電路卡，其由一組件(14)構成，其中該至少一個被動元件(40)配置於該組件之一作用部分之一層(15b)中。
  6. 如請求項5之併有一裝置(10)之微電路卡，其中該被動元件放置於位於該作用部分之一保護層(15a)下方之一層(15b)中。
  7. 如請求項1至3中任一項之併有一裝置(10)之微電路卡，其中該被動元件(40)係能夠在存在一磁場之情況下產生該電流之一天線。
  8. 如請求項1至3中任一項之併有一裝置(10)之微電路卡，其中該被動元件(40)係能夠在存在一電場之情況下產生該電流之一金屬平面。
  9. 如請求項1至3中任一項之併有一裝置(10)之微電路卡，其中一對策之該觸發構件(50)包括用於比較與該電流成比例之一第一電壓與一電壓臨限值之構件(60)。
  10. 如請求項1至3中任一項之併有一裝置(10)之微電路卡，其中一對策之該觸發構件(50)包括一熔絲(55)，該熔絲經放置與該被動元件(40)串聯且經定尺寸以在強度大於該臨限值之一電流通過其時熔融。
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FR3053503B1 (fr) * 2016-06-30 2019-03-29 Stmicroelectronics (Rousset) Sas Procede de protection d'un circuit integre, et circuit integre correspondant
CN107942154A (zh) * 2017-10-16 2018-04-20 北京中电华大电子设计有限责任公司 一种适用于芯片电磁攻击防护的保护结构和方法
FR3084521B1 (fr) * 2018-07-25 2020-08-14 Stmicroelectronics Rousset Procede de protection d'un module de circuit integre et dispositif correspondant
FR3084520B1 (fr) 2018-07-25 2020-08-14 Stmicroelectronics Rousset Procede de protection d'un circuit integre, et dispositif correspondant
FR3084492A1 (fr) 2018-07-30 2020-01-31 Stmicroelectronics (Rousset) Sas Procede de detection d'une attaque par un faisceau de particules electriquement chargees sur un circuit integre, et circuit integre correspondant
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FR3099259B1 (fr) 2019-07-24 2021-08-13 St Microelectronics Rousset Procédé de protection de données stockées dans une mémoire, et circuit intégré correspondant
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