TWI617229B - Manufacturing method of printed circuit board - Google Patents

Abstract

Provided is a method for manufacturing a printed circuit board, comprising: preparing a copper foil having a treated surface having an 8 ° diffuse reflectance SCI of 41% or less with respect to incident light, forming a photoresist pattern on the surface of the copper foil, and subjecting the copper foil to electrolysis. The copper plating layer peels off the photoresist pattern to form a wiring pattern, and performs a visual inspection of the appearance of the wiring pattern on the copper foil. According to the present invention, a method for manufacturing a printed circuit board can be provided. In the manufacture of the printed circuit board, before the formation of the laminated wiring layer, the appearance image inspection of the wiring pattern formed on the copper foil can be performed with high accuracy. This can significantly improve the productivity of printed circuit boards.

Description

Manufacturing method of printed circuit board

The present invention relates to a method for manufacturing a printed circuit board.

In recent years, in order to increase the mounting density of printed circuit boards and to reduce the size thereof, the multilayering of printed circuit boards has been increasingly performed. Such multilayer printed wiring boards are used in many portable electronic devices for the purpose of weight reduction and miniaturization. In addition, in this multilayer printed wiring board, it is required to further reduce the thickness of the interlayer insulating layer and further reduce the weight as a wiring board.

In terms of technology to meet such requirements, a method of forming a printed circuit board that is multilayered by directly forming a wiring layer on an ultra-thin metal layer has been proposed. In one aspect, a coreless buildup method is used. Production method. An example of a manufacturing method of a printed circuit board using a coreless lamination method using a copper foil with a carrier is shown in FIGS. 1 and 2. In the example shown in FIGS. 1 and 2, first, a copper foil 10 with a carrier having a carrier layer 12, a release layer 14 and a copper foil 16 in this order is laminated on a coreless support 18 such as a prepreg. Next, a photoresist pattern 20 is formed on the copper foil 16, and after the formation of a pattern plating layer (electrolytic copper plating layer) 22 and the peeling of the photoresist pattern 20, A wiring pattern 24 is formed. In addition, the pattern plating layer is subjected to a pre-lamination treatment such as a roughening treatment, and is used as the first wiring layer 26. Next, as shown in FIG. 2, in order to form a laminated layer 42, an insulating layer 28 and a copper foil 30 with a carrier (including a carrier layer 32, a peeling layer 34, and a copper foil 36) are laminated, the carrier layer 32 is peeled off, and a carbon dioxide mine is used. The copper foil 36 and the insulating layer 28 directly under it are laser-processed. Next, a second wiring layer 38 is formed by patterning by photoresist processing, electroless copper plating, electrolytic copper plating, photoresist peeling, and rapid etching, etc., and this patterning is repeated as appropriate until the nth wiring layer 40 (n Is an integer of 2 or more). Then, the coreless support 18 is peeled together with the carrier layer 12, and the copper foils 16 and 36 exposed between the wiring patterns are removed by flash etching to obtain a predetermined wiring pattern.

In addition, the printed circuit board on which the wiring pattern is formed is generally subjected to an appearance image inspection for confirming the correctness of the position and shape of the wiring pattern. The external image inspection is performed by: using an optical automatic appearance inspection (AOI) device to irradiate a predetermined light from a light source to obtain a binary image of a wiring pattern, and trying to match the binary image with a design data image Assess the agreement / disagreement between the two. In general, for an appearance image inspection, in the case shown in FIG. 2, the copper foils 16 and 36 exposed on the surface of the insulating layer 28 between the wiring patterns are removed by flash etching, and then the insulating layer is removed. 28 exposure to the surface between the wiring patterns. For example, Patent Document 1 (Japanese Patent Laid-Open Publication No. 2014-116533) discloses a method for manufacturing a coreless wiring board using a peelable metal foil, but a predetermined inspection such as an appearance inspection is performed by wiring the build-up section and the Reinforcement substrate is peeled off and will adhere to wiring buildup It is performed after removing the copper foil and exposing the dielectric layer (insulating resin layer) (final procedure).

[Prior technical literature] [Patent Literature]

[Patent Document 1] Japanese Patent Publication No. 2014-116533

However, as described above, the method of inspecting the appearance of the wiring pattern portion of the first wiring layer 26 formed on the surface of the insulating layer 28 after the manufacture of the printed circuit board (or the post-processing stage of the process) is performed even before In the stage after the first wiring layer 26 is formed on the surface of the copper foil 16 of the coreless support body of the program, there is a wafer having a defective portion in the wiring pattern of the first wiring layer 26, and the defective product cannot be determined at this stage. For this reason, the wafer yield of the first wiring layer 26 is obviously inferior, and the procedure that is followed is economically unfavorable, and the phenomenon still cannot be grasped, and the process proceeds to the superposition and stacking procedure. In this case, since the inspection is performed after the final procedure, there is a risk that a large number of defective wafers remain in the middle of the procedure. In addition, the above-mentioned method has the problem of delaying wasted production time of the inspection program, regardless of the presence or absence of defective portions in the wiring pattern of the first wiring layer 26, and requiring the entire wafer to perform a visual inspection procedure of the superimposed layer. For this reason, if the wiring pattern of the first wiring layer 26 can be formed on the surface of the copper foil 16 of the coreless support, the wiring pattern can be externally applied. A wafer having a defective wiring pattern can be identified by visual inspection, and the inspection procedure after the superposition and lamination procedure can be omitted and the inspection procedure can be simplified, which is suitable. However, after the printed circuit board is manufactured, the appearance image inspection system can use the conventional color tone contrast of the insulating layer (resin layer) and the wiring layer (copper layer), which can also use the color tone contrast caused by different materials to make a sharp appearance. Image inspection, so it has the advantage of high inspection accuracy. On the other hand, when the appearance image inspection is performed at an early stage immediately after the formation of the first wiring layer, it is necessary to detect the wiring pattern between the same materials such as the copper foil and the wiring layer (copper layer). Since the tone contrast is insufficient, there is a problem that inspection accuracy is greatly reduced.

The inventor has obtained the following discovery this time: In the manufacture of printed circuit boards, the use of copper foil with a treated surface with an SCI of 8 ° diffuse reflectance relative to incident light of 41% or less makes it possible to peel off the photoresist In such an early stage before the formation of the laminated wiring layer, a high-definition binarized image under high contrast is obtained, and the appearance image inspection of the wiring pattern formed on the copper foil is performed with high accuracy. In addition, it was also found that the defective products in the appearance image inspection can be eliminated at an early stage as described above, so that the productivity of the printed circuit board can be significantly improved.

Therefore, the object of the present invention is to obtain a high-definition binarized image with high-tone contrast at an early stage in the manufacture of a printed circuit board, such as after photoresist peeling and before formation of a laminated wiring layer. At the same time, the appearance image inspection of the wiring pattern formed on the copper foil is performed with high accuracy, thereby providing a printed circuit board manufacturing method that significantly improves the productivity of the printed circuit board.

According to one aspect of the present invention, there is provided a method for manufacturing a printed circuit board, comprising: a process of preparing a copper foil having a treated surface having an SCI of 8 ° diffuse reflectance relative to incident light of 41% or less; A process of forming a photoresist pattern on the aforementioned treated surface of the copper foil; a process of performing electrolytic copper plating on the aforementioned copper foil on which the aforementioned photoresist pattern is formed; a procedure of peeling the aforementioned photoresist pattern to form a wiring pattern; and forming the aforementioned wiring The pattern of the aforementioned copper foil is a procedure for inspecting the appearance image of the wiring pattern.

10‧‧‧ Copper foil with carrier

12‧‧‧ carrier layer

14‧‧‧ peeling layer

16‧‧‧ Copper foil

18‧‧‧ coreless support

20‧‧‧Photoresist pattern

22‧‧‧ pattern plating

24‧‧‧Wiring pattern

26‧‧‧First wiring layer

28‧‧‧ Insulation

30‧‧‧ copper foil with carrier

32‧‧‧ carrier layer

34‧‧‧ peeling layer

36‧‧‧ Copper foil

38‧‧‧ 2nd wiring layer

40‧‧‧nth wiring layer

42‧‧‧ Overlay wiring layer

44‧‧‧Multilayer wiring board

46‧‧‧Printed Circuit Board

50‧‧‧ ring light source

52‧‧‧Light receiving department

FIG. 1 is a diagram illustrating a first half of a procedure in an example of a method for manufacturing a printed circuit board using a coreless stacking method.

[FIG. 2] A procedure of the latter half of the procedure of FIG. 1 is illustrated for an example of a manufacturing method of a printed circuit board using a coreless stacking method.

FIG. 3 is a conceptual diagram showing a correlation between a measurement system used in an appearance image inspection and a cross-sectional configuration of a wiring pattern.

[Fig. 4] A diagram showing an example of the appearance image result when the recognition of the wiring pattern and the space is good and the cross-sectional configuration of the wiring pattern is attached.

[Fig. 5] An example of a design data image for pattern matching under appearance image inspection.

FIG. 6 is a diagram illustrating an example of a brightness histogram obtained at the time of initial setting of the appearance image inspection. The horizontal axis represents brightness (for example, a 256-level axis), and the vertical axis represents a cumulative amount.

FIG. 7 is a diagram illustrating an example of an appearance image result when the recognition of a wiring pattern and a space is difficult.

The present invention relates to a method for manufacturing a printed circuit board. The manufacturing of the printed circuit board according to the present invention is performed by preparing a copper foil having a predetermined treatment surface on one side, and performing a photoresist pattern formation, an electrolytic copper plating layer formation on the treatment surface, and The photoresist pattern is peeled off to form a wiring pattern. The copper foil forming the wiring pattern is subjected to an appearance image inspection of the wiring pattern. In addition, as for the copper foil used in this series of procedures, a copper foil having a treated surface having an 8 ° diffuse reflectance SCI of 41% or less with respect to incident light is used. Thereby, at such an early stage after the peeling of the photoresist and before the formation of the laminated wiring layer, a high-definition binarized image under high contrast can be obtained and the wiring pattern formed on the copper foil can be accurately performed at the same time. Appearance image check.

Thus, in the present invention, the 8 ° diffuse reflectance SCI is used as the evaluation index of the copper foil. This is based on the fact that in a visual inspection of the appearance of a glossy copper surface that is a wiring pattern, the light emission factor of diffuse reflection is effective with respect to a high 8 ° of the glossy copper surface. In addition, it was also found that in this appearance image inspection, a light source with a high reflection efficiency (high luminous factor) red LED compared to a glossy copper surface is used, and a light source having a peak region at 635 nm is particularly effective. That is, when the light source has a peak region at this wavelength, it is easy to recognize and display an image such as a defect or a short circuit of a fine wiring pattern of 3 μm or less. In order to make use of such characteristics, in order to obtain high contrast in image processing for wiring patterns in appearance image inspection, the surface of the copper foil is required to have less reflection with respect to the red semiconductor light than the first wiring layer constituting the wiring pattern. In this case, a copper foil having a wavelength of 635 nm and an 8 ° diffuse reflectance SCI of 41% or less with respect to incident light becomes very advantageous. In view of this, an example of the appearance image inspection will be described below. The external image inspection is as shown in FIG. 3 for example. The substrate on which the wiring pattern 24 is formed is irradiated with red semiconductor light (for example, light having a peak region at a wavelength of 635 nm) from the ring light source 50, and the light receiving unit 52 receives the light from the first light source 52. The reflected light of the wiring layer 26 and the reflected light from the copper foil 16 are determined into a gap portion (space) and a wiring portion (line) by comparing the obtained brightness data against a preset threshold value to form a binary value as illustrated in FIG. 4. The digitalized image is evaluated by correcting the position and shape of the wiring pattern 24 based on the pattern matching between the binary image and the image derived from the design data as shown in FIG. 5. The threshold used at this time can be determined as follows: In the initial setting, the entire surface of the substrate surface on which the wiring pattern 24 is formed (the surface on which the first wiring layer 26 is directly formed on the copper foil 16) is scanned in advance or specified. The luminance data obtained from the selected inspection sites are accumulated as shown in FIG. 6 to make a luminance histogram (the horizontal axis is brightness (for example, a 256-level axis) and the vertical axis is a cumulative amount). a gap portion between the peak peak) P _S is derived from the line (wiring portion) of the P _L, between the end of each peak (corresponding to the gap between the peak portion corresponding to the peak start point and a terminal portion of the wiring) of The median value. Therefore, as shown in FIG. 6, in the luminance histogram, the larger the distance D between the gaps (spaces) and the wirings (lines) between the peaks, the larger the high-definition binarized image at the higher contrast is obtained in the appearance image inspection. The result is more discriminative. The incident light on the processed surface of the copper foil 16 is preferably an 8 ° diffuse reflectance SCI of the wavelength of the light source used for the appearance image inspection with respect to the incident light having a wavelength in the peak region (preferably incident light having an upper wavelength of 635 nm) as Below 41%, the distance D between peaks in the above-mentioned brightness histogram increases significantly. As a result, it is possible to obtain a high-definition binarized image with high contrast and perform an appearance image inspection with high accuracy.

In this way, in the method according to the present invention, it is possible to obtain a high-definition binary image with high contrast at the same time with high accuracy at the early stage after the photoresist peeling and before the formation of the laminated wiring layer. Visual inspection of the appearance of wiring patterns on copper foil. As mentioned above, conventionally, the appearance image inspection is generally performed on a printed circuit board on which a wiring pattern is formed. However, even if the appearance image inspection is added after the printed circuit board is manufactured (or after the process stage of the process), A wafer having a defective portion in the wiring pattern of the first wiring layer 26 in the stage immediately after the first wiring layer 26 was formed on the surface of the copper foil 16 of the coreless support body following the previous procedure. Therefore, it is necessary to perform the appearance inspection procedure of the superimposed layer on the entire wafer, so that the delay time of the inspection procedure is wasted. For this reason, it is appropriate to perform an appearance image inspection at a stage earlier than that. However, the appearance of the printed circuit board can be used to check the contrast between the insulation layer (resin layer) and the wiring layer (copper layer). Contrast based on various materials can be used to carry out clear appearance image inspection, so it has the advantage of high inspection accuracy. On the other hand, when the appearance image inspection is performed at an earlier stage, the wiring pattern must be detected between the same materials such as copper foil and wiring layer (copper layer), and the contrast between the two materials is insufficient, so it can only be obtained. As shown in, for example, a binary image in which the wiring pattern is ambiguous as shown in FIG. 7, there is a problem that inspection accuracy is greatly reduced. In this case, in the aspect of the present invention, a copper foil having the above-mentioned specific diffuse reflectance SCI is used, so as to obtain a high-definition binarized image with high contrast, so related problems can be effectively avoided. As a result, defective products in the appearance image inspection can be eliminated at an early stage as described above, and thus the productivity of the printed circuit board can be significantly improved.

Hereinafter, aspects of the method of the present invention will be described with reference to the flowcharts shown in FIGS. 1 and 2. In addition, in the aspect shown in FIGS. 1 and 2, for the sake of simplicity, the laminated wiring layer 42 is formed by providing a copper foil 10 with a carrier on one side of the coreless support 18, but the coreless support 18 It is preferable to provide the copper foil 10 with a carrier on both sides and to form a laminated wiring layer 42 on both sides.

(a) Preparation of copper foil

As described above, the copper foil 16 has a surface having an 8 ° diffuse reflectance SCI of 41% or less with respect to incident light. Such a treated surface is generally provided on one side of the copper foil 16 (as in the case of the copper foil 10 with a carrier in FIG. 1, the opposite side of the release layer 14 (that is, the outermost surface of the copper foil 10 with a carrier)), But it can also be set on both sides. The incident light used for the evaluation of the 8 ° diffuse reflectance SCI has a wavelength in the peak region of the light source wavelength used for appearance image inspection. Is preferred. In addition, as described above, the appearance image inspection is preferably performed using a light source having a peak region at a wavelength of 635 nm. Therefore, the wavelength of incident light used for the evaluation of the 8 ° diffuse reflectance SCI is preferably 635 nm. The 8 ° diffuse reflectance SCI with respect to incident light (for example, incident light having a wavelength of 635 nm) is 41% or less, preferably 20% or less, and more preferably 15% or less. The 8 ° diffuse reflectance SCI with respect to incident light can be measured with a commercially available spectral colorimeter (for example, manufactured by Nippon Denshoku Industries Co., Ltd., SD7000) based on JIS Z8722 (2012). Such a treated surface with a low 8 ° diffuse reflectance SCI is preferably a surface that diffuses and reflects components of incident light (for example, incident light having a wavelength of 635 nm). In other words, a treated surface with a low 8 ° diffuse reflectance SCI is ideally realized because it has a surface with a small flat component region that diffusely reflects incident light (for example, incident light having a wavelength of 635 nm). In addition, in order to improve the accuracy in visual inspection of the appearance, the surface of the copper foil is preferably copper, or an alloy of copper and at least one selected from zinc, tin, cobalt, nickel, chromium, and molybdenum. The rough copper surface is preferable from the viewpoint of keeping the diffuse reflectance low.

The copper foil 16 has a structure other than the above-mentioned 8 ° diffuse reflectance SCI, and may have a well-known structure adopted for a copper foil with a carrier, and is not particularly limited. For example, the copper foil 16 may be formed by a wet film formation method such as an electroless plating method and an electrolytic plating method, a dry film formation method such as sputtering and chemical vapor deposition, or a combination thereof. In order to obtain the above-mentioned slightly granular surface, it is preferable to form it by electrolytic plating. The preferred thickness of the copper foil 16 is 0.05 μm to 7 μm, more preferably 0.075 μm to 5 μm, and more preferably Choose 0.09μm ~ 4μm.

It is more preferable that the copper foil 16 has a grain-like rough surface (that is, a rough surface made of irregularities composed of a plurality or a plurality of particles) on the treated surface. This makes it easy to make the 8 ° diffuse reflectance SCI of the incident light (preferably, incident light with an upper wavelength of 635 nm) be 41% or less while improving the adhesion with the photoresist pattern 20. The average particle diameter D of the roughened particle based image analysis is preferably 0.04 to 0.53 μm, more preferably 0.08 to 0.13 μm, and still more preferably 0.09 to 0.12 μm. Within the above-mentioned suitable range, the roughened surface can be provided with a moderate degree of roughness to ensure excellent adhesion to the photoresist, and at the same time, the openness of the unnecessary area of the photoresist can be well achieved during photoresist development. It can effectively prevent the line defect of the pattern plating layer 22 which may be difficult to be plated due to the photoresist that cannot be fully opened. Therefore, it can be said that it is excellent in photoresist developability and pattern plating property in the said suitable range, and is suitable for the fine formation of the wiring pattern 24. In addition, the average particle diameter D in the image analysis of the roughened particles is an image taken at a magnification of a predetermined number (for example, 1000 to 3000) of particles into one field of view of a scanning electron microscope (SEM), and the image is Commercially available image analysis software performs image processing and is preferably measured. For example, 200 particles arbitrarily selected can be used as the target, and the average diameter of these particles can be used as the average particle diameter D.

In addition, on the processed surface of the copper foil 16, the particle density ρ of the roughened particle image analysis is preferably 4 to 200 particles / μm ² , and more preferably 40 to 170 particles / μm ² and 70 to 100 particles / μm ^2. . In addition, although the roughened particles on the surface of the copper foil are dense and dense, the development residue of photoresist is easy to produce, but it is difficult to generate such development residue within the above-mentioned suitable range, so it is also excellent in the developability of the photoresist pattern 20. . Therefore, it can be said that it is suitable for the fine formation of the wiring pattern 24 when it is in the said suitable range. In addition, the particle density ρ under the image analysis of the roughened particles is an image taken at a magnification of a predetermined number (for example, 1000 to 3000) of particles into one field of view of a scanning electron microscope (SEM). A commercially available image analysis software performs image processing and is preferably measured. For example, in a field of view where 200 particles fall, a value obtained by dividing the number of particles (for example, 200) by the area of the field of view is used as the particle density ρ.

As another index for defining the characteristics of the roughened surface suitable for the fine formation of the wiring pattern 24 as described above, the specular gloss Gs (85 °) is exemplified. In this case, the specular gloss Gs (85 °) of the treated surface is preferably 20 to 100, more preferably 30 to 90, and still more preferably 40 to 80. The specular gloss Gs (85 °) under the image analysis of the roughened particles can be measured using a commercially available gloss meter based on JIS Z 8741-1997 (specular gloss-measurement method).

The surface of the copper foil may be formed with the above-mentioned roughened particles, and then subjected to a rust prevention treatment such as nickel-zinc / chromate treatment, a coupling treatment using a silane coupling agent, and the like. By such surface treatments, it is possible to improve the chemical stability of the surface of the copper foil, and to improve the adhesion when insulating layers are laminated.

The copper foil 16 is preferably provided in the form of a copper foil 10 with a carrier. In this case, it is preferable that the copper foil 10 with a carrier includes the carrier layer 12, the release layer 14, and the copper foil 16 in this order. In this case, the copper foil 16 may be in the form of an extremely thin copper foil.

The carrier layer 12 is a layer (in general, a foil) for supporting the copper foil 16 to improve its handleability. Examples of the carrier layer include aluminum foil, copper foil, stainless steel (SUS) foil, resin film, and metal-coated resin film. The copper foil is preferred. The copper foil may be either a rolled copper foil or an electrolytic copper foil. The thickness of the carrier layer is generally 250 μm or less, and preferably 12 μm to 200 μm.

The release layer 14 is a layer that weakens the peel strength of the carrier foil, guarantees the stability of the strength, and has a function of suppressing the interdiffusion that may occur between the carrier foil and the copper foil during press forming at high temperature. The release layer is generally formed on one side of the carrier foil, but may be formed on both sides. The release layer may be any one of an organic release layer and an inorganic release layer. Examples of the organic component used in the organic release layer include nitrogen-containing organic compounds, sulfur-containing organic compounds, and carboxylic acids. As examples of the nitrogen-containing organic compound, triazole compounds, imidazole compounds, and the like are exemplified. Among them, triazole compounds are particularly preferable because they are easily stable in peelability. In the case of triazole compounds, 1,2,3-benzotriazole, Carboxybenzotriazole, N ', N'-bis (benzotriazolylmethyl) urea, 1H- 1,2,4-triazole and 3-amino-1H-1,2,4-triazole. Examples of sulfur-containing organic compounds include hydrogenthiobenzothiazole, trimeric thiocyanic acid, 2-benzimidazolethiol, and the like. Examples of the carboxylic acid include monocarboxylic acid and dicarboxylic acid. On the other hand, examples of the inorganic component used in the inorganic release layer include Ni, Mo, Co, Cr, Fe, Ti, W, P, Zn, and a chromate-treated film. In addition, the release layer can be formed by bringing the release layer component-containing solution into contact with at least one surface of the carrier foil to release it. The layer component is adsorbed on the surface of the carrier foil or the like in the solution. When the carrier foil is brought into contact with the release layer component-containing solution, this contact can be carried out by immersion of the release layer component-containing solution, spraying of the release layer component-containing solution, dripping of the release layer component-containing solution, or the like. In addition, a method of forming a release layer component as a coating film by a vapor phase method using vapor deposition, sputtering, or the like can also be adopted. The fixation of the release layer component to the surface of the carrier foil can be performed by drying the release layer component-containing solution, electrodeposition of the release layer component in the release layer component-containing solution, or the like. The thickness of the release layer is generally 1 nm to 1 μm, and preferably 5 nm to 500 nm. The peel strength of the release layer 14 and the carrier foil is preferably 7 gf / cm to 50 gf / cm, more preferably 10 gf / cm to 40 gf / cm, and still more preferably 15 gf / cm to 30 gf / cm.

Other functional layers may be provided between the release layer 14 and the carrier layer 12 and / or the copper foil 16 as desired. Examples of such other functional layers include auxiliary metal layers. The auxiliary metal layer is preferably made of nickel and / or cobalt. Forming such an auxiliary metal layer on the surface side of the carrier layer 12 and / or the surface side of the copper foil 16 makes it possible to suppress mutual interaction that may occur between the carrier layer 12 and the copper foil 16 during high-temperature or long-term hot-press molding. Diffusion guarantees the stability of the peel strength of the carrier layer. The thickness of the auxiliary metal layer is preferably 0.001 to 3 μm.

(b) Formation of laminated body

As desired, as the procedure (b), the copper foil 16 or the copper foil 10 with a carrier is laminated on the coreless support 18 before the photoresist pattern is formed. Laminates are formed on one or both sides. This lamination can be performed according to well-known conditions and methods used for lamination of copper foil and prepreg in a general printed circuit board manufacturing process. The coreless support 18 is generally made of a resin, preferably an insulating resin. The coreless support 18 is preferably a prepreg and / or a resin sheet, and more preferably a prepreg. The prepreg is a general term for a composite material in which a synthetic resin is impregnated or laminated on a base material such as a synthetic resin plate, a glass plate, a glass woven fabric, a glass non-woven fabric, or paper. Preferred examples of the insulating resin impregnated in the prepreg include epoxy resin, cyanate resin, bismaleimide triazine resin (BT resin), polyphenylene ether resin, and phenol resin. Examples of the insulating resin constituting the resin sheet include insulating resins such as epoxy resin, polyimide resin, and polyester resin. In addition, the coreless support 18 may contain filler particles made of various inorganic particles such as silica and alumina from the viewpoint of reducing the coefficient of thermal expansion, improving rigidity, and the like. Although the thickness of the coreless support 18 is not particularly limited, 3 to 1000 μm is preferable, 5 to 400 μm is more preferable, and 10 to 200 μm is more preferable.

(c) Forming a photoresist pattern

In this procedure (c), a photoresist pattern 20 is formed on the surface of the copper foil 16. The formation of the photoresist pattern 20 can be performed in either of a negative photoresist and a positive photoresist, and the photoresist can be any of a film type and a liquid type. In addition, the developer may be a developer such as sodium carbonate, sodium hydroxide, or an amine aqueous solution, and may be performed in accordance with various methods and conditions generally used in the manufacture of printed circuit boards without particular limitation.

(d) Electrolytic copper plating

In this procedure (d), the electrolytic copper plating layer 22 is applied to the copper foil 16 on which the photoresist pattern 20 is formed. The formation of the electrolytic copper plating layer 22 may be performed according to various pattern plating methods and conditions generally used in the manufacture of printed circuit boards such as copper sulfate plating solution and copper pyrophosphate plating solution, without particular limitation.

(e) Peeling off the photoresist pattern

In this procedure (e), the photoresist pattern 20 is peeled to form a wiring pattern 24. The peeling of the photoresist pattern 20 is performed using a sodium hydroxide aqueous solution, an amine solution or an aqueous solution thereof, and can be performed without particular limitation depending on various peeling methods and conditions generally used in the manufacture of printed circuit boards. In this way, the wiring pattern 24 in which the wiring portions (lines) formed by the first wiring layer 26 are directly formed on the surface of the copper foil 16 is arranged with the gap portions (spaces) interposed therebetween. For example, for the miniaturization of circuits, the line / space (L / S) is formed to such a degree that it is highly refined to less than 13 μm / 13 μm (for example, 12 μm / 12 μm, 10 μm / 10 μm, 5 μm / 5 μm, 2 μm / 2 μm). The wiring pattern is preferable. For such a fine circuit, the appearance image inspection can be performed with high accuracy in the following procedure (f) according to the method of the present invention.

(f) Appearance image inspection

In this procedure (f), the copper foil 16 on which the wiring pattern 24 is formed is applied. An external image inspection of the wiring pattern 24 is performed. Based on the appearance image inspection, the correctness of the position and shape of the wiring pattern can be confirmed, and a laminated body having the wiring pattern 24 having the desired accuracy can be selected. The appearance image inspection is preferably performed by an optical automatic appearance inspection (AOI). The appearance image inspection is as described above with reference to FIG. 3 and the like, but the appearance image inspection is preferably performed using a light source having a peak region at a wavelength of 635 nm. The reason is that at this wavelength, there is an advantage that an image showing defects such as a wiring pattern and a short circuit can be easily recognized. In particular, the surface of the copper plating layer of the first wiring layer 26 constituting the wiring pattern 24 formed directly on the copper foil 16 has a characteristic that it easily reflects red semiconductor light. For this reason, in order to obtain high contrast in the appearance image inspection, the surface of the copper foil 16 is required to have less reflection with respect to the red semiconductor light than the first wiring layer 26. In this regard, the copper foil 16 having an 8 ° diffuse reflectance SCI of 41% or less with respect to incident light (preferably incident light with an upper wavelength of 635 nm) is very advantageous as described above.

The external image inspection is as shown generally in FIG. 3, for example, the substrate on which the wiring pattern 24 is formed is irradiated with red semiconductor light (for example, light having a wavelength of 635 nm) from the ring light source 50, and the light receiving unit 52 receives the light from the first wiring layer 26. The reflected light from the copper foil 16 and the reflected light from the copper foil 16 are discriminated into a gap portion (space) and a wiring portion (line) by comparing the obtained brightness data against a preset threshold to form a binary image as illustrated in FIG. 4. Based on the pattern matching between the binarized image and the image derived from the design data as shown in FIG. 5, the correctness of the position and shape of the wiring pattern 24 is evaluated. In addition, the threshold used at this time may be determined as follows: In the initial setting, the entire surface of the substrate surface on which the wiring pattern 24 is formed (the surface on which the first wiring layer 26 is directly formed on the copper foil 16) is scanned in advance or in advance. The brightness data obtained from the set lot-checking positions are integrated to generate a brightness histogram as shown in FIG. 6 (the horizontal axis is brightness (for example, a 256-level axis) and the vertical axis is a cumulative amount). peak between peak (gap portion) is derived from the line P _S (wiring portion) of the P _L, (the peak corresponding to the gap portion between the terminal and the peak corresponding to the starting point of the wiring portion) between the end of the respective peak The median value. As a result of the related appearance image inspection, a multilayer body that does not meet the desired standard is excluded, and a multilayer body having the wiring pattern 24 having the desired accuracy may be selected and attached to any subsequent procedure as appropriate.

(g) Formation of laminated wiring layers

As desired, as the procedure (g), it is preferable to form a laminated wiring layer 42 on the copper foil 16 after the appearance image inspection to produce a laminated wiring body with a laminated wiring. For example, in addition to the first wiring layer 26 already formed on the copper foil 16, an insulating layer 28 and a second wiring layer 38 may be sequentially formed to form a laminated wiring layer 42. The method of forming the superposition layer after the second wiring layer 34 is not particularly limited, and a subtraction method, an MSAP (improved semi-additive processing) method, an SAP (semi-additive) method, a full-additive method, and the like can be used. For example, when a resin layer and a metal foil typified by a copper foil are simultaneously pressed and bonded, the formation of a via hole, a panel plating layer, and other interlayer conduction means can be combined to etch and process the panel plating layer and the metal. Foil to form a wiring pattern. In addition, only the resin is bonded to the surface of the copper foil 16 by stamping or layer processing. In the case of a layer, a wiring pattern can be formed on the surface by a semi-additive method.

The above procedure is repeated as appropriate to obtain a laminated wiring body with superimposed wiring. In this procedure, a superimposed wiring layer in which a resin layer and a wiring layer including a wiring pattern are arranged in an interactive build-up layer is formed, and a superimposed wiring layer laminated body formed to an n-th wiring layer 40 (n is an integer of 2 or more) is Preferred. This procedure is repeated until a desired number of layers of stacked wiring layers are formed. At this stage, bumps for mounting such as solder resist layers, pillars, etc. may be formed on the outer layer as appropriate. In addition, the outermost layer of the laminated wiring layer can be used to form an outer layer wiring pattern in a subsequent processing procedure (i) of the multilayer wiring board.

(h) Separation of laminates with laminated wiring

As desired, as the procedure (h), it is preferable to obtain the multilayer wiring board 44 including the laminated wiring layer 42 by separating the laminated wiring-attached laminate with the release layer 14. This separation can be performed by peeling off the copper foil 16 and / or the carrier layer 12.

(i) Processing of multilayer wiring boards

As desired, as the program (i), it is preferable to obtain the printed circuit board 46 by processing the multilayer wiring board 44. In this procedure, the multilayer wiring board 44 obtained by the above-mentioned separation procedure is used to process a desired multilayer printed circuit board. The processing method from the multilayer wiring board 44 to the multilayer printed wiring board 46 may be any of various known methods. For example, the copper foil 16 on the outer layer of the multilayer wiring board 44 is etched to form outer-layer circuit wiring, and a multilayer printed circuit board can be obtained. In addition, copper on the outer layer of the multilayer wiring board 44 may be used. The foil 16 is completely removed by etching, and is used as a multilayer printed wiring board 46 while maintaining this state. Furthermore, the copper foil 16 on the outer layer of the multilayer wiring board 44 can be completely etched away, and the surface of the exposed resin layer can be formed into a circuit shape with a conductive paste or a semi-additive method to directly form an outer layer circuit to form a multilayer A printed circuit board. Furthermore, the copper foil 16 on the outer layer of the multilayer wiring board 44 may be completely etched away and the first wiring layer 26 may be soft-etched to obtain a first wiring layer 26 having a recessed portion, and this may be used as a mounting pad. .

[Example]

The present invention will be further specifically described with reference to the following examples. In addition, the examples shown below are examples of the advantages that the copper foil with a predetermined treated surface has advantages such as appearance image inspection and fine circuit formation in the manufacturing process of printed circuit boards.

example 1

(1) Manufacture of electrolytic copper foil for carrier

For the copper electrolytic solution, a sulfuric acidic copper sulfate solution having the composition shown below was used, a cathode was used with a rotating electrode drum made of titanium having a surface roughness Ra of 0.20 μm, and a DSA (dimensional stability anode) was used for the anode. Electrolysis was performed at a temperature of 45 ° C. and a current density of 55 A / dm ² to obtain an electrolytic copper foil A (hereinafter referred to as copper foil A) for a carrier having a thickness of 12 μm.

(※ Here, with respect to the formed copper foil A, the side to be processed in the procedure described later is referred to as the "drum surface side" and the side connected to the electrolyte is referred to as the "drum surface side" during electrolysis. "Electrolyte side".)

(2) Formation of organic release layer

The drumhead side of the copper foil A that had been pickled was subjected to a CBTA aqueous solution containing 1,000 weight ppm of CBTA (Carboxybenzotriazole), a free sulfuric acid concentration of 150 g / L, and a copper concentration of 10 g / L. It was lifted by immersing at 30 ° C for 30 seconds. In this way, the CBTA component was adsorbed on the drum side of the copper foil A, and the CBTA layer was formed as an organic peeling layer.

(3) Formation of extremely thin copper foil

An extremely thin copper foil having a thickness of 3 μm was formed on the drum surface side of the copper foil A forming the organic release layer in an acidic copper sulfate solution at a current density of 8 A / dm ² on the organic release layer.

(4) Roughening

The ultra-thin copper foil formed on the drum side of the electrolytic copper foil A for a carrier was roughened by the following three-stage procedure.

-The first stage of the roughening treatment is a copper electrolytic solution for roughening treatment (copper concentration: 11g / L; free sulfuric acid concentration: 220g / L; 9-phenylacridine concentration: 0mg / L; chlorine concentration: 0mg / L; solution temperature: 25 ° C) for electrolysis (current density: 10A / dm ² ) and washing with water.

-The second stage of the roughening treatment is a copper electrolytic solution for roughening treatment (copper concentration: 65 g / L; free sulfuric acid concentration: 150 g / L; 9-phenyl acridine concentration: 0 mg / L; chlorine concentration: 0 mg / L; solution temperature: 45 ° C) for electrolysis (current density: 15A / dm ² ) and washing with water.

-The third stage of roughening treatment is a copper electrolytic solution for roughening treatment (copper concentration: 13g / L; free sulfuric acid concentration: 50g / L; 9-phenyl acridine concentration: 140mg / L; chlorine concentration: 35mg / l; solution temperature: 30 ° C) for electrolysis (current density: 50A / dm ² ) and washing with water.

(5) Anti-rust treatment

Both surfaces of the electrolytic copper foil after the roughening treatment are subjected to rust prevention treatment by inorganic rust prevention treatment and chromate treatment. First, in terms of inorganic antirust treatment, a pyrophosphate bath was used at a potassium pyrophosphate concentration of 80 g / L, a zinc concentration of 0.2 g / L, a nickel concentration of 2 g / L, a liquid temperature of 40 ° C, and a current density of 0.5 A / dm ² . Anti-rust treatment of zinc-nickel alloy. Next, in the chromate treatment, a chromate layer is further formed on the zinc-nickel alloy antirust treatment. This chromate treatment was performed at a chromic acid concentration of 1 g / L, a pH of 11, a solution temperature of 25 ° C, and a current density of 1 A / dm ² .

(6) Silane coupling agent treatment

The copper foil subjected to the rust prevention treatment is washed with water, and then directly treated with a silane coupling agent, so that the silane coupling agent is adsorbed on the rust prevention treatment layer on the roughened surface. This silane coupling agent is treated with pure water as a solvent and a solution of 3-aminopropyltriethoxysilane with a concentration of 3 g / L. This solution is spray-blown onto the black roughened surface for adsorption treatment. . After the silane coupling agent is adsorbed, the water is finally dispersed by an electric heater to obtain a surface-treated copper foil with a carrier.

Examples 2 ~ 4 and 6

Instead of the roughening treatment of the three-stage procedure described above, except that the roughening treatment of the two-stage procedure was performed under the conditions shown in Table 1, the same procedure as in Example 1 was performed to produce a copper foil with a surface treatment of a carrier.

Example 5

On the electrolytic solution side of the copper foil A, an organic peeling layer and an extremely thin copper foil having a thickness of 3 μm were formed in the same procedure as in Example 1. Next, the surface of the ultra-thin copper foil was roughened using a copper electrolytic solution for roughening having the composition shown below under conditions of a solution temperature of 30 ° C. and a current density of 50 A / dm ² to perform roughening.

<Composition of copper electrolytic solution for roughening>

-Copper concentration: 15g / L

-Free sulfuric acid concentration: 55g / L

-9-phenylacridine concentration: 140mg / L

-Chlorine concentration: 35mg / L

-Bis (3-sulfopropyl) disulfide concentration: 100ppm

In this way, the treated surface roughened with black was subjected to rust prevention treatment and silane coupling treatment in the same procedure as in Example 1 to produce a surface-treated copper foil with a carrier.

Example 7 (comparative)

Except that no roughening treatment was performed, it was made in the same manner as in Production Example 5. A surface-treated copper foil with a carrier was formed on the electrolytic solution side of copper foil A to form an extremely thin copper foil.

Evaluation of surface characteristics of surface-treated copper foil

The following evaluations were performed on the treated surface (the precipitation surface side of the electrolytic copper foil) of the surface-treated copper foil produced in Examples 1 to 7. The evaluation results are shown in Table 2.

<Optical characteristics>

(8 ° diffuse reflectance SCI at 635nm)

Regarding the treated surface of the surface-treated copper foil, JIS Z 8722 (2012) was used for a 8 ° diffuse reflectance SCI with respect to incident light having a wavelength of 635 nm using a spectral colorimeter (manufactured by Nippon Denshoku Industries, Ltd., SD7000) (Measurement method of color-color of reflected and transmitted objects).

<Roughened surface characteristics>

(Average particle diameter D and particle density ρ)

The inclination angle was made 0 ° with respect to the surface of the surface-treated copper foil, and an image was taken at a magnification of 1000 to 3000 particles falling into one field of view of a scanning electron microscope (SEM). Density ρ and average particle diameter D. For image processing, image analysis software (Mac-VIEW, manufactured by Mountek) was used. The measurement is performed with 200 particles arbitrarily selected as an object, the average diameter of the particles is "average particle diameter D", and the value of the number of particles (that is, 200) divided by the visual field area is "particle density ρ".

(Gloss Gs (85 °))

A gloss meter (manufactured by Nippon Denshoku Industries Co., Ltd., PG-1M) was used for the treated surface of the surface-treated copper foil, and an angle of 85 ° was measured based on JIS Z 8741 (1997) (mirror gloss-measurement method). Gloss.

Evaluation of the manufacturability of coreless support wiring layers

Using the surface-treated copper foils prepared in Examples 1 to 7, sequential lamination to a coreless support, photoresist processing, pattern plating, and photoresist peeling were sequentially performed to produce a predetermined wiring pattern for the first wiring layer. A laminated body formed on a surface-treated copper foil. Specifically, it is prepared as follows.

(1) Lamination to coreless laminated body

Four prepregs (made by Mitsubishi Gas Chemical Co., Ltd., GHPL-830NS, thickness: 45 μm) made of glass cloth and bismaleimide triazine resin were stacked to form a coreless support. On both sides of the coreless support, the copper foil with a carrier manufactured in Examples 1 to 7 was used as the outer side of the ultra-thin copper foil as a laminate to produce a coreless laminate. This stamping and lamination was performed under the following conditions: stamping temperature: 220 ° C; stamping time: 90 minutes; pressure: 40MPa.

(2) Fabrication of fine wiring pattern samples

For the evaluation of the photoresistive adhesiveness, a sample in a state where a cylindrical pattern was prepared with a photoresist having a diameter of 7 μm (a pitch of 14 μm) which had been subjected to the above-mentioned development procedure was prepared. In addition, for appearance image inspection For characteristics evaluation and evaluation of wiring pattern formability, a sample including a wiring pattern having a line / space (L / S) of 8 μm / 8 μm and 7 μm / 7 μm which had been subjected to the above-mentioned photoresist peeling procedure was prepared. The specific procedures of photoresist coating, electrolytic copper plating, and photoresist peeling are as follows.

(Photoresist coating)

A negative photoresist (RY3625, manufactured by Hitachi Chemical Industries, Ltd.) was laminated on the ultra-thin copper foil layer, and exposed (20 mJ / cm ² ) and developed (8% sodium carbonate aqueous solution, 30 ° C spray method).

(Electrolytic copper plating)

On the ultra-thin copper foil layer patterned by the development process, an electrolytic copper plating layer was formed by a copper sulfate plating solution to a thickness of 10 μm.

(Peeling of photoresist)

Using a photoresist peeling solution (R-100S, manufactured by Mitsubishi Gas Chemical Co., Ltd.), the photoresist was peeled off at 60 ° C. for 5 minutes.

The photoresist adhesion and photoresist resolution during the formation of the circuit, and the final appearance inspection characteristics of the laminated body with the first wiring layer, were evaluated as follows. The results are shown in Table 2.

<Appearance image inspection characteristics>

(Distance between peaks of 256 levels)

An optical automatic inspection (AOI) device (made by Dainippon Screen Manufacturing Co., Ltd., product name: PI9500) equipped with a 635 nm red LED for the light source is prepared. The brightness histogram as shown in FIG. 6 was prepared by scanning the surface of the laminated body to which the wiring pattern was applied, and the rise of the peak P _S in the space (gap portion) of the 256-level axis as shown in FIG. 6 was measured. The position, the distance of the rising position on the low-level side of the peak _PL of the line (wiring portion) (that is, the distance D between the 256-level peaks). The obtained values are shown in Table 2.

(Identifiable)

The visibility of the wiring pattern was evaluated in the following order. The brightness histogram as shown in FIG. 6 is prepared by scanning the surface of the laminated body to which the wiring pattern is applied, and a threshold value for recognizable space and wiring is set. This threshold value, as based: peak between peak luminance histogram from the space (gap portion) is derived from the line P _S (wiring portion) of the P _L, between the end of each peak (corresponding to the gap portion Between the terminal of the peak value of the and the start point of the peak corresponding to the wiring portion). Based on this threshold, the circuit surface on which the wiring pattern is formed is scanned to identify the line and space, and the pattern is matched with the design data. The classification is evaluated according to the following four-stage benchmark.

-AA: as shown in Figure 4 if the design is very accurate to obtain line / space images (hereinafter, L / S images)

-A: The person who obtained the L / S image roughly correctly,

-B: Tolerable L / S image

-C: as shown in Figure 7

The image (A evaluation) obtained in Example 2 is shown in Figure 4 for reference.

The evaluation results are shown in Table 2. According to the comparison of the distance between the peaks of 256 levels shown in Table 2 and the discriminant evaluation results, it can be known that the longer the distance between the peaks of 256 levels, the better the visibility of the wiring pattern, which is more suitable for confirming the position and Appearance image check for correctness of shape. In addition, when the relationship between the discretion and the 256-level peak distance shown in Table 2 is considered, the 256-level peak distance is preferably 85 or more, more preferably 100 or more, and still more preferably 110 or more.

<Circuit formation characteristics>

(Evaluation of wiring pattern formability)

The wiring pattern formability evaluation was performed as follows. For a wiring pattern including 20 (length 10 mm) lines formed by various lines / spaces (L / S), each of the wiring patterns having a line / space (L / S) of 8 μm / 8 μm and 7 μm / 7 μm Based on the viewpoint that there is no developing residue and whether the electrolytic copper plating layer is formed into a pattern, the evaluation was performed in the following three stages.

-A: No defective electrical plating

-B: There are 2 or less defective portions of the electroplating in the 20 wires

-C: There are 3 or more defective electrical coatings in 20 wires

In addition, for the comprehensive evaluation based on the evaluation results of the above four types of L / S, a hierarchical evaluation was performed according to the following four-stage benchmark.

-AA: Very good

-A: Good

-B: Allowable

-C: bad

(Photoresistive Adhesiveness / Peelability)

The evaluation of the adhesiveness / peelability of the photoresist is based on the frequency of occurrence of photoresistive adhesion failure (photoresistance discontinuity) or defective photoresist residue between the patterns caused by the development of the above-mentioned cylindrical pattern 200 of the photoresist. The occurrence of the disease is evaluated in accordance with the following three-stage benchmark.

-A: less than 10 places

-B: 10 or more defects and less than 50

-C: more defects than 50

-D: Photoresist residue is generated between the patterns, and no independent cylindrical pattern is formed

10‧‧‧ Copper foil with carrier

16‧‧‧ Copper foil

18‧‧‧ coreless support

24‧‧‧Wiring pattern

26‧‧‧First wiring layer

Claims (14)

A method for manufacturing a printed circuit board, comprising: a process of preparing a copper foil having a treated surface having an SCI with an 8 ° diffuse reflectance relative to incident light of 41% or less; and forming a photoresist pattern on the treated surface of the copper foil A procedure of performing electrolytic copper plating on the copper foil on which the aforementioned photoresist pattern is formed; a procedure of peeling off the aforementioned photoresist pattern to form a wiring pattern; and performing a wiring pattern on the aforementioned copper foil on which the wiring pattern is formed Procedure for appearance image inspection; wherein the copper foil has a thickness of 0.05 to 7 μm. The method of claim 1, wherein the incident light has a wavelength within a peak region of a light source wavelength used for the appearance image inspection. For example, the method of claim 1, wherein the appearance image inspection is performed using a light source having a peak region at a wavelength of 635 nm. For example, the method of claim 1, wherein the wavelength of the incident light is 635 nm. For example, the method of claim 1 in the patent scope, wherein the aforementioned 8 ° diffuse reflectance SCI is 20% or less. The method according to item 1 of the patent application range, wherein a rough surface having a particle shape is formed on the treated surface. For example, the method of claim 6 in the patent application range, wherein the average particle diameter D of the roughened particles under image analysis is 0.04 to 0.53 μm, and the particle density ρ of the roughened particles under image analysis is 4 to 200 particles / μm. ² . For example, the method of claim 1 in the patent scope, wherein the specular gloss Gs (85 °) of the aforementioned treated surface is 20 to 100. For example, the method of claim 1 in the patent application scope, wherein the appearance image inspection is performed by an optical automatic appearance inspection (AOI). For example, the method of claim 1 in which the aforementioned copper foil is provided in the form of a copper foil with a carrier, and the copper foil with a carrier is sequentially provided with a carrier layer, a release layer, and the aforementioned copper foil. For example, the method of claiming a patent scope item 1 further includes: before forming the photoresist pattern, laminating the copper foil or the copper foil with a carrier on one or both sides of the coreless support to form a laminate. For example, the method of claiming a patent scope item 1 further includes a procedure of forming a laminated wiring layer on the aforementioned copper foil after the appearance image inspection, and manufacturing a laminated body with laminated wiring. For example, the method of claim 12 in the patent application scope further includes: a process of separating the aforementioned laminated wiring layer-attached laminated body with the aforementioned peeling layer to obtain a multilayer wiring board including the aforementioned laminated wiring layer. For example, the method of claiming the scope of patent application No. 1 further includes a process of obtaining the printed circuit board by processing the aforementioned steel foil or the aforementioned multilayer wiring board.