TWI608615B - Semiconductor devices including a stressor in a recess and methods of forming the same - Google Patents
Semiconductor devices including a stressor in a recess and methods of forming the same Download PDFInfo
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- TWI608615B TWI608615B TW102133206A TW102133206A TWI608615B TW I608615 B TWI608615 B TW I608615B TW 102133206 A TW102133206 A TW 102133206A TW 102133206 A TW102133206 A TW 102133206A TW I608615 B TWI608615 B TW I608615B
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- Prior art keywords
- forming
- ldd
- active region
- gate electrode
- trench
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 24
- 229910052796 boron Inorganic materials 0.000 claims description 24
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 23
- 229910052698 phosphorus Inorganic materials 0.000 claims description 21
- 239000011574 phosphorus Substances 0.000 claims description 20
- 239000013078 crystal Substances 0.000 claims description 17
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 13
- 229910052732 germanium Inorganic materials 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 12
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- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 5
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- 239000011229 interlayer Substances 0.000 description 17
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 16
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- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 12
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- 238000001312 dry etching Methods 0.000 description 4
- 229910052735 hafnium Inorganic materials 0.000 description 4
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 4
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- 229910052751 metal Inorganic materials 0.000 description 4
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
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- 239000010409 thin film Substances 0.000 description 3
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- NDKBVBUGCNGSJJ-UHFFFAOYSA-M benzyltrimethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)CC1=CC=CC=C1 NDKBVBUGCNGSJJ-UHFFFAOYSA-M 0.000 description 2
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- 229910001507 metal halide Inorganic materials 0.000 description 2
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- 229910052707 ruthenium Inorganic materials 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910010041 TiAlC Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
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- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Description
本發明係大致有關於電子裝置之領域,且特別有關於半導體裝置。 The present invention relates generally to the field of electronic devices, and more particularly to semiconductor devices.
為改善半導體裝置之電氣特性,已發展出各種應變技術。 Various strain techniques have been developed to improve the electrical characteristics of semiconductor devices.
一種形成一半導體裝置之方法可包括在一基材之一作用區域中形成一輕摻雜汲極(LDD)及在該LDD中形成一包括磷之快速蝕刻區域。該方法亦可包括藉由使該快速蝕刻區域凹陷在該作用區域中形成一第一槽及藉由使用一方向性蝕刻程序擴大該第一槽在該作用區域中形成一第二槽。該第二槽可包括該作用區域之一缺口部份。該方法可更包括在該第二槽中形成一應力件及在該作用區域上形成一閘極電極。在各種實施例中,該LDD可包括硼。 A method of forming a semiconductor device can include forming a lightly doped drain (LDD) in an active region of a substrate and forming a rapidly etched region comprising phosphorous in the LDD. The method can also include forming a first trench in the active region by recessing the fast etch region and expanding the first trench to form a second trench in the active region by using a directional etch process. The second groove may include a notched portion of the active area. The method may further include forming a stressor in the second trench and forming a gate electrode on the active region. In various embodiments, the LDD can include boron.
依據各種實施例,形成該第一槽可包括實施一等向蝕刻程序。該第一槽可包括藉由使該快速蝕刻區域凹陷所形成之一上槽及與該上槽之一下部連接的一下槽。該下槽可具有比該上槽之一第二寬度窄之一第一寬度。在各種實施例中,形成該第一槽可更包括在實施該等向蝕刻程序之前實施一異向蝕刻程序。 According to various embodiments, forming the first trench may include performing an isotropic etch process. The first groove may include an upper groove formed by recessing the rapid etched region and a lower groove connected to a lower portion of the upper groove. The lower slot may have a first width that is narrower than a second width of one of the upper slots. In various embodiments, forming the first trench can further include performing an anisotropic etch process prior to performing the isotropic etch process.
依據各種實施例,該作用區域之缺口部份可包括一上側壁及一接觸該上側壁之下側壁。在該作用區域之一最上方表面與該上側壁之間的一角度可為一銳角且該上側壁可與該下側壁不共平面。在各種實施例中,該上側壁可在該LDD之一表面上之一會合界面接觸該下側壁。該閘極電極可重疊該等上與下側壁之會合界面且該上側壁之一邊緣部份可突出超過該閘極電極之一相鄰側壁。 According to various embodiments, the notched portion of the active area may include an upper sidewall and a lower sidewall contacting the upper sidewall. An angle between the uppermost surface of one of the active regions and the upper sidewall may be an acute angle and the upper sidewall may be non-coplanar with the lower sidewall. In various embodiments, the upper sidewall may contact the lower sidewall at a meeting interface on one of the surfaces of the LDD. The gate electrode may overlap the meeting interface of the upper and lower sidewalls and an edge portion of the upper sidewall may protrude beyond an adjacent sidewall of the gate electrode.
在各種實施例中,該快速蝕刻區域之一寬度可比該LDD之一寬度窄。該快速蝕刻區域之一第一深度可比該LDD之一第二深度淺。該LDD之一部份可形成在該作用區域與該快速蝕刻區域之間。在形成該應力件後,該快速蝕刻區域之一部份可在該LDD與該應力件之間。 In various embodiments, one of the fast etch regions may have a width that is narrower than one of the LDDs. One of the fast etched regions may have a first depth that is shallower than a second depth of the one of the LDDs. A portion of the LDD may be formed between the active region and the fast etched region. After the stress member is formed, a portion of the fast etched region may be between the LDD and the stress member.
依據各種實施例,該方法可更包括在形成該LDD之前,在該作用區域上形成一預備閘極電極且在該預備閘極電極之一側壁上形成一分隔件及在形成該應力件後,移除該預備閘極電極。 According to various embodiments, the method may further include: forming a preliminary gate electrode on the active region and forming a spacer on one sidewall of the preliminary gate electrode and forming the stress member before forming the LDD; The preliminary gate electrode is removed.
依據各種實施例,該方法可包括在形成該快速蝕刻區域之前,在該作用區域上形成一預備閘極電極且在該 預備閘極電極之一側壁上形成一分隔件及在形成該應力件後,移除該預備閘極電極。 According to various embodiments, the method may include forming a preliminary gate electrode on the active region and forming the flash etched region A spacer is formed on a sidewall of one of the preliminary gate electrodes, and after the stressor is formed, the preliminary gate electrode is removed.
在各種實施例中,該方法可包括在形成該第一槽之前,在該作用區域上形成一預備閘極電極且在該預備閘極電極之一側壁上形成一分隔件及在形成該應力件後,移除該預備閘極電極。 In various embodiments, the method can include forming a preliminary gate electrode on the active region and forming a spacer on a sidewall of the preliminary gate electrode and forming the stress member before forming the first trench After that, the preliminary gate electrode is removed.
依據各種實施例,形成該應力件可包括在該第二槽中形成一第一半導體層,在該第一半導體層上形成一第二半導體層及在該第二半導體層上形成一第三半導體層。該等第一及第二半導體層可包括該作用區域所缺少之一材料。形成該等第一、第二及第三半導體層可包括實施選擇磊晶成長(SEG)程序。依據各種實施例,該等第一與第二半導體層可包括各自之矽鍺層,且該第二半導體層之一鍺濃度可比該第一半導體層之鍺濃度大。該第三半導體層可包括一Si層。 According to various embodiments, forming the stress member may include forming a first semiconductor layer in the second trench, forming a second semiconductor layer on the first semiconductor layer, and forming a third semiconductor on the second semiconductor layer Floor. The first and second semiconductor layers may include a material that is missing from the active region. Forming the first, second, and third semiconductor layers can include performing a selective epitaxial growth (SEG) process. According to various embodiments, the first and second semiconductor layers may include respective germanium layers, and one of the second semiconductor layers may have a germanium concentration greater than a germanium concentration of the first semiconductor layer. The third semiconductor layer may include a Si layer.
一種形成一半導體裝置之方法可包括在一第一作用區域中形成一輕摻雜汲極(LDD)且在一第二作用區域中形成一第二LDD及在該第一作用區域之LDD中形成一第一快速蝕刻區域且在該第二作用區域之第二LDD中形成一第二快速蝕刻區域。該第一作用區域可在一基材之一第一區域中且該第二作用區域可在該基材之一第二區域中。該等第一與第二快速蝕刻區域可包括磷。該方法亦可包括藉由使該等第一與第二快速蝕刻區域分別凹陷,形成一第一預備槽及一第二預備槽,及藉由使用一方向性蝕刻 程序分別擴大該等第一與第二預備槽,形成一第一槽及一第二槽。該第一槽可包括該第一作用區域之一第一缺口部份且該第二槽可包括該第二作用區域之一第二缺口部份。該方法可更包括在該第一槽中形成一第一應力件且在該第二槽中形成一第二應力件及在該第一作用區域上形成一第一閘極電極且在該第二作用區域上形成一第二閘極電極。 A method of forming a semiconductor device can include forming a lightly doped drain (LDD) in a first active region and forming a second LDD in a second active region and forming in the LDD of the first active region a first fast etched region and a second fast etched region formed in the second LDD of the second active region. The first active region can be in a first region of one of the substrates and the second active region can be in a second region of the substrate. The first and second fast etch regions may include phosphorous. The method may further include forming a first preliminary trench and a second preliminary trench by recessing the first and second fast etch regions, respectively, and using a directional etching The program expands the first and second preliminary grooves to form a first groove and a second groove. The first slot may include a first notch portion of the first active region and the second slot may include a second notch portion of the second active region. The method may further include forming a first stress member in the first trench and forming a second stress member in the second trench and forming a first gate electrode on the first active region and in the second A second gate electrode is formed on the active area.
依據各種實施例,該第一作用區域之第一缺口部份可包括在一第一會合界面接觸一第一下側壁之一第一上側壁且該第二作用區域之第二缺口部份可包括在一第二會合界面接觸一第二下側壁之一第二上側壁。該第一閘極電極可重疊該第一會合界面且該第二閘極電極可不重疊該第二會合界面。該第一會合界面可比該第二會合界面高。 According to various embodiments, the first notch portion of the first active area may include a first upper side wall contacting a first lower side wall at a first meeting interface and a second notch portion of the second active area may include Contacting a second upper sidewall of a second lower sidewall at a second junction interface. The first gate electrode may overlap the first meeting interface and the second gate electrode may not overlap the second meeting interface. The first meeting interface can be higher than the second meeting interface.
在各種實施例中,在該第一會合界面與該第一閘極電極之一側壁之間的一水平距離可在0nm至5nm之範圍內,且在該第二會合界面與該第二閘極電極之一側壁之間的一水平距離可在1nm至3nm之範圍內。 In various embodiments, a horizontal distance between the first meeting interface and one of the sidewalls of the first gate electrode may be in a range of 0 nm to 5 nm, and the second meeting interface and the second gate are A horizontal distance between one of the sidewalls of the electrode can range from 1 nm to 3 nm.
在各種實施例中,在該第一會合界面與該第一作用區域之一最上方表面之間的一垂直距離可在3nm至7nm之範圍內,且在該第二會合界面與該第二作用區域之一最上方表面之間的一垂直距離可在8nm至12nm之範圍內。 In various embodiments, a vertical distance between the first meeting interface and an uppermost surface of the first active region may be in the range of 3 nm to 7 nm, and the second meeting interface and the second function are A vertical distance between the uppermost surfaces of one of the regions may range from 8 nm to 12 nm.
依據各種實施例,該第一會合界面可形成在該 第一LDD之一表面上,且該第二會合界面可形成在該第二LDD之一表面上並且其中該第二LDD之一硼濃度可比該第一LDD之一硼濃度大。 According to various embodiments, the first meeting interface may be formed in the One surface of the first LDD may be formed on one surface of the second LDD and wherein one of the second LDDs may have a boron concentration greater than a boron concentration of the first LDD.
在各種實施例中,該第二快速蝕刻區域之一磷濃度可比該第一快速蝕刻區域之一磷濃度小。 In various embodiments, one of the second fast etch regions may have a phosphorous concentration that is less than one of the first fast etch regions.
一種半導體裝置可包括:一基材,包括第一與第二區域;一第一閘極電極,係在該第一區域之一第一作用區域上;一第一槽,係在該第一作用區域中且與該第一閘極電極之一側相鄰;及一第一埋入應力件,係在該第一槽中。該裝置亦可包括:一第二閘極電極,係在該第二區域之一第二作用區域中;一第二槽,係在該第二作用區域中且與該第二閘極電極之一側相鄰;及一第二埋入應力件,係在該第二槽中。該等第一與第二區域可包括各自不同之圖案密度。該第一作用區域可包括該第一作用區域之一第一缺口部份且該第二槽可包括該第二作用區域之一第二缺口部份。該第一缺口部份可包括一第一上側壁及一與該第一上側壁接觸之第一下側壁,且該第一上側壁及該第一下側壁可在一第一會合界面會合。該第二缺口部份可包括一第二上側壁及一與該第二上側壁接觸之第二下側壁,且該第二上側壁及該第一下側壁可在一第一會合界面會合。該第一閘極電極可重疊該第二會合界面且該第一會合界面可比該第二會合界面高。 A semiconductor device can include: a substrate including first and second regions; a first gate electrode on a first active region of the first region; a first slot in the first function And in a region adjacent to one side of the first gate electrode; and a first buried stress member is in the first groove. The device may further include: a second gate electrode in a second active region of the second region; a second slot in the second active region and one of the second gate electrodes Side adjacent; and a second embedded stress member in the second groove. The first and second regions may include respective different pattern densities. The first active area may include a first notch portion of the first active area and the second groove may include a second notched portion of the second active area. The first notch portion may include a first upper sidewall and a first lower sidewall contacting the first upper sidewall, and the first upper sidewall and the first lower sidewall may meet at a first meeting interface. The second notch portion may include a second upper sidewall and a second lower sidewall contacting the second upper sidewall, and the second upper sidewall and the first lower sidewall may meet at a first meeting interface. The first gate electrode may overlap the second meeting interface and the first meeting interface may be higher than the second meeting interface.
一種半導體裝置可包括:一基材,包括一作用區域;一閘極電極,係在該作用區域上;及一輕摻雜汲極 (LDD),係在該作用區域中且與該閘極電極之一側相鄰,該LDD包括硼及磷。該磷之一濃度可在5×1018原子/cm3至1×1019原子/cm3。該裝置亦可包括在該作用區域中且與該閘極電極之該側相鄰之槽,且該槽包括該作用區域之一缺口部份及在該槽中之一埋入應力件。 A semiconductor device can include: a substrate including an active region; a gate electrode on the active region; and a lightly doped drain (LDD) in the active region and the gate electrode Adjacent to one side, the LDD includes boron and phosphorus. One of the phosphorus concentrations may be from 5 x 10 18 atoms/cm 3 to 1 x 10 19 atoms/cm 3 . The device can also include a slot in the active region adjacent the side of the gate electrode, and the slot includes a notched portion of the active region and a stress member embedded in one of the slots.
一種形成一半導體裝置之方法可包括在一基材上形成一閘極結構及在該基材中形成與該閘極結構之一側相鄰的摻雜圖案。該方法亦可包括藉由使用該閘極結構作為一蝕刻遮罩蝕刻該摻雜圖案之一部份而形成一第一預備孔穴;藉由選擇地蝕刻該摻雜圖案形成一第二預備孔穴;藉由使用一方向性蝕刻程序蝕刻該第二預備孔穴之暴露表面而形成一孔穴;及在該孔穴中形成一應力件。該第一預備孔穴之一側可暴露該摻雜圖案。該孔穴可包括一在該閘極結構下方之凹處且該凹處可包括兩會合傾斜部份。 A method of forming a semiconductor device can include forming a gate structure on a substrate and forming a doping pattern adjacent to one side of the gate structure in the substrate. The method may further include forming a first preliminary hole by etching the portion of the doping pattern by using the gate structure as an etch mask; forming a second preliminary hole by selectively etching the doping pattern; Forming a hole by etching a exposed surface of the second preliminary cavity using a directional etching process; and forming a stress member in the hole. One side of the first preliminary cavity may expose the doping pattern. The aperture can include a recess below the gate structure and the recess can include two converging slope portions.
在各種實施例中,形成該摻雜圖案可包括使用該閘極結構作為一植入遮罩將多數元素植入該基材。植入該等元素可包括將磷植入該基材。 In various embodiments, forming the doping pattern can include implanting a majority of elements into the substrate using the gate structure as an implant mask. Implanting the elements can include implanting phosphorus into the substrate.
依據各種實施例,該方法可更包括在形成該摻雜圖案之前在該基材中形成一與該閘極結構之該側相鄰之輕摻雜汲極(LDD)。該摻雜圖案之至少一部份可形成在該LDD中。該方法可另外包括在形成該LDD後,在該閘極結構之一側形成一分隔件圖案。植入該等元素可包括使用該分隔件圖案及該閘極結構作為一植入遮罩植入該等元素。 According to various embodiments, the method may further include forming a lightly doped drain (LDD) adjacent to the side of the gate structure in the substrate prior to forming the doped pattern. At least a portion of the doping pattern can be formed in the LDD. The method can additionally include forming a spacer pattern on one side of the gate structure after forming the LDD. Implanting the elements can include implanting the elements using the spacer pattern and the gate structure as an implant mask.
在各種實施例中,該方向性蝕刻程序可包括依 據該基材之晶體取向以不同蝕刻速度蝕刻該基材的一蝕刻程序且該凹處可包括一缺口部份,且該缺口部份包括兩會合傾斜部份。 In various embodiments, the directional etch process can include An etching process for etching the substrate at different etch rates according to the crystal orientation of the substrate and the recess may include a notched portion, and the notched portion includes two converging inclined portions.
21‧‧‧基材 21‧‧‧Substrate
22‧‧‧井部 22‧‧‧ Wells
23‧‧‧作用區域 23‧‧‧Action area
23S1‧‧‧第一側表面 23S1‧‧‧ first side surface
23S2‧‧‧第二側表面 23S2‧‧‧ second side surface
23S3‧‧‧第二表面 23S3‧‧‧ second surface
23SU‧‧‧第一表面 23SU‧‧‧ first surface
29‧‧‧裝置隔離層 29‧‧‧Device isolation
31‧‧‧緩衝層 31‧‧‧ Buffer layer
33‧‧‧暫時閘極電極 33‧‧‧Temporary gate electrode
33T‧‧‧閘極槽 33T‧‧‧ gate slot
35‧‧‧第一遮罩圖案;第一下遮 罩圖案 35‧‧‧First mask pattern; first under cover Cover pattern
37‧‧‧第二遮罩圖案;第一上遮罩圖案 37‧‧‧ second mask pattern; first upper mask pattern
42‧‧‧第一分隔件 42‧‧‧First partition
43‧‧‧輕摻雜汲極(LDD) 43‧‧‧Lightly doped bungee (LDD)
45‧‧‧暈圈 45‧‧‧Halo
47‧‧‧第二分隔件;第一中間分 隔件 47‧‧‧Second partition; first intermediate point Spacer
47A‧‧‧第二分隔件 47A‧‧‧Second separator
49‧‧‧較快蝕刻速度部 49‧‧‧faster etching speed
51‧‧‧第三分隔件;第一外分隔件 51‧‧‧ third partition; first outer partition
51T‧‧‧凹區域 51T‧‧‧ recessed area
53‧‧‧第一槽 53‧‧‧first slot
53A‧‧‧上槽 53A‧‧‧上槽
53B‧‧‧下槽 53B‧‧‧Slot
55‧‧‧第二槽;第一槽 55‧‧‧second trough; first trough
61‧‧‧第一半導體層 61‧‧‧First semiconductor layer
61A‧‧‧第一半導體層 61A‧‧‧First semiconductor layer
61B‧‧‧第一半導體層 61B‧‧‧First semiconductor layer
62‧‧‧第二半導體層 62‧‧‧Second semiconductor layer
63‧‧‧第三半導體層 63‧‧‧ third semiconductor layer
65‧‧‧埋入應力件 65‧‧‧buried stress parts
65A‧‧‧埋入應力件 65A‧‧‧buried stress parts
65B‧‧‧埋入應力件 65B‧‧‧buried stress parts
71‧‧‧層間絕緣層 71‧‧‧Interlayer insulation
73‧‧‧第一閘極介電層 73‧‧‧First gate dielectric layer
75‧‧‧第二閘極介電層 75‧‧‧Second gate dielectric layer
77‧‧‧第一閘極電極 77‧‧‧First gate electrode
79‧‧‧第二閘極電極 79‧‧‧second gate electrode
100‧‧‧半導體晶片 100‧‧‧Semiconductor wafer
101‧‧‧記憶體區域 101‧‧‧ memory area
101C‧‧‧第二區域 101C‧‧‧Second area
101P‧‧‧SRAM周邊區域 101P‧‧‧SRAM area
102‧‧‧第一區域 102‧‧‧First area
131‧‧‧閘極介電層 131‧‧‧ gate dielectric layer
133‧‧‧第一閘極電極 133‧‧‧first gate electrode
134‧‧‧內分隔件 134‧‧ ‧ inner partition
142‧‧‧第一分隔件 142‧‧‧First partition
147‧‧‧第二分隔件 147‧‧‧Second partition
151‧‧‧第三分隔件 151‧‧‧ Third partition
181‧‧‧第二閘極電極 181‧‧‧second gate electrode
183‧‧‧蝕刻停止層 183‧‧‧etch stop layer
185‧‧‧層間絕緣層 185‧‧‧Interlayer insulation
221‧‧‧基材 221‧‧‧Substrate
222‧‧‧井部 222‧‧‧ Wells
223‧‧‧作用區域 223‧‧‧Action area
225‧‧‧緩衝層 225‧‧‧buffer layer
223S1‧‧‧第一側表面 223S1‧‧‧ first side surface
223S2‧‧‧第二側表面 223S2‧‧‧ second side surface
223S3‧‧‧第三側表面 223S3‧‧‧ third side surface
223S4‧‧‧第二表面 223S4‧‧‧ second surface
223S5‧‧‧第一側表面 223S5‧‧‧ first side surface
223SU‧‧‧第一表面 223SU‧‧‧ first surface
229‧‧‧裝置隔離層 229‧‧‧Device isolation
231‧‧‧暫時閘極介電層 231‧‧‧ Temporary gate dielectric layer
233‧‧‧暫時閘極電極 233‧‧‧Temporary gate electrode
233T‧‧‧閘極槽 233T‧‧ ‧ gate slot
235‧‧‧第一遮罩圖案 235‧‧‧First mask pattern
237‧‧‧第二遮罩圖案 237‧‧‧Second mask pattern
242‧‧‧第一分隔件 242‧‧‧First partition
243‧‧‧輕摻雜汲極(LDD) 243‧‧‧Lightly doped bungee (LDD)
245‧‧‧暈圈 245‧‧‧Halo
247‧‧‧第二分隔件 247‧‧‧Second partition
249‧‧‧較快蝕刻速度部 249‧‧‧faster etching speed
251‧‧‧第三分隔件 251‧‧‧ third partition
253‧‧‧第一槽 253‧‧‧first slot
253A‧‧‧上槽 253A‧‧‧上槽
253B‧‧‧下槽 253B‧‧‧Slot
255‧‧‧第二槽 255‧‧‧second slot
255A‧‧‧第二槽 255A‧‧‧second slot
255‧‧‧第二槽 255‧‧‧second slot
262‧‧‧第二半導體層 262‧‧‧Second semiconductor layer
262A‧‧‧第二半導體層 262A‧‧‧second semiconductor layer
262B‧‧‧第二半導體層 262B‧‧‧Second semiconductor layer
263‧‧‧第三半導體層 263‧‧‧ third semiconductor layer
265‧‧‧埋入應力件 265‧‧‧buried stress parts
271‧‧‧層間絕緣層 271‧‧‧Interlayer insulation
273‧‧‧第一閘極介電層 273‧‧‧First gate dielectric layer
275‧‧‧第二閘極介電層 275‧‧‧Second gate dielectric layer
279‧‧‧閘極電極 279‧‧‧gate electrode
322‧‧‧第二井部 322‧‧‧Second well
323‧‧‧第二作用區域 323‧‧‧Second action area
323S1‧‧‧第三側表面 323S1‧‧‧ third side surface
323S2‧‧‧第四側表面 323S2‧‧‧ fourth side surface
323S3‧‧‧第四表面 323S3‧‧‧ fourth surface
323SU‧‧‧第三表面 323SU‧‧‧ third surface
329‧‧‧第二裝置隔離層 329‧‧‧Second device isolation
331‧‧‧第二緩衝層 331‧‧‧Second buffer layer
333‧‧‧第二暫時閘極電極 333‧‧‧Second temporary gate electrode
335‧‧‧第二下遮罩圖案 335‧‧‧Second lower mask pattern
337‧‧‧第二上遮罩圖案 337‧‧‧Second upper mask pattern
342‧‧‧第二內分隔件 342‧‧‧Second inner divider
343‧‧‧第二LDD 343‧‧‧Second LDD
345‧‧‧第二暈圈 345‧‧‧second halo
347‧‧‧第二中間分隔件 347‧‧‧Second intermediate partition
349‧‧‧第二較快蝕刻速度部 349‧‧‧Second faster etch rate
351‧‧‧第二外分隔件 351‧‧‧Second outer divider
353‧‧‧第二預備槽 353‧‧‧Second preparation tank
353A‧‧‧第二上槽 353A‧‧‧Second upper trough
353B‧‧‧第二下槽 353B‧‧‧Second trough
355‧‧‧第二槽 355‧‧‧second trough
361‧‧‧第四半導體層 361‧‧‧fourth semiconductor layer
362‧‧‧第五半導體層 362‧‧‧ fifth semiconductor layer
363‧‧‧第六半導體層 363‧‧‧ sixth semiconductor layer
365‧‧‧第二埋入應力件 365‧‧‧Second buried stress
371‧‧‧第二層間絕緣層 371‧‧‧Second interlayer insulation
373‧‧‧第三閘極介電層 373‧‧‧ Third Gate Dielectric Layer
375‧‧‧第四閘極介電層 375‧‧‧fourth gate dielectric layer
377‧‧‧第三閘極電極 377‧‧‧3rd gate electrode
379‧‧‧第四閘極電極 379‧‧‧fourth gate electrode
500-570‧‧‧方塊 500-570‧‧‧ square
1900‧‧‧智慧型手機 1900‧‧‧Smart Phone
2100‧‧‧電子系統 2100‧‧‧Electronic system
2110‧‧‧本體 2110‧‧‧ Ontology
2120‧‧‧微處理器單元 2120‧‧‧Microprocessor unit
2130‧‧‧電源單元 2130‧‧‧Power unit
2140‧‧‧功能單元 2140‧‧‧ functional unit
2150‧‧‧顯示器控制單元 2150‧‧‧Display Control Unit
2160‧‧‧顯示器單元 2160‧‧‧Display unit
2170‧‧‧外部設備 2170‧‧‧External equipment
2180‧‧‧有線或無線通訊單元 2180‧‧‧Wired or wireless communication unit
2400‧‧‧電子系統 2400‧‧‧Electronic system
2412‧‧‧記憶體系統 2412‧‧‧Memory System
2414‧‧‧微處理器 2414‧‧‧Microprocessor
2416‧‧‧隨機存取記憶體(RAM) 2416‧‧‧ Random Access Memory (RAM)
2418‧‧‧使用者介面 2418‧‧‧User interface
2420‧‧‧匯流排 2420‧‧ ‧ busbar
E1‧‧‧第一邊緣 E1‧‧‧ first edge
E2‧‧‧第二邊緣 E2‧‧‧ second edge
E31‧‧‧第三邊緣 E31‧‧‧ third edge
E32‧‧‧第四邊緣 E32‧‧‧ fourth edge
X‧‧‧水平距離 X‧‧‧ horizontal distance
Y‧‧‧垂直高度 Y‧‧‧Vertical height
X1‧‧‧第一水平距離 X1‧‧‧first horizontal distance
Y1‧‧‧第一垂直高度 Y1‧‧‧first vertical height
X3‧‧‧第二水平距離 X3‧‧‧Second horizontal distance
Y3‧‧‧第二垂直高度 Y3‧‧‧second vertical height
圖1係一流程圖,顯示形成依據本發明觀念之某些實施例之一半導體裝置的方法。 1 is a flow chart showing a method of forming a semiconductor device in accordance with some embodiments of the inventive concept.
圖2、3、4A、4B、5A至5C、6A至6C、7A至7C、8A至8C、9至13與14A至14G係橫截面圖,顯示在形成依據本發明觀念之某些實施例之一半導體裝置的操作中所提供之中間結構。 2, 3, 4A, 4B, 5A to 5C, 6A to 6C, 7A to 7C, 8A to 8C, 9 to 13 and 14A to 14G are cross-sectional views showing the formation of certain embodiments in accordance with the teachings of the present invention. An intermediate structure provided in the operation of a semiconductor device.
圖15係橫截面圖,顯示在形成依據本發明觀念之某些實施例之一半導體裝置的操作中所提供之一中間結構。 Figure 15 is a cross-sectional view showing an intermediate structure provided in the operation of forming a semiconductor device in accordance with some embodiments of the present inventive concept.
圖16係依據本發明觀念之某些實施例之一半導體裝置的一配置。 16 is a diagram of a configuration of a semiconductor device in accordance with some embodiments of the inventive concept.
圖17至24、25A至25C、26至30與31A至31C係沿圖16之線I-I'與II-II'所截取之橫截面圖,顯示在形成依據本發明觀念之某些實施例之一半導體裝置的操作中所提供之中間結構。 17 to 24, 25A to 25C, 26 to 30, and 31A to 31C are cross-sectional views taken along lines I-I' and II-II' of Fig. 16, and are shown in some embodiments for forming the concept according to the present invention. An intermediate structure provided in the operation of one of the semiconductor devices.
圖32係依據本發明觀念之某些實施例之一半導體裝置的一配置。 32 is a configuration of a semiconductor device in accordance with some embodiments of the inventive concept.
圖33至38係橫截面圖,顯示在形成依據本發明觀念之某些實施例之一半導體裝置的操作中所提供之中間結 構。 33 through 38 are cross-sectional views showing intermediate junctions provided in the operation of forming a semiconductor device in accordance with certain embodiments of the present inventive concept. Structure.
圖39與40係依據本發明觀念之某些實施例之一電子設備的立體圖及方塊圖。 39 and 40 are perspective and block diagrams of an electronic device in accordance with some embodiments of the inventive concept.
圖41係依據本發明觀念之某些實施例之一電子系統的方塊圖。 Figure 41 is a block diagram of an electronic system in accordance with some embodiments of the inventive concept.
以下參照附圖說明多數實施例。在不偏離這揭露內容之精神與教示之情形下可有許多不同形態及實施例且因此該揭露內容不應被視為在此提出之實施例的限制。相反地,所提供之這些實施例使這說明將是詳盡且完整的,且將該揭露內容之範圍告知所屬技術領域中具有通常知識者。在圖式中,層與區域之尺寸及相對尺寸會誇大以便清楚顯示。類似符號表示全部類似元件。 Most of the embodiments are described below with reference to the drawings. There may be many different forms and embodiments without departing from the spirit and scope of the disclosure, and thus the disclosure should not be construed as limiting the embodiments presented herein. Rather, these embodiments are provided so that this description will be thorough and complete, and the scope of the disclosure will be disclosed to those of ordinary skill in the art. In the drawings, the dimensions and relative sizes of layers and regions are exaggerated for clarity. Like symbols indicate all similar elements.
應了解的是當一元件被稱為與另一元件“連接”或“耦合”時,它可與另一元件直接連接或耦合或可存在多數中間元件。相反地,當一元件被稱為與另一元件“直接連接”或“直接耦合”時,沒有中間元件。用以說明元件之間之關係的其他字應以一相似方式解讀(即,“在…之間”對“直接在…之間”,“相鄰”對“直接相鄰”等)。 It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element. Other words used to describe the relationship between the elements should be interpreted in a similar manner (i.e., "between", "directly between", "adjacent", "directly adjacent", etc.).
應了解的是,雖然在此可使用該等用語第一、第二等表示本發明之元件,該等元件不應被視為受限於這些用語。在不偏離本發明之範圍的情形下,例如,一第一元件可稱為一第二元件,且一第二元件可稱為一第一元件。 在此,該用語“及/或”包括一或一以上相關對象之任一或所有組合。 It will be appreciated that, although the terms first, second, etc. may be used herein to refer to the elements of the invention, such elements are not to be construed as being limited. Without departing from the scope of the invention, for example, a first element may be referred to as a second element and a second element may be referred to as a first element. Here, the term "and/or" includes any or all combinations of one or more related objects.
在此可使用如“正下方”、“以下”、“下方”、“以上”、“上方”等空間相對用語以輕易地說明圖中所示之一元件或特徵與另一元件或特徵之關係。在此應了解的是該等空間相對用語係欲包含該裝置在使用或操作時,除了圖中所示之方位以外之不同方位。例如,如果在圖中之裝置翻轉,則以在其他元件或特徵“以下”或“正下方”說明之元件係定向為在其他元件或特徵“以上”。如此,該用語”以下”可包含以上與以下之方位。又,該裝置可另外定向(旋轉90度或在其他方位上)且在此所使用之該等空間相對用語亦可依此解讀。 Spatially relative terms such as "directly below", "below", "below", "above", "above", etc., may be used to describe the relationship of one element or feature to another element or feature. . It should be understood that the spatially relative terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, the elements are described as "below" or "below" the other elements or features are "above" the other elements or features. As such, the term "below" can encompass the above and the following. Again, the device can be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative terms used herein can also be interpreted accordingly.
在此用來說明本發明之實施例的用語不是意圖限制本發明之範圍。該冠詞“一”與“該”係表示它們具有一單一相關對象的單數,但是在本文獻中使用單數形不應排除存在一以上之相關對象。換言之,除非本文另外清楚地指出,否則表示單數之本發明之元件的可具有一或一以上之數目。在此亦應了解的是當在此使用時,該等用語包含”及/或“包括”係指存在所述之特徵、零件、步驟、操作、元件及/或組件,但並未排除存在或再加入一或一以上其他特徵、零件、步驟、操作、構件、組件及/或其群組。 The terms used herein to describe the embodiments of the invention are not intended to limit the scope of the invention. The articles "a" and "the" are intended to mean that they have a s In other words, the elements of the invention, which are singular, may have one or more. It is also to be understood that the phrase "and" or "includes" or "includes," One or more other features, parts, steps, operations, components, components, and/or groups thereof are added.
在此參照示意顯示本發明之理想實施例(及中間結構)之橫截面圖說明多數實施例。因此,可預期由於例如製造方法及/或公差所造成之圖式形狀的變化。如此,實施 例不應被解讀為受限於在此所示區域之特殊形狀,而是應包括,例如,因製造所產生之形狀上的偏差。例如,一顯示為矩形之植入區域,通常在其邊緣處將具有圓化或彎曲特徵及/或一植入濃度梯度,而不是由已植入至未植入區域之雙態變化。類似地,一由植入所形成之已埋入區域會在該已埋入區域與被穿過而發生該植入之表面之間的一區域中產生某種植入,因此,在圖式中所示之區域本質上是以示意方式顯示且它們的形狀不是要顯示一裝置之一區域之精確形狀並且不是意圖限制本發明觀念之範圍。 Most of the embodiments are illustrated herein with reference to cross-section illustrations of the preferred embodiments (and intermediate structures) of the invention. Thus, variations in the shape of the drawings due to, for example, manufacturing methods and/or tolerances are contemplated. So, implement The examples should not be construed as being limited to the particular shapes of the regions illustrated herein, but should include, for example, variations in the shape resulting from the manufacture. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or an implant concentration gradient at its edges rather than a two-state change that has been implanted into the unimplanted region. Similarly, a buried region formed by implantation creates an implant in a region between the buried region and the surface through which the implantation occurs, and thus, in the drawings The regions shown are shown in schematic form in nature and their shapes are not intended to indicate the precise shape of one of the regions of the device and are not intended to limit the scope of the inventive concept.
除非另外定義,在此使用之所有用語(包括技術與科學用語)可被解讀為在發明所屬技術領域中是通常的。在此更應了解的是,在一般使用字典中定義之用語應被解釋為在相關技術中是通常的,且除非在此明白地定義,否則不應以一理想化或過度形式判斷之方式解讀。 Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as being It should be understood here that the terms defined in the general use of the dictionary should be interpreted as being common in the related art, and should not be interpreted in an idealized or excessively formal manner unless explicitly defined herein. .
應注意的是在某些其他實施例中,在此之流程方塊圖中所註記之功能/動作可不依在流程圖中所註記之順序發生。例如,依據所涉及之功能/動作,連續之所示兩方塊事實上可實質上同時實行或該等方塊有時可以相反之順序實行。此外,該等流程圖及/或方塊圖之一給定方塊之功能可分成多數方塊及/或該等流程圖及/或方塊圖之二或二以上方塊之功能可至少部份地整合。最後,在不偏離本發明之範圍的情形下,可在所示該等方塊之間添加或插入其他方塊,及/或可省略方塊/操作。 It should be noted that in some other embodiments, the functions/acts noted in the flow block diagrams herein may not occur in the order noted in the flowchart. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may be carried out in the reverse order. In addition, the functions of a given block of one of the flowcharts and/or block diagrams may be divided into a plurality of blocks and/or the functions of the two or more blocks of the flowcharts and/or block diagrams may be at least partially integrated. Finally, other blocks may be added or inserted between the blocks shown, and/or blocks/operations may be omitted, without departing from the scope of the invention.
雖然在凹處包括一應力件的一電晶體可增加載 子移動性,但是在一裝置內之凹處之尺寸及形狀可有大變化。但是,本發明觀念之各種實施例提供形成一半導體裝置之方法,該等方法包括形成可控制一凹處之尺寸及形狀的一較快蝕刻速度部。因此,在此所述之方法可減少在一裝置內之凹處之尺寸及形狀的變化。 Although a transistor including a stress member in the recess can increase the load Sub-mobility, but the size and shape of the recess in a device can vary widely. However, various embodiments of the inventive concept provide a method of forming a semiconductor device that includes forming a faster etch rate portion that can control the size and shape of a recess. Thus, the methods described herein can reduce variations in the size and shape of the recesses in a device.
圖1係顯示形成依據本發明觀念之某些實施例之一半導體裝置之方法的流程圖。圖2、3、4A、4B、5A至5C、6A至6C、7A至7C、8A至8C、9至13與14A至14G係顯示在形成依據本發明觀念之某些實施例之一半導體裝置之操作中所提供的中間結構之橫截面圖。 1 is a flow chart showing a method of forming a semiconductor device in accordance with some embodiments of the inventive concept. 2, 3, 4A, 4B, 5A to 5C, 6A to 6C, 7A to 7C, 8A to 8C, 9 to 13 and 14A to 14G are shown in a semiconductor device forming a certain embodiment according to the inventive concept. A cross-sectional view of the intermediate structure provided in the operation.
請參閱圖1,依據本發明觀念之某些實施例之一半導體裝置之一方法可包括形成一輕摻雜汲極(LDD)(方塊500),形成一較快蝕刻速度部(方塊510),形成一第一槽(方塊520),形成一第二槽(方塊530),形成一第一半導體層(方塊540),形成一第二半導體層(方塊550),形成一第三半導體層(方塊560),及形成一層間絕緣層(方塊570)。 Referring to FIG. 1, a method of a semiconductor device according to some embodiments of the inventive concept may include forming a lightly doped drain (LDD) (block 500) to form a faster etch rate portion (block 510). Forming a first trench (block 520), forming a second trench (block 530), forming a first semiconductor layer (block 540), forming a second semiconductor layer (block 550), forming a third semiconductor layer (block 560), and forming an interlayer insulating layer (block 570).
請參閱圖1與2,在一基材21上可形成一井部22、一作用區域23、一裝置隔離層29、一緩衝層31、一暫時閘極電極33、一第一遮罩圖案35及一第二遮罩圖案37。該基材21可以是一單結晶半導體基材,例如一矽晶圓或一絕緣體上覆矽(SOI)晶圓。該基材21可包括第一導電性型雜質。該井部22可包括與該第一導電性型雜質不同之第二導電性型雜質。 Referring to FIGS. 1 and 2, a well portion 22, an active region 23, a device isolation layer 29, a buffer layer 31, a temporary gate electrode 33, and a first mask pattern 35 may be formed on a substrate 21. And a second mask pattern 37. The substrate 21 can be a single crystalline semiconductor substrate, such as a germanium wafer or a silicon-on-insulator (SOI) wafer. The substrate 21 may include a first conductive type impurity. The well portion 22 may include a second conductivity type impurity different from the first conductivity type impurity.
以下,將在該第一導電性型係p型且該第二導電 性型係n型之假設下進行說明。但是,在某些實施例中,該第一導電性型雜質可為n型且該第二導電性型雜質可為p型。例如,該基材21可為包括p型雜質之單結晶矽,且該井部22係包括n型雜質之單結晶矽。該基材21可包括硼(B),且該井部22可包括As、P或其組合。 Hereinafter, the first conductive type is p-type and the second conductive The description of the sex type n type is given. However, in some embodiments, the first conductivity type impurity may be an n type and the second conductivity type impurity may be a p type. For example, the substrate 21 may be a single crystal ruthenium including a p-type impurity, and the well portion 22 is a single crystal ruthenium including an n-type impurity. The substrate 21 can include boron (B), and the well 22 can include As, P, or a combination thereof.
該作用區域23可藉由該裝置隔離層29局限於該井部22。該作用區域23可包含包括n型雜質之單結晶矽。該裝置隔離層29可使用一淺槽隔離(STI)法形成。該裝置隔離層29可包括一絕緣層,例如矽氧化物、矽氮化物、矽氧氮化物或其組合。該緩衝層31可位在該作用區域23與該暫時閘極電極33之間。該緩衝層31可包括一絕緣層,例如矽氧化物、矽氮化物、矽氧氮化物或其組合。例如,該緩衝層31可包括矽氧化物。 The active region 23 can be confined to the well 22 by the device isolation layer 29. The active region 23 may comprise a single crystalline germanium comprising an n-type impurity. The device isolation layer 29 can be formed using a shallow trench isolation (STI) process. The device isolation layer 29 can include an insulating layer such as tantalum oxide, tantalum nitride, tantalum oxynitride or a combination thereof. The buffer layer 31 can be positioned between the active region 23 and the temporary gate electrode 33. The buffer layer 31 may include an insulating layer such as tantalum oxide, tantalum nitride, hafnium oxynitride or a combination thereof. For example, the buffer layer 31 may include a cerium oxide.
該暫時閘極電極33可形成為橫越該作用區域23。該暫時閘極電極33可橫越該作用區域23及該裝置隔離層29。該暫時閘極電極33可包括多晶矽。在某些實施例中,該暫時閘極電極33可包括一絕緣層。該第一遮罩圖案35可形成在該暫時閘極電極33上。該第一遮罩圖案35可包括相對該暫時閘極電極33具有一蝕刻選擇性的一材料。該第二遮罩圖案37可形成在該第一遮罩圖案35上。該第二遮罩圖案37可包括相對該第一遮罩圖案35具有一蝕刻選擇性之一材料。例如,該第一遮罩圖案35可包括矽氧化物。該第二遮罩圖案37可包括矽氮化物或多晶矽。在某些實施例中,可省略該第一遮罩圖案35及該第二遮罩圖案37中之一遮罩 圖案。 The temporary gate electrode 33 may be formed to traverse the active region 23. The temporary gate electrode 33 can traverse the active region 23 and the device isolation layer 29. The temporary gate electrode 33 may include polysilicon. In some embodiments, the temporary gate electrode 33 can include an insulating layer. The first mask pattern 35 may be formed on the temporary gate electrode 33. The first mask pattern 35 can include a material having an etch selectivity with respect to the temporary gate electrode 33. The second mask pattern 37 may be formed on the first mask pattern 35. The second mask pattern 37 can include a material having an etch selectivity with respect to the first mask pattern 35. For example, the first mask pattern 35 may include tantalum oxide. The second mask pattern 37 may include tantalum nitride or polysilicon. In some embodiments, one of the first mask pattern 35 and the second mask pattern 37 may be omitted. pattern.
該第二遮罩圖案37、第一遮罩圖案35、暫時閘極電極33及緩衝層31之側邊可垂直地對齊。該第二遮罩圖案37、第一遮罩圖案35、暫時閘極電極33及緩衝層31可被稱為一暫時閘極圖案31、33、35與37。該暫時閘極圖案31、33、35與37可橫越該作用區域23。多數該等暫時閘極圖案31、33、35與37可平行地形成在該作用區域23上。 The sides of the second mask pattern 37, the first mask pattern 35, the temporary gate electrode 33, and the buffer layer 31 may be vertically aligned. The second mask pattern 37, the first mask pattern 35, the temporary gate electrode 33, and the buffer layer 31 may be referred to as a temporary gate pattern 31, 33, 35, and 37. The temporary gate patterns 31, 33, 35 and 37 can traverse the active region 23. Most of the temporary gate patterns 31, 33, 35 and 37 may be formed in parallel on the active region 23.
請參閱圖1與3,在該暫時閘極電極33之一側壁上可形成一第一分隔件42。一輕摻雜汲極(LDD)43可藉由使用該第一分隔件42、該第二遮罩圖案37、該第一遮罩圖案35及該暫時閘極電極33作為一離子植入遮罩在該作用區域23中植入該等第一導電性型雜質(方塊500)。例如,該LDD43之形成可以一1×1013至5×1014原子/cm2之BF2的用量及一2至5Kev之離子植入能量完成。該LDD43可包括硼。一暈圈45可藉由植入該等第二導電性型雜質至該作用區域23形成。該暈圈45可覆蓋該LDD43之一側及一底部。該LDD43及該暈圈45之形成可包括一離子植入程序及一熱處理程序。 Referring to FIGS. 1 and 3, a first spacer 42 may be formed on one of the sidewalls of the temporary gate electrode 33. A lightly doped drain (LDD) 43 can be used as an ion implantation mask by using the first spacer 42 , the second mask pattern 37 , the first mask pattern 35 , and the temporary gate electrode 33 . The first conductivity type impurities are implanted in the active region 23 (block 500). For example, the formation of the LDD 43 can be accomplished by an amount of BF 2 of 1 × 10 13 to 5 × 10 14 atoms/cm 2 and an ion implantation energy of 2 to 5 KeV. The LDD 43 can include boron. A halo 45 can be formed by implanting the second conductivity type impurities into the active region 23. The halo 45 can cover one side of the LDD 43 and a bottom. The formation of the LDD 43 and the halo 45 can include an ion implantation process and a heat treatment process.
該第一分隔件42可一致地覆蓋該基材21之一上表面。例如,該第一分隔件42可以一固定厚度覆蓋該暫時閘極圖案31、33、35與37之上與側表面,且覆蓋該作用區域23及該裝置隔離層29。該第一分隔件42可包括一絕緣層,例如矽氧化物、矽氮化物、矽氧氮化物或其組合。該第一分隔件42可包括相對該暫時閘極電極33具有一蝕刻選 擇性之一材料。例如,該第一分隔件42可包括矽氮化物。該LDD43可形成為由該作用區域23之一上表面達到某一深度。該LDD43可部份地重疊該暫時閘極圖案31、33、35與37之一底部。該LDD43可藉由調整該第一分隔件42之厚度而形成在一所欲位置。 The first spacer 42 may uniformly cover an upper surface of the substrate 21. For example, the first spacer 42 may cover the upper surface and the side surface of the temporary gate patterns 31, 33, 35 and 37 with a fixed thickness, and cover the active region 23 and the device isolation layer 29. The first spacer 42 may include an insulating layer such as tantalum oxide, tantalum nitride, hafnium oxynitride or a combination thereof. The first spacer 42 may include an etch option with respect to the temporary gate electrode 33 Selective material. For example, the first spacer 42 can include tantalum nitride. The LDD 43 may be formed to reach a certain depth by the upper surface of one of the active regions 23. The LDD 43 may partially overlap the bottom of one of the temporary gate patterns 31, 33, 35 and 37. The LDD 43 can be formed at a desired position by adjusting the thickness of the first spacer 42.
請參閱圖1與4A,一第二分隔件47可形成在該第一分隔件42上。一較快蝕刻速度部49可使用該第二分隔件47作為一離子植入遮罩形成在該作用區域23中(方塊510)。例如,該較快蝕刻速度部49之形成可以一5×1014至3×1015原子/cm2之PH3的用量及一2至5Kev之離子植入能量完成。可使用PH2取代該PH3。該較快蝕刻速度部49可包括磷(P)。 Referring to FIGS. 1 and 4A, a second spacer 47 may be formed on the first spacer 42. A faster etch rate portion 49 can be formed in the active region 23 using the second spacer 47 as an ion implantation mask (block 510). For example, the formation of the faster etching rate portion 49 can be accomplished by an amount of PH 3 of 5 × 10 14 to 3 × 10 15 atoms/cm 2 and an ion implantation energy of 2 to 5 KeV. This PH 3 can be replaced with PH 2 . The faster etch rate portion 49 may include phosphorus (P).
該第二分隔件47可一致地覆蓋該基材21。例如,該第二分隔件47可覆蓋該暫時閘極圖案31、33、35與37之上與側表面,且覆蓋該LDD43及該裝置隔離層29。該第二分隔件47可包括一絕緣層,例如矽氧化物、矽氮化物、矽氧氮化物或其組合。該第二分隔件47可包括相對該暫時閘極電極33具有一蝕刻選擇性之一材料。例如,該第二分隔件47可包括矽氮化物。該第一分隔件42及該第二分隔件47可依序覆蓋該暫時閘極圖案31、33、35與37之側表面。 The second spacer 47 can uniformly cover the substrate 21. For example, the second spacer 47 may cover the upper surface and the side surface of the temporary gate patterns 31, 33, 35 and 37, and cover the LDD 43 and the device isolation layer 29. The second spacer 47 may include an insulating layer such as tantalum oxide, tantalum nitride, tantalum oxynitride or a combination thereof. The second spacer 47 may include a material having an etch selectivity with respect to the temporary gate electrode 33. For example, the second spacer 47 may include tantalum nitride. The first spacer 42 and the second spacer 47 may sequentially cover side surfaces of the temporary gate patterns 31, 33, 35 and 37.
藉由調整該第二分隔件47之厚度,可在一所欲位置形成該較快蝕刻速度部49。該較快蝕刻速度部49可形成在該LDD43中。該較快蝕刻速度部49之一底部可形成在比 該LDD43之一底部高之高度。該較快蝕刻速度部49可形成與該暫時閘極電極33之一外側對齊。該作用區域23可被扣持在該暫時閘極電極33下方。該LDD43可被扣持在該暫時閘極電極33下方。該LDD43可被扣持在該較快蝕刻速度部49與該作用區域23之間。 By adjusting the thickness of the second spacer 47, the faster etching speed portion 49 can be formed at a desired position. The faster etch rate portion 49 can be formed in the LDD 43. The bottom of one of the faster etching speed portions 49 can be formed in a ratio The height of one of the LDDs 43 is high. The faster etch rate portion 49 can be formed to be aligned with one of the outer sides of the temporary gate electrode 33. The active region 23 can be held under the temporary gate electrode 33. The LDD 43 can be held under the temporary gate electrode 33. The LDD 43 can be held between the faster etch rate portion 49 and the active region 23.
請參閱圖1與4B,一第二分隔件47A可形成為具有各種厚度。例如,該第二分隔件47A可形成為具有一1至3nm之厚度。該第二分隔件47A可用以控制該較快蝕刻速度部49之位置。例如,藉由調整該第二分隔件47A之厚度,可控制該較快蝕刻速度部49之一側為位在該LDD43中。藉由調整該第二分隔件47A之厚度,可控制該較快蝕刻速度部49為與該暫時閘極電極33分開。該LDD43可被扣持在該較快蝕刻速度部49與該作用區域23之間。 Referring to FIGS. 1 and 4B, a second spacer 47A may be formed to have various thicknesses. For example, the second spacer 47A may be formed to have a thickness of 1 to 3 nm. The second spacer 47A can be used to control the position of the faster etching speed portion 49. For example, by adjusting the thickness of the second spacer 47A, one side of the faster etching speed portion 49 can be controlled to be positioned in the LDD 43. By adjusting the thickness of the second spacer 47A, the faster etching rate portion 49 can be controlled to be separated from the temporary gate electrode 33. The LDD 43 can be held between the faster etch rate portion 49 and the active region 23.
在某些實施例中,該較快蝕刻速度部49可通過該LDD43。例如,該較快蝕刻速度部49之底部可形成在該暈圈45中。此外,該較快蝕刻速度部49可通過該LDD43與該暈圈45。 In some embodiments, the faster etch rate portion 49 can pass through the LDD 43. For example, the bottom of the faster etch rate portion 49 can be formed in the halo 45. Further, the faster etching speed portion 49 can pass through the LDD 43 and the halo 45.
請參閱圖1與5A,一第三分隔件51可形成在該第二分隔件47上。該第三分隔件51之形成可包括一薄膜形成程序及一異向蝕刻程序。在形成該第三分隔件51時,可部份地移除該第二分隔件47及該第一分隔件42以暴露該較快蝕刻速度部49之一上表面。該第二分隔件47及該第一分隔件42可被扣持在該暫時閘極圖案31、33、35與37與該第三分隔件51之間。 Referring to FIGS. 1 and 5A, a third spacer 51 may be formed on the second spacer 47. The formation of the third spacer 51 may include a thin film forming process and an anisotropic etching process. When the third spacer 51 is formed, the second spacer 47 and the first spacer 42 may be partially removed to expose an upper surface of the faster etching speed portion 49. The second spacer 47 and the first spacer 42 can be held between the temporary gate patterns 31, 33, 35 and 37 and the third spacer 51.
該第三分隔件51可包括一絕緣層,例如矽氧化物、矽氮化物、矽氧氮化物或其組合。該第三分隔件51可包括相對該暫時閘極電極33具有一蝕刻選擇性之一材料。例如,該第三分隔件51可包括矽氮化物。 The third spacer 51 may include an insulating layer such as tantalum oxide, tantalum nitride, hafnium oxynitride or a combination thereof. The third spacer 51 may include a material having an etch selectivity with respect to the temporary gate electrode 33. For example, the third spacer 51 may include tantalum nitride.
請參閱圖1與5B,在形成該第三分隔件51時,可部份地移除該較快蝕刻速度部49以形成一凹區域51T。例如,該凹區域51T可具有一1nm至10nm之深度。 Referring to FIGS. 1 and 5B, when the third spacer 51 is formed, the faster etch rate portion 49 may be partially removed to form a recessed region 51T. For example, the recessed region 51T may have a depth of 1 nm to 10 nm.
請參閱圖1與5C,在形成該第三分隔件51後,可使用另一異向蝕刻程序形成一凹區域51T。該凹區域51T可通過該較快蝕刻速度部49與該LDD43。例如,該凹區域51T可具有一7nm至10nm之深度。該凹區域51T之一底部可暴露該暈圈45。該凹區域51T之側壁可與該第三分隔件51之側表面垂直地對齊。 Referring to FIGS. 1 and 5C, after the third spacer 51 is formed, a recessed region 51T may be formed using another anisotropic etching process. The recessed region 51T can pass the faster etch rate portion 49 and the LDD 43. For example, the recessed region 51T may have a depth of 7 nm to 10 nm. The halo 45 may be exposed at the bottom of one of the concave regions 51T. The side wall of the concave portion 51T may be vertically aligned with the side surface of the third partition 51.
請參閱圖1、6A與6B,可蝕刻該較快蝕刻速度部49、該LDD43及該暈圈45以形成一第一槽53(方塊520)。該第一槽53可包括與該較快蝕刻速度部49對齊之一上槽53A及與該上槽53A之一底部連接的一下槽53B。該上槽53A可形成在該LDD43中。由於該上槽53A,一底切可形成在該第一分隔件42、該第二分隔件47及該第三分隔件51下方。該下槽53B可通過該LDD43而形成在該暈圈45中。該下槽53B可具有比該上槽53A之一寬度小之一寬度。該第一槽53之一側壁可具有一階部。例如,藉由該上槽53A及下槽53B暴露之該LDD43的一側表面可具有一階部。 Referring to FIGS. 1, 6A and 6B, the faster etch rate portion 49, the LDD 43 and the halo 45 may be etched to form a first trench 53 (block 520). The first groove 53 may include an upper groove 53A aligned with the faster etching speed portion 49 and a lower groove 53B connected to one of the bottom portions of the upper groove 53A. The upper groove 53A may be formed in the LDD 43. Due to the upper groove 53A, an undercut may be formed under the first spacer 42, the second spacer 47, and the third spacer 51. The lower groove 53B can be formed in the halo 45 by the LDD 43. The lower groove 53B may have a width smaller than a width of one of the upper grooves 53A. One of the side walls of the first groove 53 may have a first step. For example, one side surface of the LDD 43 exposed by the upper groove 53A and the lower groove 53B may have a first step.
該第一槽53之形成可包括一乾式蝕刻程序,一 濕式蝕刻程序或其組合。該第一槽53之形成可包括一等向蝕刻程序,一異向蝕刻程序或其組合。例如,該第一槽53之形成可包括使用HBr、CF4、O2、Cl2、NF3或其組合之一等向乾式蝕刻程序。依據某些實施例,在該較快蝕刻速度部49中可包括具有比含有硼(B)之單晶矽之蝕刻速度高之一蝕刻速度的含有磷(P)之單晶矽,且因此該較快蝕刻速度部49可具有一比該LDD43之蝕刻速度高的蝕刻速度。依據該較快蝕刻速度部49及該LDD43之構態,可決定該上槽53A及下槽53B之尺寸及形狀。可依需要使用該較快蝕刻速度部49及該LDD43之構態來控制該第一槽53之尺寸、形狀及位置。該第一槽53可均一地形成在該基材21之整個表面上。 The formation of the first trench 53 can include a dry etch process, a wet etch process, or a combination thereof. The formation of the first trench 53 can include an isotropic etch process, an anisotropic etch process, or a combination thereof. For example, the first groove 53 is formed may include the use of HBr, CF 4, O 2, Cl, NF 23 like one or a combination of the dry etching process. According to some embodiments, a single crystal germanium containing phosphorus (P) having an etching rate higher than an etching rate of a single crystal germanium containing boron (B) may be included in the faster etching speed portion 49, and thus The faster etch rate portion 49 can have an etch rate that is higher than the etch rate of the LDD 43. The size and shape of the upper groove 53A and the lower groove 53B can be determined according to the configuration of the faster etching speed portion 49 and the LDD 43. The configuration of the faster etch rate portion 49 and the LDD 43 can be used to control the size, shape and position of the first groove 53 as needed. The first groove 53 may be uniformly formed on the entire surface of the substrate 21.
請參閱圖6C,在某些實施例中,該較快蝕刻速度部49可被扣持在該上槽53A與該LDD43之間。 Referring to FIG. 6C, in some embodiments, the faster etch rate portion 49 can be held between the upper slot 53A and the LDD 43.
請參閱圖1與7A,可使用一方向性蝕刻程序形成一第二槽55(方塊530)。例如,該第二槽55之形成可包括一使用NH4OH、NH3OH、TMAH(四甲基氫氧化銨)、KOH、NaOH、BTMH(苄基三甲基氫氧化銨)或其組合之濕式蝕刻。由於該第二槽55,該作用區域23可具有一西格馬形狀(Σ形狀)。該LDD43可被扣持在該暫時閘極圖案31、33、35與37下方。該作用區域23可包括一第一表面23SU、一第一側表面23S1、一第二側表面23S2及一第二表面23S3。在該第一側表面23S1與該第一表面23SU之間可界定一第一邊緣E1。在該第一側表面23S1與該第二側表面23S2之間可界 定一第二邊緣E2。該第一側表面23S1及該第二側表面23S2之各側表面可包括一{111}晶面。該第二槽55可解讀為該第一槽53之一延伸部。 Referring to Figures 1 and 7A, a second trench 55 can be formed using a directional etch process (block 530). For example, the formation of the second tank 55 may include using NH 4 OH, NH 3 OH, TMAH (tetramethylammonium hydroxide), KOH, NaOH, BTMH (benzyltrimethylammonium hydroxide) or a combination thereof. Wet etching. Due to the second groove 55, the active region 23 may have a sigma shape (Σ shape). The LDD 43 can be held under the temporary gate patterns 31, 33, 35 and 37. The active area 23 can include a first surface 23SU, a first side surface 23S1, a second side surface 23S2, and a second surface 23S3. A first edge E1 may be defined between the first side surface 23S1 and the first surface 23SU. A second edge E2 may be defined between the first side surface 23S1 and the second side surface 23S2. The side surfaces of the first side surface 23S1 and the second side surface 23S2 may include a {111} crystal plane. The second groove 55 can be interpreted as an extension of the first groove 53.
請參閱圖7B,該第二槽55可通過該LDD43及該暈圈45。在該作用區域23之一上端上可界定該第一表面23SU。例如,該第一表面23SU可與該緩衝層31接觸且在該第一分隔件42下方延伸。該第二槽55可暴露該第一側表面23S1、該第二側表面23S2及該第二表面23S3。該第一側表面23S1可與該第一表面23SU連接。該第一側表面23S1可相對該第一表面23SU形成一銳角。該第二側表面23S2可形成在該第一側表面23S1下方。該第二側表面23S2可具有一與該第一側表面23S1不同之角度。該第二側表面23S2可相對一水平延伸線形成一銳角,且該水平延伸線平行於該基材21且通過該第二表面23S3。該第二槽55之一底部可暴露該第二表面23S3。該第二表面23S3可與該第二側表面23S2連接。該第一表面23SU可解讀為該作用區域23之一上表面。 Referring to FIG. 7B, the second slot 55 can pass through the LDD 43 and the halo 45. The first surface 23SU can be defined on one of the upper ends of the active region 23. For example, the first surface 23SU may be in contact with the buffer layer 31 and extend below the first spacer 42. The second groove 55 may expose the first side surface 23S1, the second side surface 23S2, and the second surface 23S3. The first side surface 23S1 can be coupled to the first surface 23SU. The first side surface 23S1 can form an acute angle with respect to the first surface 23SU. The second side surface 23S2 may be formed below the first side surface 23S1. The second side surface 23S2 may have a different angle from the first side surface 23S1. The second side surface 23S2 can form an acute angle with respect to a horizontally extending line, and the horizontally extending line is parallel to the substrate 21 and passes through the second surface 23S3. The bottom of one of the second grooves 55 may expose the second surface 23S3. The second surface 23S3 is connectable to the second side surface 23S2. The first surface 23SU can be interpreted as one of the upper surfaces of the active area 23.
該第一邊緣E1及該第二邊緣E2可藉由控制該較快蝕刻速度部49之位置而形成在一所欲位置。例如,該第一邊緣E1可形成在該第一分隔件42下方,且該第二邊緣E2可形成為重疊該暫時閘極電極33之一底部。該第一邊緣E1及該第二邊緣E2可位在該LDD43之一表面上。該第一側表面23S1可暴露該LDD43。該第二側表面23S2可暴露該LDD43、該暈圈45及該作用區域23。 The first edge E1 and the second edge E2 can be formed at a desired position by controlling the position of the faster etching speed portion 49. For example, the first edge E1 may be formed under the first spacer 42 and the second edge E2 may be formed to overlap one of the bottoms of the temporary gate electrode 33. The first edge E1 and the second edge E2 may be located on a surface of the LDD 43. The first side surface 23S1 may expose the LDD 43. The second side surface 23S2 can expose the LDD 43, the halo 45, and the active area 23.
在該第二邊緣E2與垂直於該基材21且通過該暫時閘極電極33之一側表面的一直線之間可界定一水平距離X。在該第二邊緣E2與平行於該基材21且通過該第一表面23SU之一直線之間可界定一垂直高度Y。例如,該水平距離X可由0至-5nm,且該垂直高度Y可由3nm至7nm。當該水平距離X為零時,可了解的是該第二邊緣E2被該暫時閘極電極33之側表面垂直地重疊,且當該水平距離X為一負(-)值時,可了解的是該第二邊緣E2被該暫時閘極電極33之底部垂直地重疊。此外,當該水平距離X為一正(+)值時,可了解的是該第二邊緣E2係與該暫時閘極電極33之外側對齊。 A horizontal distance X may be defined between the second edge E2 and a line perpendicular to the substrate 21 and passing through one of the side surfaces of the temporary gate electrode 33. A vertical height Y may be defined between the second edge E2 and a line parallel to the substrate 21 and passing through the first surface 23SU. For example, the horizontal distance X may be from 0 to -5 nm, and the vertical height Y may be from 3 nm to 7 nm. When the horizontal distance X is zero, it can be understood that the second edge E2 is vertically overlapped by the side surface of the temporary gate electrode 33, and when the horizontal distance X is a negative (-) value, it is understood It is the second edge E2 that is vertically overlapped by the bottom of the temporary gate electrode 33. Further, when the horizontal distance X is a positive (+) value, it is understood that the second edge E2 is aligned with the outer side of the temporary gate electrode 33.
藉由調整該較快蝕刻速度部49之位置,可在該基材21之整個表面上均一地控制該水平距離X與該垂直高度Y。在某些實施例中,可相對地減少該垂直高度Y同時增加該水平距離X之絕對值。依據本發明觀念之某些實施例的一半導體裝置可依據該水平距離X及該垂直高度Y具有一良好電氣特性。依據某些實施例,包括位在該LDD43之表面上之該第二邊緣E2的一半導體裝置可顯示良好電氣特性。 By adjusting the position of the faster etching speed portion 49, the horizontal distance X and the vertical height Y can be uniformly controlled over the entire surface of the substrate 21. In some embodiments, the vertical height Y can be relatively reduced while increasing the absolute value of the horizontal distance X. A semiconductor device in accordance with certain embodiments of the inventive concept can have a good electrical characteristic depending on the horizontal distance X and the vertical height Y. In accordance with certain embodiments, a semiconductor device including the second edge E2 on the surface of the LDD 43 can exhibit good electrical characteristics.
請參閱圖7C,在某些實施例中,該較快蝕刻速度部49可被扣持在該第二槽55與該LDD43之間。 Referring to FIG. 7C, in some embodiments, the faster etch rate portion 49 can be held between the second slot 55 and the LDD 43.
請參閱圖1與8A,在該第二槽55中可形成一第一半導體層61(方塊540)。該第一半導體層61可包括藉由一選擇磊晶成長(SEG)法所形成之未摻雜單結晶SiGe。在該第一 半導體層61中之Ge含量可由10至25%。該第一半導體層61可一致地覆蓋該第二槽55之一內壁。該第一半導體層61可以一固定厚度覆蓋該第一側表面23S1及該第二側表面23S2。 Referring to FIGS. 1 and 8A, a first semiconductor layer 61 (block 540) may be formed in the second trench 55. The first semiconductor layer 61 may include undoped single crystal SiGe formed by a selective epitaxial growth (SEG) method. At the first The Ge content in the semiconductor layer 61 may be 10 to 25%. The first semiconductor layer 61 can uniformly cover one of the inner walls of the second groove 55. The first semiconductor layer 61 may cover the first side surface 23S1 and the second side surface 23S2 with a fixed thickness.
請參閱圖8B,一第一半導體層61A可形成為以一固定厚度覆蓋該第二側表面23S2且部份地暴露該第一側表面23S1。 Referring to FIG. 8B, a first semiconductor layer 61A may be formed to cover the second side surface 23S2 with a fixed thickness and partially expose the first side surface 23S1.
請參閱圖8C,一第一半導體層61B可形成為覆蓋該第一側表面23S1及該第二側表面23S2。 Referring to FIG. 8C, a first semiconductor layer 61B may be formed to cover the first side surface 23S1 and the second side surface 23S2.
請參閱圖1與9,在該第二槽55中可形成一第二半導體層62(方塊550)。該第二半導體層62可包括藉由一SEG法所形成之B摻雜單結晶SiGe。在該第二半導體層62中之Ge含量可由25至50%。該第二半導體層62可包含1×1020至3×1020原子/cm3之B。該第二半導體層62可完全填充該第二槽55。該第二半導體層62之一上端可在比該作用區域23高之高度。 Referring to FIGS. 1 and 9, a second semiconductor layer 62 can be formed in the second trench 55 (block 550). The second semiconductor layer 62 may include B-doped single crystal SiGe formed by a SEG method. The Ge content in the second semiconductor layer 62 may be 25 to 50%. The second semiconductor layer 62 may contain B of 1 × 10 20 to 3 × 10 20 atoms/cm 3 . The second semiconductor layer 62 can completely fill the second trench 55. The upper end of one of the second semiconductor layers 62 may be higher than the active region 23.
請參閱圖1與10,在該第二半導體層62上可形成一第三半導體層63(方塊560)。該第三半導體層63可包括藉由該SEG法所形成之B摻雜單結晶矽。在該第三半導體層63可包含1×1020至3×1020原子/cm3之B。該第一半導體層61、該第二半導體層62及該第三半導體層63可形成一埋入應力件65。該埋入應力件65可被稱為一減少應變圖案。在某些實施例中,可省略該第一半導體層61或該第三半導體層63。 Referring to FIGS. 1 and 10, a third semiconductor layer 63 may be formed on the second semiconductor layer 62 (block 560). The third semiconductor layer 63 may include a B-doped single crystal germanium formed by the SEG method. The third semiconductor layer 63 may contain B of 1 × 10 20 to 3 × 10 20 atoms/cm 3 . The first semiconductor layer 61, the second semiconductor layer 62, and the third semiconductor layer 63 may form a buried stress member 65. The buried stress member 65 can be referred to as a reduced strain pattern. In some embodiments, the first semiconductor layer 61 or the third semiconductor layer 63 may be omitted.
請參閱圖1與11,在該基材21上可形成一層間絕緣層71(方塊570)。該層間絕緣層71可包括一絕緣層,例如矽氧化物、矽氮化物、矽氧氮化物或其組合。在某些實施例中,可在形成該層間絕緣層71之前在該第三半導體層63上實施數種另外之程序,例如一金屬矽化物形成程序及一熱處理程序。 Referring to Figures 1 and 11, an interlayer insulating layer 71 may be formed on the substrate 21 (block 570). The interlayer insulating layer 71 may include an insulating layer such as tantalum oxide, tantalum nitride, hafnium oxynitride or a combination thereof. In some embodiments, several additional processes, such as a metal telluride formation process and a heat treatment process, can be performed on the third semiconductor layer 63 prior to forming the interlayer insulating layer 71.
請參閱圖1與12,藉由部份地移除該層間絕緣層71及移除該第二遮罩圖案37與該第一遮罩圖案35,可暴露該暫時閘極電極33。移除該層間絕緣層71、該第二遮罩圖案37及該第一遮罩圖案35可藉由一化學機械拋光(CMP)程序、一深蝕刻程序或其組合實施。 Referring to FIGS. 1 and 12, the temporary gate electrode 33 can be exposed by partially removing the interlayer insulating layer 71 and removing the second mask pattern 37 and the first mask pattern 35. Removing the interlayer insulating layer 71, the second mask pattern 37, and the first mask pattern 35 may be performed by a chemical mechanical polishing (CMP) process, a deep etching process, or a combination thereof.
請參閱圖1與13,藉由移除該暫時閘極電極33及該緩衝層31,可形成一暴露該作用區域23之閘極槽33T。 Referring to FIGS. 1 and 13, by removing the temporary gate electrode 33 and the buffer layer 31, a gate trench 33T exposing the active region 23 can be formed.
請參閱圖1與14A,在該閘極槽33T中可形成一第一閘極介電層73、一第二閘極介電層75、一第一閘極電極77及一第二閘極電極79。 Referring to FIGS. 1 and 14A, a first gate dielectric layer 73, a second gate dielectric layer 75, a first gate electrode 77, and a second gate electrode are formed in the gate trench 33T. 79.
該第一閘極介電層73可形成在該作用區域23上。該第一閘極介電層73可被稱為一界面氧化層。該第一閘極介電層73可藉由一清潔程序形成。該第一閘極介電層73可包括矽氧化物。該第二閘極介電層75可包括矽氧化物、矽氮化物、矽氧氮化物、一高K介電材料或其組合。例如,該第二閘極介電層75可包括HfO或HfSiO。該第二閘極介電層75可包圍該第一閘極電極77之一側及一底部。該第一閘極介電層73可設置在該作用區域23與該第二閘極介電 層75之間。 The first gate dielectric layer 73 can be formed on the active region 23. The first gate dielectric layer 73 can be referred to as an interface oxide layer. The first gate dielectric layer 73 can be formed by a cleaning process. The first gate dielectric layer 73 can include a tantalum oxide. The second gate dielectric layer 75 can comprise tantalum oxide, tantalum nitride, tantalum oxynitride, a high K dielectric material, or a combination thereof. For example, the second gate dielectric layer 75 can include HfO or HfSiO. The second gate dielectric layer 75 can surround one side and a bottom of the first gate electrode 77. The first gate dielectric layer 73 can be disposed on the active region 23 and the second gate dielectric Between layers 75.
該第一閘極電極77可包圍該第二閘極電極79之一側及一底部。該第一閘極電極77可包括藉由考慮一功函數所選擇之一導電材料。例如,該第一閘極電極77可包括TiN或TaN。該第二閘極電極79可包括一金屬層。在某些實施例中,該第一閘極電極77可包括TiAl或TiAlC。 The first gate electrode 77 can surround one side and a bottom of the second gate electrode 79. The first gate electrode 77 can include a conductive material selected by considering a work function. For example, the first gate electrode 77 may include TiN or TaN. The second gate electrode 79 can include a metal layer. In some embodiments, the first gate electrode 77 can comprise TiAl or TiAlC.
請參閱圖14B,該埋入應力件65可通過該LDD43及該暈圈45而與該作用區域23接觸。該埋入應力件65之一底部可形成在一比該暈圈45低之高度。該埋入應力件65可與該第一側表面23S1及該第二側表面23S2接觸。該第一半導體層61可設置在該LDD43與該第二半導體層62之間。 Referring to FIG. 14B, the embedding stress member 65 can be in contact with the active region 23 through the LDD 43 and the halo 45. The bottom of one of the buried stress members 65 may be formed at a lower height than the halo 45. The buried stress member 65 is in contact with the first side surface 23S1 and the second side surface 23S2. The first semiconductor layer 61 may be disposed between the LDD 43 and the second semiconductor layer 62.
在該第二半導體層62中之第一導電性型雜質之濃度可比在該LDD43中之第一導電性型雜質之濃度高。例如,在該第二半導體層62中之一硼(B)濃度可比在該LDD43中之硼濃度高。在該第二半導體層62中之第一導電性型雜質可擴散進入該第一半導體層61。在該第一半導體層61中之硼(B)濃度可比在第二半導體層62中之硼濃度低。 The concentration of the first conductivity type impurity in the second semiconductor layer 62 may be higher than the concentration of the first conductivity type impurity in the LDD 43. For example, one boron (B) concentration in the second semiconductor layer 62 may be higher than the boron concentration in the LDD 43. The first conductivity type impurity in the second semiconductor layer 62 may diffuse into the first semiconductor layer 61. The boron (B) concentration in the first semiconductor layer 61 may be lower than the boron concentration in the second semiconductor layer 62.
植入該較快蝕刻速度部49(例如,如圖4A所示)之磷(P)可擴散進入該LDD43。該LDD43可包含磷及硼。例如,該LDD43可包含5×1018至1×1019原子/cm3之磷。當將磷植入該較快蝕刻速度部49時,該磷會留在該第二分隔件47、該第一分隔件42及其一界面中。該磷可留在該第三分隔件51及在該第三分隔件51與該第二分隔件47之間的一 界面中。該磷可留在該埋入應力件65及在該埋入應力件65與該等第一、第二及第三分隔件42、47、51之間的界面中。在某些實施例中,該磷亦可留在該LDD43中及在該LDD43與該等第一、第二及第三分隔件42、47、51的界面之間。 Phosphorus (P) implanted into the faster etch rate portion 49 (e.g., as shown in Figure 4A) can diffuse into the LDD 43. The LDD 43 can comprise phosphorus and boron. For example, the LDD 43 may contain 5 x 10 18 to 1 x 10 19 atoms/cm 3 of phosphorus. When phosphorus is implanted into the faster etch rate portion 49, the phosphorus will remain in the second spacer 47, the first spacer 42, and an interface thereof. The phosphorus may remain in the third partition 51 and in an interface between the third partition 51 and the second partition 47. The phosphorus may remain in the buried stressor 65 and in the interface between the embedded stressor 65 and the first, second and third dividers 42, 47, 51. In some embodiments, the phosphorus may also remain in the LDD 43 and between the LDD 43 and the interfaces of the first, second, and third dividers 42, 47, 51.
請參閱圖14C,該埋入應力件65可藉由調整該第二分隔件47A之厚度形成具有一所欲水平寬度。例如,該埋入應力件65可形成在該第一閘極電極77之一外側。 Referring to FIG. 14C, the embedding stress member 65 can be formed to have a desired horizontal width by adjusting the thickness of the second spacer 47A. For example, the buried stressor 65 may be formed outside one of the first gate electrodes 77.
請參閱圖14D,該埋入應力件65之底部可位在該暈圈45中。 Referring to FIG. 14D, the bottom of the buried stress member 65 can be positioned in the halo 45.
請參閱圖14E,一埋入應力件65A可包括一第一半導體層61A、該第二半導體層62及該第三半導體層63。該第一半導體層61A可形成為以一固定厚度覆蓋該第二側表面23S2及部份地暴露該第一側表面23S1。該第二半導體層62可與該第一側表面23S1接觸。 Referring to FIG. 14E, a buried stress member 65A may include a first semiconductor layer 61A, the second semiconductor layer 62, and the third semiconductor layer 63. The first semiconductor layer 61A may be formed to cover the second side surface 23S2 with a fixed thickness and partially expose the first side surface 23S1. The second semiconductor layer 62 is in contact with the first side surface 23S1.
請參閱圖14F,一埋入應力件65B可包括一第一半導體層61B、該第二半導體層62及該第三半導體層63。該第一半導體層61B可形成為覆蓋該第一側表面23S1及該第二側表面23S2。該第一半導體層61B可形成在該LDD43與該第二半導體層62之間。 Referring to FIG. 14F, a buried stress member 65B may include a first semiconductor layer 61B, the second semiconductor layer 62, and the third semiconductor layer 63. The first semiconductor layer 61B may be formed to cover the first side surface 23S1 and the second side surface 23S2. The first semiconductor layer 61B may be formed between the LDD 43 and the second semiconductor layer 62.
請參閱圖14G,該較快蝕刻速度部49可被扣持在該埋入應力件65與該LDD43之間。 Referring to FIG. 14G, the faster etch rate portion 49 can be held between the buried stress member 65 and the LDD 43.
圖15係橫截面圖,顯示在形成依據本發明觀念之某些實施例之一半導體裝置的操作中所提供之一中間結構。請參閱圖15,在該基材21上可形成一井部22、一作用 區域23、一裝置隔離層29、一閘極介電層131、一第一閘極電極133、一第二閘極電極181、一內分隔件134、一第一分隔件142、一輕摻雜汲極(LDD)43、一暈圈45、一第二分隔件147、一第三分隔件151、一埋入應力件65、一蝕刻停止層183及一層間絕緣層185。該閘極介電層131及該第一閘極電極133可在形成該埋入應力件65之前形成。 Figure 15 is a cross-sectional view showing an intermediate structure provided in the operation of forming a semiconductor device in accordance with some embodiments of the present inventive concept. Referring to FIG. 15, a well 22 can be formed on the substrate 21, and a function is formed. The region 23, a device isolation layer 29, a gate dielectric layer 131, a first gate electrode 133, a second gate electrode 181, an inner spacer 134, a first spacer 142, and a lightly doped region A drain (LDD) 43, a halo 45, a second spacer 147, a third spacer 151, a buried stress member 65, an etch stop layer 183, and an interlayer insulating layer 185. The gate dielectric layer 131 and the first gate electrode 133 may be formed before the buried stressor 65 is formed.
該閘極介電層131可包括矽氧化物、矽氮化物、矽氧氮化物、一高K介電層或其組合。該第一閘極電極133可包括一導電層,例如多晶矽、一金屬矽化物、一金屬或其組合。該第二閘極電極181可包括一導電層,例如一金屬矽化物、一金屬或其組合。該內分隔件134可包括矽氧化物、矽氮化物、矽氧氮化物或其組合。該蝕刻停止層183可包括相對該層間絕緣層185具有一蝕刻選擇性之一材料。例如,該層間絕緣層185可包括矽氧化物,且該蝕刻停止層183可包括矽氮化物。 The gate dielectric layer 131 can include tantalum oxide, tantalum nitride, tantalum oxynitride, a high-k dielectric layer, or a combination thereof. The first gate electrode 133 may include a conductive layer such as polysilicon, a metal halide, a metal, or a combination thereof. The second gate electrode 181 can include a conductive layer, such as a metal halide, a metal, or a combination thereof. The inner spacer 134 may include tantalum oxide, tantalum nitride, tantalum oxynitride, or a combination thereof. The etch stop layer 183 can include a material having an etch selectivity with respect to the interlayer insulating layer 185. For example, the interlayer insulating layer 185 may include tantalum oxide, and the etch stop layer 183 may include tantalum nitride.
圖16係依據本發明觀念之某些實施例之一半導體裝置的一配置。圖17至24、25A至25C、26至30與31A至31C係沿圖16之線I-I'與II-II'所截取之橫截面圖,顯示在形成依據本發明觀念之某些實施例之一半導體裝置的操作中所提供之中間結構。 16 is a diagram of a configuration of a semiconductor device in accordance with some embodiments of the inventive concept. 17 to 24, 25A to 25C, 26 to 30, and 31A to 31C are cross-sectional views taken along lines I-I' and II-II' of Fig. 16, and are shown in some embodiments for forming the concept according to the present invention. An intermediate structure provided in the operation of one of the semiconductor devices.
請參閱圖16與17,在一基材221上可形成界定一作用區域223之一裝置隔離層229。該作用區域223之一上表面可被一緩衝層225覆蓋。該作用區域223可具有各種形成,例如翼形或線形。例如,該作用區域223可包括主軸形 成為比較長之一翼形單結晶矽。 Referring to FIGS. 16 and 17, a device isolation layer 229 defining an active region 223 may be formed on a substrate 221. One of the upper surfaces of the active region 223 may be covered by a buffer layer 225. The active area 223 can have various formations, such as a wing or a line. For example, the active area 223 can include a major axis Become a relatively long wing-shaped single crystal 矽.
請參閱圖16與18,在該基材221之一預定區域中可形成一井部222。該作用區域223可局限於該井部222。多數通道離子可植入該作用區域223中。藉由植入具有一與該基材221中之雜質之導電性型不同之導電性型的雜質,可形成該井部222。例如,藉由植入n型雜質至由該基材221之表面的一預定深度,可形成該井部222。在某些實施例中,可在形成該裝置隔離層229之前形成該井部222。在某些實施例中,可省略該井部222。 Referring to Figures 16 and 18, a well 222 may be formed in a predetermined region of the substrate 221. The active area 223 can be limited to the well 222. Most of the channel ions can be implanted in the active region 223. The well portion 222 can be formed by implanting an electrically conductive type impurity having a conductivity type different from that of the impurity in the substrate 221. The well portion 222 can be formed, for example, by implanting an n-type impurity to a predetermined depth from the surface of the substrate 221. In some embodiments, the well 222 can be formed prior to forming the device isolation layer 229. In some embodiments, the well 222 can be omitted.
請參閱圖16與19,藉由使該裝置隔離層229凹陷,可暴露該作用區域223之側表面。該裝置隔離層229可被扣持在比該作用區域223之一上端低之高度。當使該裝置隔離層229凹陷時,亦可移除該緩衝層225。可暴露該作用區域223之上表面。在該裝置隔離層229之凹處中可實施一深蝕刻程序。 Referring to FIGS. 16 and 19, the side surface of the active region 223 may be exposed by recessing the device isolation layer 229. The device isolation layer 229 can be held at a lower height than the upper end of one of the active regions 223. The buffer layer 225 can also be removed when the device isolation layer 229 is recessed. The upper surface of the active region 223 may be exposed. A deep etch process can be performed in the recess of the device isolation layer 229.
請參閱圖16與20,在該作用區域223上可形成一暫時閘極介電層231、一暫時閘極電極233、一第一遮罩圖案235及一第二遮罩圖案237。藉由一薄膜形成程序、一CMP程序及一圖案化程序,可形成該暫時閘極電極233。 Referring to FIGS. 16 and 20, a temporary gate dielectric layer 231, a temporary gate electrode 233, a first mask pattern 235, and a second mask pattern 237 are formed on the active region 223. The temporary gate electrode 233 can be formed by a thin film forming process, a CMP process, and a patterning process.
該暫時閘極電極233可形成為橫越該作用區域223。該暫時閘極電極233可覆蓋該作用區域223之側及上表面。該暫時閘極介電層231可形成在該作用區域223與該暫時閘極電極233之間。該暫時閘極介電層231可包括一絕緣層,例如矽氧化物、矽氮化物、矽氧氮化物或其組合。該 暫時閘極電極233可包括多晶矽。該第一遮罩圖案235矽氧化物。該第二遮罩圖案237可包括矽氮化物。 The temporary gate electrode 233 may be formed to traverse the active region 223. The temporary gate electrode 233 can cover the side and the upper surface of the active region 223. The temporary gate dielectric layer 231 may be formed between the active region 223 and the temporary gate electrode 233. The temporary gate dielectric layer 231 can include an insulating layer such as tantalum oxide, tantalum nitride, tantalum oxynitride or a combination thereof. The The temporary gate electrode 233 may include polysilicon. The first mask pattern 235 is an oxide. The second mask pattern 237 can include tantalum nitride.
請參閱圖16與21,在該暫時閘極電極233之側表面上可形成一第一分隔件242。在該作用區域223亦可形成一輕摻雜汲極(LDD)243及一暈圈245。該第一分隔件242可覆蓋該暫時閘極電極233、該第一遮罩圖案235及該第二遮罩圖案237之側表面。該第一分隔件242可包括一絕緣層,例如矽氧化物、矽氮化物、矽氧氮化物或其組合。例如,該第一分隔件242可為矽氮化物。 Referring to FIGS. 16 and 21, a first spacer 242 may be formed on a side surface of the temporary gate electrode 233. A lightly doped drain (LDD) 243 and a halo 245 may also be formed in the active region 223. The first spacer 242 can cover the side surfaces of the temporary gate electrode 233, the first mask pattern 235, and the second mask pattern 237. The first spacer 242 may include an insulating layer such as tantalum oxide, tantalum nitride, tantalum oxynitride or a combination thereof. For example, the first spacer 242 can be tantalum nitride.
使用該第二遮罩圖案237及該第一分隔件242作為一離子植入遮罩,可形成該LDD243及該暈圈245。在該作用區域223中可形成與該暫時閘極電極233之一外側相鄰的該LDD243。該LDD243可包括具有與該井部222中之雜質之導電性型不同之一導電性型。例如,該LDD247可包括p型雜質。該LDD243可包括硼。 The LDD 243 and the halo 245 can be formed by using the second mask pattern 237 and the first spacer 242 as an ion implantation mask. The LDD 243 adjacent to one of the outer sides of the temporary gate electrode 233 may be formed in the active region 223. The LDD 243 can include a conductivity type that is different from the conductivity type of the impurities in the well 222. For example, the LDD 247 can include a p-type impurity. The LDD 243 can include boron.
該暈圈245可形成在該LDD243外側。該暈圈245可覆蓋該LDD243之一底及側表面。該暈圈245可具有與該LDD243中之雜質之導電性型不同的一導電性型,且該暈圈245可包括具有與該井部222中之雜質之導電性型相同的一導電性型。該暈圈245之n型雜質的濃度可比該井部222之n型雜質的濃度高。 The halo 245 can be formed outside of the LDD 243. The halo 245 can cover one of the bottom and side surfaces of the LDD 243. The halo 245 may have a conductivity type different from the conductivity type of the impurities in the LDD 243, and the halo 245 may include a conductivity type having the same conductivity type as the impurities in the well 222. The concentration of the n-type impurity of the halo 245 may be higher than the concentration of the n-type impurity of the well 222.
請參閱圖16與22,在該第一分隔件242上可形成一第二分隔件247。使用該第二分隔件247作為一離子植入遮罩,可在該作用區域223中形成一較快蝕刻速度部249。 該第二分隔件247可一致地覆蓋該基材221。該第二分隔件247可包括相對該暫時閘極電極233具有一蝕刻選擇性之一材料。例如,該第二分隔件247可包括矽氮化物。 Referring to FIGS. 16 and 22, a second spacer 247 may be formed on the first spacer 242. Using the second spacer 247 as an ion implantation mask, a faster etch rate portion 249 can be formed in the active region 223. The second spacer 247 can uniformly cover the substrate 221. The second spacer 247 can include a material having an etch selectivity with respect to the temporary gate electrode 233. For example, the second spacer 247 can include tantalum nitride.
藉由調整該第二分隔件247之厚度,可在一所欲位置形成該較快蝕刻速度部249。該較快蝕刻速度部249可形成在該LDD243中。該較快蝕刻速度部249之一底部可形成在比該LDD243之一底部高之高度。該較快蝕刻速度部249可形成與該暫時閘極電極233之一外側對齊。該作用區域223可被扣持在該暫時閘極電極233下方。該LDD243可被扣持在該暫時閘極電極233下方。該LDD243可被扣持在該較快蝕刻速度部249與該作用區域223之間。 By adjusting the thickness of the second spacer 247, the faster etch rate portion 249 can be formed at a desired position. The faster etch rate portion 249 can be formed in the LDD 243. The bottom of one of the faster etching speed portions 249 may be formed at a height higher than the bottom of one of the LDDs 243. The faster etch rate portion 249 may be formed to be aligned with one of the outer sides of the temporary gate electrode 233. The active region 223 can be held under the temporary gate electrode 233. The LDD 243 can be held under the temporary gate electrode 233. The LDD 243 can be held between the faster etch rate portion 249 and the active region 223.
請參閱圖16與23,一第三分隔件251可形成在該第二分隔件247上。該第三分隔件251之形成可包括一薄膜形成程序及一異向蝕刻程序。在形成該第三分隔件251時,可部份地移除該第二分隔件247及該第一分隔件242以暴露該較快蝕刻速度部249之一上表面。該第二分隔件247及該第一分隔件242可被扣持在該暫時閘極圖案233與該第三分隔件251之間。 Referring to FIGS. 16 and 23, a third spacer 251 may be formed on the second spacer 247. The formation of the third spacer 251 may include a thin film forming process and an anisotropic etching process. When the third spacer 251 is formed, the second spacer 247 and the first spacer 242 may be partially removed to expose an upper surface of the faster etching speed portion 249. The second spacer 247 and the first spacer 242 can be fastened between the temporary gate pattern 233 and the third spacer 251.
請參閱圖16與24,藉由蝕刻該較快蝕刻速度部249及該LDD243,可形成一第一槽253。該第一槽253可包括與該較快蝕刻速度部249對齊之一上槽253A及與該上槽253A之一底部連接的一下槽253B。該上槽253A可形成在該LDD243中。藉由該上槽253A,一底切可形成在該第一分隔件242、該第二分隔件247及該第三分隔件251下 方。該第一槽253之一側壁可具有一階部。例如,藉由該上槽253A及下槽253B暴露之該LDD243的側表面可具有該階部。 Referring to FIGS. 16 and 24, a first trench 253 can be formed by etching the faster etch rate portion 249 and the LDD 243. The first slot 253 can include an upper slot 253A aligned with the faster etch rate portion 249 and a lower slot 253B coupled to one of the upper slots 253A. The upper groove 253A may be formed in the LDD 243. An undercut can be formed under the first spacer 242, the second spacer 247, and the third spacer 251 by the upper slot 253A. square. One of the side walls of the first groove 253 may have a first step. For example, the side surface of the LDD 243 exposed by the upper groove 253A and the lower groove 253B may have the step.
該第一槽253之形成可包括一乾式蝕刻程序,一濕式蝕刻程序或其組合。該第一槽253之形成可包括一等向蝕刻程序,一異向蝕刻程序或其組合。例如,該第一槽253之形成可包括使用HBr、CF4、O2、Cl2、NF3或其組合之一等向乾式蝕刻程序。依據某些實施例,在該較快蝕刻速度部49中可包括具有比包括硼之單晶矽之蝕刻速度高之一蝕刻速度的包括磷之單晶矽,且因此該較快蝕刻速度部249可具有比該LDD243之蝕刻速度高之一蝕刻速度。依據該較快蝕刻速度部249及該LDD243之構態,可決定該上槽253A及下槽253B之尺寸及形狀。 The formation of the first trench 253 can include a dry etch process, a wet etch process, or a combination thereof. The formation of the first trench 253 can include an isotropic etch process, an anisotropic etch process, or a combination thereof. For example, the first groove 253 may include the use of HBr, CF 4, O 2, Cl, NF 23 like one or a combination of the dry etching process. According to some embodiments, a single crystal germanium including phosphorus having an etching rate higher than an etching rate of a single crystal germanium including boron may be included in the faster etching speed portion 49, and thus the faster etching speed portion 249 There may be one etch rate higher than the etch rate of the LDD 243. The size and shape of the upper groove 253A and the lower groove 253B can be determined according to the configuration of the faster etching rate portion 249 and the LDD 243.
請參閱圖16與25A,可使用一方向性蝕刻程序形成一第二槽255。例如,該第二槽255之形成可包括一使用NH4OH、NH3OH、TMAH(四甲基氫氧化銨)、KOH、NaOH、BTMH(苄基三甲基氫氧化銨)或其組合之濕式蝕刻。依據該作用區域223之晶體取向,該方向性蝕刻程序可具有不同蝕刻速度。該第二槽255可通過該LDD243。該LDD243可被扣持在該第二槽255與該作用區域223之間。 Referring to Figures 16 and 25A, a second trench 255 can be formed using a directional etch process. For example, the formation of the second tank 255 may include using NH 4 OH, NH 3 OH, TMAH (tetramethylammonium hydroxide), KOH, NaOH, BTMH (benzyltrimethylammonium hydroxide) or a combination thereof. Wet etching. Depending on the crystal orientation of the active region 223, the directional etch process can have different etch rates. The second slot 255 can pass through the LDD 243. The LDD 243 can be held between the second slot 255 and the active area 223.
該作用區域223可包括一第一側表面223S1、一第二側表面223S2、一第三側表面223S3及一第二表面223S4。該第一側表面223S1、該第二側表面223S2及該第三側表面223S3之各側表面可包括一{111}晶面。該 第一表面223SU可形成在該作用區域223之上端。該第一側表面223S1可與該第一表面223SU連接。該第一側表面223S1可相對該第一表面223SU形成一銳角。該第二側表面223S2可形成在該第一側表面223S1下方。該第二側表面223S2可具有一與該第一側表面223S1之斜率不同的斜率。該第二側表面223S2可與該基材221垂直。該第三側表面223S3可形成在該第二側表面223S2下方。該第三側表面223S3可具有一與該第二側表面223S2之斜率不同的斜率。該第二槽255之一底部可暴露該第二表面223S4。該第二表面223S4可與該第三側表面223S3連接。 The active area 223 can include a first side surface 223S1, a second side surface 223S2, a third side surface 223S3, and a second surface 223S4. The side surfaces of the first side surface 223S1, the second side surface 223S2, and the third side surface 223S3 may include a {111} crystal plane. The The first surface 223SU may be formed at an upper end of the active region 223. The first side surface 223S1 can be coupled to the first surface 223SU. The first side surface 223S1 can form an acute angle with respect to the first surface 223SU. The second side surface 223S2 may be formed below the first side surface 223S1. The second side surface 223S2 may have a slope different from the slope of the first side surface 223S1. The second side surface 223S2 may be perpendicular to the substrate 221 . The third side surface 223S3 may be formed below the second side surface 223S2. The third side surface 223S3 may have a slope different from the slope of the second side surface 223S2. The bottom of one of the second slots 255 may expose the second surface 223S4. The second surface 223S4 can be coupled to the third side surface 223S3.
請參閱圖25B,依據該作用區域223之晶體取向,一第二槽255A可形成各種形狀。例如,該第二槽255A可呈一U形。該第二槽255A可暴露一第一側表面223S5及該第二表面223S4。該第一側表面223S5可與該第一表面223SU連接。該第一側表面223S5可與該第一表面223SU垂直。該第二槽255A可暴露該第二表面223S4。該第二表面223S4可與該第一側表面223S5連接。 Referring to FIG. 25B, a second groove 255A may be formed in various shapes depending on the crystal orientation of the active region 223. For example, the second slot 255A can have a U shape. The second groove 255A can expose a first side surface 223S5 and the second surface 223S4. The first side surface 223S5 can be coupled to the first surface 223SU. The first side surface 223S5 may be perpendicular to the first surface 223SU. The second groove 255A can expose the second surface 223S4. The second surface 223S4 can be coupled to the first side surface 223S5.
請參閱圖25C,該第二槽255B可暴露該第一側表面223S1、該第二側表面223S2及該第二表面223S4。該第一側表面223S1可與該第一表面223SU連接。該第一側表面223S1可相對該第一表面223SU形成一銳角。該第二側表面223S2可形成在該第一側表面223S1下方。該第二槽255B之底部可暴露該第二表面223S4。該第二表面223S4可與該第二側表面223S2連接。 Referring to FIG. 25C, the second groove 255B may expose the first side surface 223S1, the second side surface 223S2, and the second surface 223S4. The first side surface 223S1 can be coupled to the first surface 223SU. The first side surface 223S1 can form an acute angle with respect to the first surface 223SU. The second side surface 223S2 may be formed below the first side surface 223S1. The bottom of the second groove 255B may expose the second surface 223S4. The second surface 223S4 can be coupled to the second side surface 223S2.
請參閱圖16與26,在該第二槽255中可形成一第二半導體層262。該第二半導體層262可包括藉由一SEG法所形成之B摻雜單結晶SiGe。在該第二半導體層262中之Ge含量可為25至50%。該第二半導體層262可包含1×1020至3×1020原子/cm3之(B)。該第二半導體層262可完全填充該第二槽255。該第二半導體層262之一上端可在比該作用區域223高之高度。 Referring to FIGS. 16 and 26, a second semiconductor layer 262 may be formed in the second trench 255. The second semiconductor layer 262 may include B-doped single crystal SiGe formed by a SEG method. The Ge content in the second semiconductor layer 262 may be 25 to 50%. The second semiconductor layer 262 may include (B) of 1 × 10 20 to 3 × 10 20 atoms/cm 3 . The second semiconductor layer 262 can completely fill the second trench 255. The upper end of one of the second semiconductor layers 262 may be higher than the active region 223.
請參閱圖16與27,在該第二半導體層262上可形成一第三半導體層263。該第三半導體層263可包括藉由一SEG法所形成之B摻雜單結晶Si。在該第三半導體層263可包含1×1020至3×1020原子/cm3之(B)。該第二半導體層262及該第三半導體層263可形成一埋入應力件265。在某些實施例中,可省略該第三半導體層263。 Referring to FIGS. 16 and 27, a third semiconductor layer 263 may be formed on the second semiconductor layer 262. The third semiconductor layer 263 may include B-doped single crystal Si formed by a SEG method. The third semiconductor layer 263 may contain 1 × 10 20 to 3 × 10 20 atoms/cm 3 (B). The second semiconductor layer 262 and the third semiconductor layer 263 may form a buried stress member 265. In some embodiments, the third semiconductor layer 263 can be omitted.
請參閱圖16與28,在該基材221上可形成一層間絕緣層271。 Referring to FIGS. 16 and 28, an interlayer insulating layer 271 may be formed on the substrate 221.
請參閱圖16與29,藉由部份地移除該層間絕緣層271及移除該第二遮罩圖案237與該第一遮罩圖案235,可暴露該暫時閘極電極233。 Referring to FIGS. 16 and 29, the temporary gate electrode 233 may be exposed by partially removing the interlayer insulating layer 271 and removing the second mask pattern 237 and the first mask pattern 235.
請參閱圖16與30,移除該暫時閘極電極233及該暫時閘極介電層231以形成一暴露該作用區域223之閘極槽233T。 Referring to FIGS. 16 and 30, the temporary gate electrode 233 and the temporary gate dielectric layer 231 are removed to form a gate trench 233T exposing the active region 223.
請參閱圖16與31A,在該閘極槽233T中可形成一第一閘極介電層273、一第二閘極介電層275及一閘極電極279。該埋入應力件265可具有一楔形。 Referring to FIGS. 16 and 31A, a first gate dielectric layer 273, a second gate dielectric layer 275, and a gate electrode 279 are formed in the gate trench 233T. The buried stress member 265 can have a wedge shape.
該第一閘極介電層273可形成在該作用區域223上。該第一閘極介電層273可被稱為一界面氧化層。該第一閘極介電層273可藉由一清潔程序形成。該第一閘極介電層273可包括矽氧化物。該第二閘極介電層275可包括矽氧化物、矽氮化物、矽氧氮化物、一高K介電層或其組合。該第二閘極介電層275可包圍該閘極電極279之一側及一底部。該第一閘極介電層273可設置在該作用區域223與該第二閘極介電層275之間。 The first gate dielectric layer 273 may be formed on the active region 223. The first gate dielectric layer 273 can be referred to as an interface oxide layer. The first gate dielectric layer 273 can be formed by a cleaning process. The first gate dielectric layer 273 can include tantalum oxide. The second gate dielectric layer 275 can include tantalum oxide, tantalum nitride, tantalum oxynitride, a high-k dielectric layer, or a combination thereof. The second gate dielectric layer 275 can surround one side of the gate electrode 279 and a bottom. The first gate dielectric layer 273 can be disposed between the active region 223 and the second gate dielectric layer 275.
請參閱圖31B,該埋入應力件265可包括一第二半導體層262A及一第三半導體層263。該埋入應力件265可呈一U形。 Referring to FIG. 31B, the buried stressor 265 may include a second semiconductor layer 262A and a third semiconductor layer 263. The embedded stress member 265 can have a U shape.
請參閱圖31C,該埋入應力件265可包括一第二半導體層262B及一第三半導體層263。該埋入應力件265可呈一角錐形或一鉛筆形。 Referring to FIG. 31C, the buried stress member 265 may include a second semiconductor layer 262B and a third semiconductor layer 263. The embedding stress member 265 may have a pyramid shape or a pencil shape.
圖32係依據本發明觀念之某些實施例之一半導體裝置的一配置。圖33至38係橫截面圖,顯示在形成依據本發明觀念之某些實施例之一半導體裝置的操作中所提供之中間結構。 32 is a configuration of a semiconductor device in accordance with some embodiments of the inventive concept. Figures 33 through 38 are cross-sectional views showing intermediate structures provided in the operation of forming a semiconductor device in accordance with certain embodiments of the present teachings.
請參閱圖32,一半導體晶片100可包括一第一區域102及一第二區域101C。該第一區域102可被稱為一邏輯區域。該第二區域101C可被稱為一晶胞陣列區域。在該第一區域102及該第二區域101C中可形成多數PMOS電晶體。該第二區域101C可具有一比該第一區域102之圖案密度高之圖案密度。 Referring to FIG. 32, a semiconductor wafer 100 can include a first region 102 and a second region 101C. The first region 102 can be referred to as a logical region. The second region 101C may be referred to as a cell array region. A plurality of PMOS transistors can be formed in the first region 102 and the second region 101C. The second region 101C can have a pattern density that is higher than the pattern density of the first region 102.
該半導體晶片100可為一微處理器。該半導體晶片100可包括一記憶體區域101。該記憶體區域101可包括該第二區域101C及一SRAM周邊區域101P。該第二區域101C可包括記憶體晶胞,例如一SRAM。該第一區域102可形成為與該記憶體區域101相鄰。 The semiconductor wafer 100 can be a microprocessor. The semiconductor wafer 100 can include a memory region 101. The memory region 101 can include the second region 101C and an SRAM peripheral region 101P. The second region 101C can include a memory cell, such as an SRAM. The first region 102 may be formed adjacent to the memory region 101.
請參閱圖32與33,在一基材21之該第一區域102中可形成一第一井部22、一第一作用區域23、一第一裝置隔離層29、一第一緩衝層31、一第一暫時閘極電極33、一第一下遮罩圖案35及一第一上遮罩圖案37。該基材21可包括第一導電性型雜質。該第一井部22可包括與該第一導電性型雜質不同之第二導電性型雜質。以下,將在該第一導電性係p型且該第二導電係n型之假設下進行說明。 Referring to FIGS. 32 and 33, a first well 22, a first active region 23, a first device isolation layer 29, a first buffer layer 31, and a first region 22 may be formed in the first region 102 of the substrate 21. A first temporary gate electrode 33, a first lower mask pattern 35 and a first upper mask pattern 37. The substrate 21 may include a first conductive type impurity. The first well portion 22 may include a second conductivity type impurity different from the first conductivity type impurity. Hereinafter, the first conductivity type p-type and the second conductivity type n type will be described.
該第一作用區域23可藉由該第一裝置隔離層29局限於該第一井部22。該第一暫時閘極電極33可形成為橫越該第一作用區域23。該第一上遮罩圖案37、該第一下遮罩圖案35、該第一暫時閘極電極33及該第一緩衝層31可被稱為一第一暫時閘極圖案31、33、35與37。第一暫時閘極圖案31、33、35與37可橫越該第一作用區域23。多數該等第一暫時閘極圖案31、33、35與37可平行地形成在該第一作用區域23上。 The first active region 23 can be limited to the first well 22 by the first device isolation layer 29. The first temporary gate electrode 33 may be formed to traverse the first active region 23. The first upper mask pattern 37, the first lower mask pattern 35, the first temporary gate electrode 33, and the first buffer layer 31 may be referred to as a first temporary gate pattern 31, 33, 35 and 37. The first temporary gate patterns 31, 33, 35 and 37 may traverse the first active region 23. Most of the first temporary gate patterns 31, 33, 35 and 37 may be formed in parallel on the first active region 23.
在該第一暫時閘極電極33之一側壁上可形成一第一內分隔件42。藉由使用該第一內分隔件42、該第一上遮罩圖案37、該第一下遮罩圖案35及該第一暫時閘極電極33作為一離子植入遮罩在該第一作用區域23中植入該等 第一導電性型雜質,可形成一第一LDD43。藉由在該第一作用區域23中植入該等第二導電性型雜質,可形成一第一暈圈45。該第一暈圈45可覆蓋該第一LDD43之一側及一底部。該第一LDD43及該第一暈圈45之形成可包括一離子植入程序及一熱處理程序。 A first inner spacer 42 may be formed on one side wall of the first temporary gate electrode 33. By using the first inner spacer 42 , the first upper mask pattern 37 , the first lower mask pattern 35 and the first temporary gate electrode 33 as an ion implantation mask in the first active region Implanted in 23 The first conductive type impurity can form a first LDD 43. A first halo 45 can be formed by implanting the second conductivity type impurities in the first active region 23. The first halo 45 can cover one side and a bottom of the first LDD 43. The formation of the first LDD 43 and the first halo 45 may include an ion implantation process and a heat treatment process.
在該第一內分隔件42上可形成一第一中間分隔件47。使用該第一中間分隔件47作為一離子植入遮罩在該第一作用區域23中形成一第一較快蝕刻速度部49。在該第一中間分隔件47上可形成一第一外分隔件51。該第一外分隔件51之形成可包括一薄膜形成程序及一異向蝕刻程序。可暴露該第一較快蝕刻速度部49之一上表面。 A first intermediate partition 47 may be formed on the first inner partition 42. A first faster etch rate portion 49 is formed in the first active region 23 using the first intermediate spacer 47 as an ion implantation mask. A first outer spacer 51 may be formed on the first intermediate partition 47. The formation of the first outer spacer 51 may include a film forming process and an anisotropic etching process. One of the upper surfaces of the first faster etch rate portion 49 may be exposed.
在該基材21之第二區域101C中可形成一第二井部322、一第二作用區域323、一第二裝置隔離層329、一第二緩衝層331、一第二暫時閘極電極333、一第二下遮罩圖案335及一第二上遮罩圖案337。該第二井部322可包括第二導電性型雜質。 A second well portion 322, a second active region 323, a second device isolation layer 329, a second buffer layer 331, and a second temporary gate electrode 333 may be formed in the second region 101C of the substrate 21. a second lower mask pattern 335 and a second upper mask pattern 337. The second well portion 322 can include a second conductivity type impurity.
該第二作用區域323可藉由該第二裝置隔離層329局限於該第二井部322。該第二暫時閘極電極333可形成為橫越該第二作用區域323。該第二上遮罩圖案337、該第二下遮罩圖案335、該第二暫時閘極電極333及該第二緩衝層331可被稱為一第二暫時閘極圖案331、333、335與337。第二暫時閘極圖案331、333、335與337可橫越該第二作用區域323。多數該等第二暫時閘極圖案331、333、335與337可平行地形成在該第二作用區域323上。 The second active region 323 can be limited to the second well 322 by the second device isolation layer 329. The second temporary gate electrode 333 may be formed to traverse the second active region 323. The second upper mask pattern 337, the second lower mask pattern 335, the second temporary gate electrode 333, and the second buffer layer 331 may be referred to as a second temporary gate pattern 331, 333, 335 and 337. The second temporary gate patterns 331, 333, 335, and 337 may traverse the second active region 323. Most of the second temporary gate patterns 331, 333, 335 and 337 may be formed in parallel on the second active region 323.
在該第二暫時閘極電極333之一側壁上可形成一第二內分隔件342。藉由使用該第二內分隔件342、該第二上遮罩圖案337、該第二下遮罩圖案335及該第二暫時閘極電極333作為一離子植入遮罩在該第二作用區域323中植入該等第一導電性型雜質,可形成一第二LDD343。藉由在該第二作用區域323中植入該等第二導電性型雜質,可形成一第二暈圈345。該第二暈圈345可覆蓋該第二LDD343之一側及一底部。該第二LDD343及該第二暈圈345之形成可包括一離子植入程序及一熱處理程序。 A second inner spacer 342 may be formed on one sidewall of the second temporary gate electrode 333. The second inner spacer 342, the second upper mask pattern 337, the second lower mask pattern 335 and the second temporary gate electrode 333 are used as an ion implantation mask in the second active region. The first conductivity type impurities are implanted in 323 to form a second LDD 343. A second halo 345 can be formed by implanting the second conductive type impurities in the second active region 323. The second halo 345 can cover one side and a bottom of the second LDD 343. The formation of the second LDD 343 and the second halo 345 may include an ion implantation process and a heat treatment process.
在該第二內分隔件342上可形成一第二中間分隔件347。使用該第二中間分隔件347作為一離子植入遮罩在該第二作用區域323中形成一第二較快蝕刻速度部349。在該第二中間分隔件347上可形成一第二外分隔件351。該第二外分隔件351之形成可包括一薄膜形成程序及一異向蝕刻程序。可暴露該第二較快蝕刻速度部349之一上表面。 A second intermediate partition 347 may be formed on the second inner partition 342. A second faster etch rate portion 349 is formed in the second active region 323 using the second intermediate spacer 347 as an ion implantation mask. A second outer spacer 351 may be formed on the second intermediate spacer 347. The formation of the second outer spacer 351 may include a film forming process and an anisotropic etching process. One of the upper surfaces of the second faster etch rate portion 349 may be exposed.
該第一LDD43及該第二LDD343可包含硼。該第二LDD343可具有一比該第一LDD43之硼濃度高之硼濃度。該第一較快蝕刻速度部49及該第二較快蝕刻速度部349可包含磷。該第二較快蝕刻速度部349可具有一比該第一較快蝕刻速度部49之磷濃度低之磷濃度。 The first LDD 43 and the second LDD 343 may comprise boron. The second LDD 343 can have a boron concentration that is higher than the boron concentration of the first LDD 43. The first faster etch rate portion 49 and the second faster etch rate portion 349 may comprise phosphorous. The second faster etch rate portion 349 can have a phosphor concentration that is lower than the phosphor concentration of the first faster etch rate portion 49.
在某些實施例中,該第二LDD343可包含一比該第一LDD43之硼濃度高之硼濃度,且該第二較快蝕刻速度部349可具有一比該第一較快蝕刻速度部49之磷濃度 低之磷濃度。在某些實施例中,可省略該第二較快蝕刻速度部349。 In some embodiments, the second LDD 343 can include a boron concentration that is higher than the boron concentration of the first LDD 43, and the second faster etch rate portion 349 can have a faster than the first faster etch rate portion 49. Phosphorus concentration Low phosphorus concentration. In some embodiments, the second faster etch rate portion 349 can be omitted.
請參閱圖32與34,可蝕刻該第一較快蝕刻速度部49、該第一LDD43及該第一暈圈45以形成一第一預備槽53。該第一預備槽53可包括與該第一較快蝕刻速度部49對齊之一第一上槽53A及與該第一上槽53A之一底部連接的一第一下槽53B。該第一上槽53A可形成在該第一LDD43中。該第一下槽53B可通過該第一LDD43而形成在該第一暈圈45中。該第一下槽53B可具有比該第一上槽53A之一寬度小之一寬度。該第一預備槽53之一側壁可具有一階部。例如,藉由該第一上槽53A及第一下槽53B暴露之該第一LDD43的一側壁可具有一階部。 Referring to FIGS. 32 and 34, the first faster etch rate portion 49, the first LDD 43 and the first halo 45 may be etched to form a first preliminary trench 53. The first preliminary groove 53 may include a first upper groove 53A aligned with the first faster etching speed portion 49 and a first lower groove 53B connected to one of the bottom portions of the first upper groove 53A. The first upper groove 53A may be formed in the first LDD 43. The first lower groove 53B is formed in the first halo 45 by the first LDD 43. The first lower groove 53B may have a width smaller than a width of one of the first upper grooves 53A. One side wall of the first preliminary groove 53 may have a first step. For example, a sidewall of the first LDD 43 exposed by the first upper trench 53A and the first lower trench 53B may have a first step.
可蝕刻該第二較快蝕刻速度部349、該第二LDD343及該第二暈圈345以形成一第二預備槽353。該第二預備槽353可包括與該第二較快蝕刻速度部349對齊之一第二上槽353A及與該第二上槽353A之一底部連接之一第二下槽353B。在該第二LDD343中可形成該第二上槽353A。該第二下槽353B可通過該第二LDD343而形成在該第二暈圈345中。該第二下槽353B可具有一比該第二上槽353A之寬度小的寬度。該第二預備槽353之一側壁可具有一階部。例如,藉由該第二上槽353A及該第二下槽353B暴露之該第二LDD343的一側壁可具有一階部。 The second faster etch rate portion 349, the second LDD 343, and the second halo 345 may be etched to form a second preliminary trench 353. The second preliminary groove 353 may include a second upper groove 353A aligned with the second faster etching speed portion 349 and a second lower groove 353B connected to one of the second upper grooves 353A. The second upper groove 353A may be formed in the second LDD 343. The second lower groove 353B can be formed in the second halo 345 by the second LDD 343. The second lower groove 353B may have a width smaller than a width of the second upper groove 353A. One side wall of the second preliminary groove 353 may have a first step. For example, a sidewall of the second LDD 343 exposed by the second upper trench 353A and the second lower trench 353B may have a first step.
該第一預備槽53及該第二預備槽353之形成可包括一乾式蝕刻程序,一濕式蝕刻程序或其組合。該第 一預備槽53及該第二預備槽353之形成可包括一等向蝕刻程序,一異向蝕刻程序或其組合。例如,該第一預備槽53及該第二預備槽353之形成可包括使用HBr、CF4、O2、Cl2、NF3或其組合之一等向乾式蝕刻程序。依據某些實施例,具有一比該第一LDD43之硼濃度高之硼濃度的該第二LDD343可具有一比該第一LDD43之蝕刻速度低之蝕刻速度。依據某些實施例,具有一比該第一較快蝕刻速度部49之磷濃度低之磷濃度的該第二較快蝕刻速度部349可具有一比該第一較快蝕刻速度部49之蝕刻速度低之蝕刻速度。 The formation of the first preliminary groove 53 and the second preliminary groove 353 may include a dry etching process, a wet etching process, or a combination thereof. The formation of the first preliminary groove 53 and the second preliminary groove 353 may include an isotropic etching process, an anisotropic etching process, or a combination thereof. For example, the formation of the first preliminary trench 53 and the second preliminary trench 353 may include a dry etching process using one of HBr, CF 4 , O 2 , Cl 2 , NF 3 , or a combination thereof. In accordance with certain embodiments, the second LDD 343 having a boron concentration that is higher than the boron concentration of the first LDD 43 can have an etch rate that is lower than the etch rate of the first LDD 43. According to some embodiments, the second faster etch rate portion 349 having a lower phosphorus concentration than the first faster etch rate portion 49 may have an etch compared to the first faster etch rate portion 49. Low etch rate.
依據該第一較快蝕刻速度部49,該第二較快蝕刻速度部349、該第一LDD43及該第二LDD343之構態,可決定該第一上槽53A、該第一下槽53B、該第二上槽353A及該第二下槽353B之尺寸及形狀。使用該第一較快蝕刻速度部49、該第二較快蝕刻速度部349、該第一LDD43及該第二LDD343之構態,可依需要控制該第一預備槽53及該第二預備槽353之尺寸、形狀及位置。 According to the first faster etch rate portion 49, the configuration of the second faster etch rate portion 349, the first LDD 43 and the second LDD 343 may determine the first upper slot 53A, the first lower slot 53B, The size and shape of the second upper groove 353A and the second lower groove 353B. The first preliminary groove 53 and the second preliminary groove can be controlled as needed by using the configuration of the first faster etching speed portion 49, the second faster etching speed portion 349, the first LDD 43 and the second LDD 343. 353 size, shape and location.
請參閱圖32與35,使用一方向性蝕刻程序可在該第一作用區域23中形成一第一槽55且在該第二作用區域323中形成一第二槽355。例如,該第一槽55及該第二槽355之形成可包括一使用NH4OH、NH3OH、TMAH(四甲基氫氧化銨)、KOH、NaOH、BTMH(苄基三甲基氫氧化銨)或其組合之濕式蝕刻。 Referring to FIGS. 32 and 35, a first trench 55 may be formed in the first active region 23 and a second trench 355 may be formed in the second active region 323 using a directional etching process. For example, the formation of the first tank 55 and the second tank 355 may include using NH 4 OH, NH 3 OH, TMAH (tetramethylammonium hydroxide), KOH, NaOH, BTMH (benzyltrimethyl hydroxide). Wet etching of ammonium or a combination thereof.
由於該第一槽55,該第一作用區域23可具有一第一西格馬形狀(Σ形狀)。該第一LDD43可被扣持在該第 一暫時閘極圖案31、33、35與37下方。該第一作用區域23可包括一第一表面23SU、一第一側表面23S1、一第二側表面23S2及一第二表面23S3。在該第一側表面23S1與該第一表面23SU之間可界定一第一邊緣E1。在該第一側表面23S1與該第二側表面23S2之間可界定一第二邊緣E2。 Due to the first groove 55, the first active region 23 may have a first sigma shape (Σ shape). The first LDD 43 can be held in the first Below the temporary gate patterns 31, 33, 35 and 37. The first active area 23 can include a first surface 23SU, a first side surface 23S1, a second side surface 23S2, and a second surface 23S3. A first edge E1 may be defined between the first side surface 23S1 and the first surface 23SU. A second edge E2 may be defined between the first side surface 23S1 and the second side surface 23S2.
由於該第二槽355,該第二作用區域323可具有一第二西格馬形狀(Σ形狀)。該第二LDD343可被扣持在該第二暫時閘極圖案331、333、335與337下方。該第二作用區域323可包括一第三表面323SU、一第三側表面323S1、一第四側表面323S2及一第四表面323S3。在該第三側表面323S1與該第三表面323SU之間可界定一第三邊緣E31。在該第三側表面323S1與該第四側表面323S2之間可界定一第四邊緣E32。 Due to the second groove 355, the second active region 323 may have a second sigma shape (Σ shape). The second LDD 343 can be held under the second temporary gate patterns 331, 333, 335 and 337. The second active area 323 can include a third surface 323SU, a third side surface 323S1, a fourth side surface 323S2, and a fourth surface 323S3. A third edge E31 may be defined between the third side surface 323S1 and the third surface 323SU. A fourth edge E32 may be defined between the third side surface 323S1 and the fourth side surface 323S2.
該第一槽55可被解讀為該第一預備槽53之一延伸部,且該第二槽355可被解讀為該第二預備槽353之一延伸部。 The first groove 55 can be interpreted as an extension of the first preparation groove 53 , and the second groove 355 can be interpreted as an extension of the second preparation groove 353 .
請參閱圖32與36,該第一槽55可通過該第一LDD43及該第一暈圈45。在該第一作用區域23之一上端上可界定該第一表面23SU。例如,該第一表面23SU可與該第一緩衝層31接觸且在該第一內分隔件42下方延伸。該第一槽55可暴露該第一側表面23S1、該第二側表面23S2及該第二表面23S3。該第一側表面23S1可與該第一表面23SU連接。該第一側表面23S1可相對該第一表面23SU形成一銳角。該第二側表面23S2可形成在該第一側表面23S1下方。 該第二側表面23S2可具有一與該第一側表面23S1不同之斜率。該第二側表面23S2可相對一水平延伸線形成一銳角,且該水平延伸線平行於該基材21且通過該第二表面23S3。該第一槽55之一底部可暴露該第二表面23S3。該第二表面23S3可與該第二側表面23S2連接。該第一表面23SU可解讀為該第一作用區域23之一上表面。 Referring to FIGS. 32 and 36, the first slot 55 can pass through the first LDD 43 and the first halo 45. The first surface 23SU may be defined on an upper end of the first active region 23. For example, the first surface 23SU may be in contact with the first buffer layer 31 and extend below the first inner spacer 42. The first groove 55 may expose the first side surface 23S1, the second side surface 23S2, and the second surface 23S3. The first side surface 23S1 can be coupled to the first surface 23SU. The first side surface 23S1 can form an acute angle with respect to the first surface 23SU. The second side surface 23S2 may be formed below the first side surface 23S1. The second side surface 23S2 may have a different slope from the first side surface 23S1. The second side surface 23S2 can form an acute angle with respect to a horizontally extending line, and the horizontally extending line is parallel to the substrate 21 and passes through the second surface 23S3. The bottom of one of the first grooves 55 may expose the second surface 23S3. The second surface 23S3 is connectable to the second side surface 23S2. The first surface 23SU can be interpreted as one of the upper surfaces of the first active region 23.
該第二槽355可通過該第二LDD43及該第二暈圈345。在該第二作用區域323之一上端上可界定該第三表面323SU。例如,該第三表面323SU可與該第二緩衝層331接觸且在該第二內分隔件342下方延伸。該第二槽355可暴露該第三側表面323S1、該第四側表面323S2及該第四表面323S3。該第三側表面323S1可與該第三表面323SU連接。該第三側表面323S1可相對該第三表面323SU形成一銳角。該第四側表面323S2可形成在該第三側表面323S1下方。該第四側表面323S2可具有一與該第三側表面323S1不同之斜率。該第四側表面323S2可相對一水平延伸線形成一銳角,且該水平延伸線平行於該基材21且通過該第四表面323S3。該第二槽355之一底部可暴露該第四表面323S3。該第四表面323S3可與該第四側表面323S2連接。該第三表面323SU可解讀為該第二作用區域323之一上表面。 The second slot 355 can pass through the second LDD 43 and the second halo 345. The third surface 323SU may be defined on an upper end of one of the second active regions 323. For example, the third surface 323SU may be in contact with the second buffer layer 331 and extend under the second inner spacer 342. The second groove 355 may expose the third side surface 323S1, the fourth side surface 323S2, and the fourth surface 323S3. The third side surface 323S1 may be coupled to the third surface 323SU. The third side surface 323S1 may form an acute angle with respect to the third surface 323SU. The fourth side surface 323S2 may be formed below the third side surface 323S1. The fourth side surface 323S2 may have a different slope from the third side surface 323S1. The fourth side surface 323S2 may form an acute angle with respect to a horizontally extending line, and the horizontal extension line is parallel to the substrate 21 and passes through the fourth surface 323S3. The bottom of one of the second grooves 355 may expose the fourth surface 323S3. The fourth surface 323S3 is connectable to the fourth side surface 323S2. The third surface 323SU can be interpreted as an upper surface of the second active region 323.
使用該第一LDD43及該第一較快蝕刻速度部49之構態,該第一邊緣E1及該第二邊緣E2可形成在所欲位置。例如,該第一邊緣E1可形成在該第一內分隔件42 下方,且該第二邊緣E2可形成為與該第一暫時閘極電極33重疊。該第一邊緣E1及該第二邊緣E2可位在該第一LDD43之一表面上。該第一側表面23S1可暴露該第一LDD43。該第二側表面23S2可暴露該第一LDD43、該第一暈圈45及該第一作用區域23。 Using the configuration of the first LDD 43 and the first faster etch rate portion 49, the first edge E1 and the second edge E2 can be formed at desired positions. For example, the first edge E1 may be formed at the first inner spacer 42 Below, the second edge E2 may be formed to overlap the first temporary gate electrode 33. The first edge E1 and the second edge E2 may be located on a surface of the first LDD 43. The first side surface 23S1 may expose the first LDD 43. The second side surface 23S2 can expose the first LDD 43, the first halo 45 and the first active area 23.
使用該第二LDD43及該第二較快蝕刻速度部349之構態,該第三邊緣E31及該第四邊緣E32可形成在所欲位置。例如,該第三邊緣E31可形成在該第二內分隔件342下方,且該第四邊緣E32可與該第二暫時閘極電極333之一外側對齊。該第三邊緣E31及該第四邊緣E32可位在該第二LDD343之一表面上。該第三側表面323S1可暴露該第二LDD343。該第四側表面323S2可暴露該第二LDD343、該第二暈圈345及該第二作用區域323。 Using the configuration of the second LDD 43 and the second faster etch rate portion 349, the third edge E31 and the fourth edge E32 can be formed at desired positions. For example, the third edge E31 may be formed under the second inner spacer 342, and the fourth edge E32 may be aligned with an outer side of the second temporary gate electrode 333. The third edge E31 and the fourth edge E32 may be located on a surface of the second LDD 343. The third side surface 323S1 may expose the second LDD 343. The fourth side surface 323S2 may expose the second LDD 343, the second halo 345, and the second active area 323.
在該第二邊緣E2與通過該第一暫時閘極電極33之一側表面且垂直於該基材21的一直線之間可界定一第一水平距離X1。在該第二邊緣E2與通過該第一表面23SU且平行於該基材21之一直線之間可界定一第一垂直高度Y1。例如,該第一水平距離X1可為零至-5nm,且該第一垂直高度Y1可由3nm至7nm。可解讀為當該第一水平距離X1為零時,該第二邊緣E2被該第一暫時閘極電極33之側表面垂直地重疊,且當該第一水平距離X1為一負(-)值時,該第二邊緣E2被該第一暫時閘極電極33之一底部垂直地重疊。 A first horizontal distance X1 may be defined between the second edge E2 and a line passing through one side surface of the first temporary gate electrode 33 and perpendicular to the substrate 21. A first vertical height Y1 may be defined between the second edge E2 and a line passing through the first surface 23SU and parallel to the substrate 21. For example, the first horizontal distance X1 may be from zero to -5 nm, and the first vertical height Y1 may be from 3 nm to 7 nm. It can be interpreted that when the first horizontal distance X1 is zero, the second edge E2 is vertically overlapped by the side surface of the first temporary gate electrode 33, and when the first horizontal distance X1 is a negative (-) value The second edge E2 is vertically overlapped by the bottom of one of the first temporary gate electrodes 33.
在該第四邊緣E32與通過該第二暫時閘極電極333之一側表面且垂直於該基材21的一直線之間可界定 一第二水平距離X3。在該第四邊緣E32與通過該第三表面323SU且平行於該基材21之一直線之間可界定一第二垂直高度Y3。該第四邊緣E32可形成在一比該第二邊緣E2低之高度。例如,該第三水平距離X3可為+1nm至+3nm,且該第二垂直高度Y3可由8nm至12nm。可解讀為當該第二水平距離X3為一正值時,該第二暫時閘極電極333不重疊該第四邊緣E32。 Definable between the fourth edge E32 and a straight line passing through one side surface of the second temporary gate electrode 333 and perpendicular to the substrate 21. A second horizontal distance X3. A second vertical height Y3 may be defined between the fourth edge E32 and a line passing through the third surface 323SU and parallel to one of the substrates 21. The fourth edge E32 may be formed at a lower height than the second edge E2. For example, the third horizontal distance X3 may be +1 nm to +3 nm, and the second vertical height Y3 may be 8 nm to 12 nm. It can be interpreted that when the second horizontal distance X3 is a positive value, the second temporary gate electrode 333 does not overlap the fourth edge E32.
請參閱圖32與37,在該第一槽55中可形成一第一半導體層61。在該第一半導體層61上可形成一第二半導體層62。在該第二半導體層62上可形成一第三半導體層63。該第一半導體層61、該第二半導體層62及該第三半導體層63可形成一第一埋入應力件65。 Referring to FIGS. 32 and 37, a first semiconductor layer 61 may be formed in the first trench 55. A second semiconductor layer 62 may be formed on the first semiconductor layer 61. A third semiconductor layer 63 may be formed on the second semiconductor layer 62. The first semiconductor layer 61, the second semiconductor layer 62, and the third semiconductor layer 63 may form a first buried stress member 65.
在該第二槽355中可形成一第四半導體層361。在該第四半導體層361上可形成一第五半導體層362。在該第五半導體層362上可形成一第六半導體層363。該第四半導體層361、該第五半導體層362及該第六半導體層363可形成一第二埋入應力件365。該第四半導體層361可包括與該第一半導體層61同時形成之相同材料,該第五半導體層362可包括與該第二半導體層62同時形成之相同材料,且該第六半導體層363可包括與該第三半導體層63同時形成之相同材料。 A fourth semiconductor layer 361 can be formed in the second trench 355. A fifth semiconductor layer 362 may be formed on the fourth semiconductor layer 361. A sixth semiconductor layer 363 may be formed on the fifth semiconductor layer 362. The fourth semiconductor layer 361, the fifth semiconductor layer 362, and the sixth semiconductor layer 363 may form a second buried stress member 365. The fourth semiconductor layer 361 may include the same material formed simultaneously with the first semiconductor layer 61, the fifth semiconductor layer 362 may include the same material formed simultaneously with the second semiconductor layer 62, and the sixth semiconductor layer 363 may be The same material as that formed simultaneously with the third semiconductor layer 63 is included.
在該基材21上可形成一第一層間絕緣層71及一第二層間絕緣層371。可移除該第一暫時閘極圖案31、33、35與37以暴露該第一作用區域23,且可移除該第 二暫時閘極圖案331、333、335與337以暴露該第二作用區域323。 A first interlayer insulating layer 71 and a second interlayer insulating layer 371 may be formed on the substrate 21. The first temporary gate patterns 31, 33, 35 and 37 may be removed to expose the first active region 23, and the first Two temporary gate patterns 331, 333, 335 and 337 to expose the second active region 323.
在該第一作用區域23上可形成一第一閘極介電層73、一第二閘極介電層75、一第一閘極電極77及一第二閘極電極79。在該第二作用區域323上可形成一第三閘極介電層373、一第四閘極介電層375、一第三閘極電極377及一第四閘極電極379。該第三閘極介電層373可具有與該第一閘極介電層73類似之構態,該第四閘極介電層375可具有與該第二閘極介電層75類似之構態,該第三閘極電極377可具有與該第一閘極電極77類似之構態,且該第四閘極電極379可具有與該第二閘極電極79類似之構態。 A first gate dielectric layer 73, a second gate dielectric layer 75, a first gate electrode 77 and a second gate electrode 79 are formed on the first active region 23. A third gate dielectric layer 373, a fourth gate dielectric layer 375, a third gate electrode 377, and a fourth gate electrode 379 are formed on the second active region 323. The third gate dielectric layer 373 can have a configuration similar to the first gate dielectric layer 73. The fourth gate dielectric layer 375 can have a similar structure to the second gate dielectric layer 75. The third gate electrode 377 can have a configuration similar to the first gate electrode 77, and the fourth gate electrode 379 can have a configuration similar to the second gate electrode 79.
請參閱圖32與38,該第一埋入應力件65可通過該第一LDD43及該第一暈圈45而與該第一作用區域23接觸。該第一埋入應力件65之一底部可形成在一比該第一暈圈45低之高度。該第一埋入應力件65可與該第一側表面23S1及該第二側表面23S2接觸。該第二埋入應力件365可通過該第二LDD343及該第二暈圈345而與該第二作用區域323接觸。該第二埋入應力件365之一底部可形成在一比該第二暈圈345低之高度。該第二埋入應力件365可與該第三側表面323S1及該第四側表面323S2接觸。 Referring to FIGS. 32 and 38, the first embedded stress member 65 can be in contact with the first active region 23 through the first LDD 43 and the first halo 45. The bottom of one of the first embedding stress members 65 may be formed at a lower height than the first halo 45. The first embedding stress member 65 is in contact with the first side surface 23S1 and the second side surface 23S2. The second embedding stress member 365 can be in contact with the second active region 323 through the second LDD 343 and the second halo 345. The bottom of one of the second buried stress members 365 may be formed at a lower height than the second halo 345. The second embedding stress member 365 can be in contact with the third side surface 323S1 and the fourth side surface 323S2.
在該第一LDD43之一表面上可形成該第二邊緣E2,且在該第二LDD343之一表面上可形成該第四邊緣E32。該第二邊緣E2可形成在一比該第四邊緣E32高之高 度。該第二邊緣E2可重疊該第一閘極電極77之一底部,且該第四邊緣E32可與該第三閘極電極377之一外側對齊。 The second edge E2 may be formed on a surface of one of the first LDDs 43, and the fourth edge E32 may be formed on a surface of one of the second LDDs 343. The second edge E2 can be formed at a height higher than the fourth edge E32 degree. The second edge E2 may overlap one of the bottoms of the first gate electrode 77, and the fourth edge E32 may be aligned with an outer side of the third gate electrode 377.
圖39與40係依據本發明觀念之某些實施例之一電子設備的立體圖及方塊圖。請參閱圖39,依據某些實施例之半導體裝置可應用於電子系統,例如一智慧型手機1900、一輕省筆電、一筆記型電腦、或一平板電腦。例如,依據某些實施例之半導體裝置可安裝在該智慧型手機1900之一主板中。此外,依據某些實施例之半導體裝置可設置於一擴充設備,例如可與該智慧型手機1900組合之一外部記憶卡。 39 and 40 are perspective and block diagrams of an electronic device in accordance with some embodiments of the inventive concept. Referring to FIG. 39, a semiconductor device according to some embodiments may be applied to an electronic system, such as a smart phone 1900, a light notebook, a notebook computer, or a tablet computer. For example, a semiconductor device in accordance with some embodiments can be installed in a motherboard of the smart phone 1900. Moreover, the semiconductor device in accordance with some embodiments can be provided in an expansion device, such as an external memory card that can be combined with the smart phone 1900.
請參閱圖40,依據某些實施例之半導體裝置可應用於一電子系統2100。該電子系統2100可包括一本體2110、一微處理器單元2120、一電源單元2130、一功能單元2140、及/或一顯示器控制單元2150。該本體2110可以是由一印刷電路板(PCB)形成之一母板。該微處理器單元2120、該電源單元2130、該功能單元2140及顯示器控制單元2150可裝設或安裝在該本體2110上。一顯示器單元2160可配置在該本體2110之一表面上且顯示一藉由該顯示器控制單元2150處理之影像。 Referring to FIG. 40, a semiconductor device in accordance with some embodiments may be applied to an electronic system 2100. The electronic system 2100 can include a body 2110, a microprocessor unit 2120, a power unit 2130, a functional unit 2140, and/or a display control unit 2150. The body 2110 can be a motherboard formed from a printed circuit board (PCB). The microprocessor unit 2120, the power unit 2130, the function unit 2140, and the display control unit 2150 can be mounted or mounted on the body 2110. A display unit 2160 can be disposed on a surface of the body 2110 and display an image processed by the display control unit 2150.
該電源單元2130可由一外部電池等接受一固定電壓,將該電壓分成各種位準,且將這些電壓供應至該微處理器單元2120、該功能單元2140及該顯示器控制單元2150等。該微處理器單元2120可由該電源單元2130接受一電壓以控制該功能單元2140及該顯示器單元2160。該功 能單元2140可執行該電子系統2100之各種功能。例如,當該電子系統2100係一行動電話,該功能單元2140可具有數種組件,且該等組件可藉由撥號或與一外部設備2170通訊來執行例如輸出一影像至該顯示器單元2160或輸出一聲音至一擴音器等之行動電話功能。如果安裝一攝影機,該功能單元2140可作為一影像處理器。 The power supply unit 2130 can receive a fixed voltage from an external battery or the like, divide the voltage into various levels, and supply the voltages to the microprocessor unit 2120, the function unit 2140, the display control unit 2150, and the like. The microprocessor unit 2120 can receive a voltage from the power unit 2130 to control the functional unit 2140 and the display unit 2160. The work The energy unit 2140 can perform various functions of the electronic system 2100. For example, when the electronic system 2100 is a mobile phone, the functional unit 2140 can have several components, and the components can perform, for example, outputting an image to the display unit 2160 or output by dialing or communicating with an external device 2170. A voice to a mobile phone function such as a loudspeaker. If a camera is installed, the functional unit 2140 can function as an image processor.
依據某些實施例,當該電子系統2100與一記憶卡等連接以擴大容量時,該功能單元2140可以是一記憶卡控制器。該功能單元2140可透過一有線或無線通訊單元2180與該外部設備2170交換信號。此外,當該電子系統2100需要一通用串列匯流排(USB)等以擴大功能時,該功能單元2140可作為一介面控制器。此外,該功能單元2140可包括一大量儲存設備。 According to some embodiments, when the electronic system 2100 is connected to a memory card or the like to expand the capacity, the functional unit 2140 may be a memory card controller. The functional unit 2140 can exchange signals with the external device 2170 through a wired or wireless communication unit 2180. In addition, when the electronic system 2100 requires a universal serial bus (USB) or the like to expand the function, the functional unit 2140 can function as an interface controller. Additionally, the functional unit 2140 can include a mass storage device.
依據某些實施例之半導體裝置可應用於該功能單元2140或該微處理器單元2120。例如,該微處理器單元2120可包括該埋入應力件65。由於該埋入應力件65之構態,該微處理器單元2120可具有一良好電氣特性。 A semiconductor device in accordance with certain embodiments may be applied to the functional unit 2140 or the microprocessor unit 2120. For example, the microprocessor unit 2120 can include the buried stress member 65. Due to the configuration of the buried stress member 65, the microprocessor unit 2120 can have a good electrical characteristic.
圖41係依據本發明觀念之某些實施例之一電子系統的方塊圖。請參閱圖41,該電子系統2400可包括依據某些實施例之至少一半導體裝置。該電子系統2400可被用來製造一行動設備或一電腦。例如,該電子系統2400可包括一記憶體系統2412、一微處理器2414、一隨機存取記憶體(RAM)2416、一匯流排2420及一使用者介面2418。該微處理器2414、該記憶體系統2412及該使用者介面2418 可透過該匯流排2420互相連接。該使用者介面2418可用以輸入/輸出資料至/由該電子系統2400。該微處理器2414可規劃及控制該電子系統2400。該RAM2416可作為該微處理器2414之一操作記憶體使用。該微處理器2414、該RAM2416及/或其他組件可組合在一單一封裝體中。該微處理器2414可儲存用以操作該微處理器2414之代碼、由該微處理器2414所處理之資料、或外部輸入資料。該記憶體系統2412可包括一控制器或一記憶體。 Figure 41 is a block diagram of an electronic system in accordance with some embodiments of the inventive concept. Referring to FIG. 41, the electronic system 2400 can include at least one semiconductor device in accordance with certain embodiments. The electronic system 2400 can be used to make a mobile device or a computer. For example, the electronic system 2400 can include a memory system 2412, a microprocessor 2414, a random access memory (RAM) 2416, a bus 2420, and a user interface 2418. The microprocessor 2414, the memory system 2412, and the user interface 2418 The busbars 2420 can be connected to each other. The user interface 2418 can be used to input/output data to/from the electronic system 2400. The microprocessor 2414 can plan and control the electronic system 2400. The RAM 2416 can be used as one of the operating memories of the microprocessor 2414. The microprocessor 2414, the RAM 2416, and/or other components can be combined in a single package. The microprocessor 2414 can store code for operating the microprocessor 2414, data processed by the microprocessor 2414, or external input data. The memory system 2412 can include a controller or a memory.
該微處理器2414、該RAM2416或該記憶體系統2412可包括依據某些實施例之半導體裝置。例如,該微處理器2414可包括該埋入應力件65。由於該埋入應力件65之構態,該微處理器2414可具有一良好電氣特性。 The microprocessor 2414, the RAM 2416, or the memory system 2412 can include a semiconductor device in accordance with certain embodiments. For example, the microprocessor 2414 can include the buried stress member 65. Due to the configuration of the buried stress member 65, the microprocessor 2414 can have a good electrical characteristic.
依據某些實施例之半導體裝置可包括填充一槽之一埋入應力件,且該槽形成在一作用區域中。形成該槽可包括藉由在一LDD中植入磷形成一較快蝕刻速度部,藉由等向地蝕刻該較快蝕刻速度部形成一第一槽,及使用一方向性蝕刻程序形成一第二槽。該埋入應力件可填充該槽。因為該埋入應力件之一尺寸、一形狀及一位置之控制可以是容易的/經改良的,該圖案負載效應可減少/減至最小,且依據在該中心區域與一邊緣區域之間之作用區域之位置的變化可以減少,所以依據某些實施例之半導體裝置可具有良好電氣特性。 A semiconductor device in accordance with some embodiments may include a buried stress member filled in a trench, and the trench is formed in an active region. Forming the trench may include forming a faster etch rate portion by implanting phosphorus in an LDD, forming a first trench by isotropically etching the faster etch rate portion, and forming a first portion using a directional etch process Two slots. The buried stress member can fill the groove. Since the control of the size, shape and position of one of the embedded stress members can be easily/improved, the pattern loading effect can be reduced/minimized and depending on between the central region and an edge region. Variations in the location of the active area can be reduced, so semiconductor devices in accordance with certain embodiments can have good electrical characteristics.
上述標的物應被視為是說明的,而不是限制的,且附加之申請專利範圍係意圖涵蓋所有落在本發明觀 念之真正精神與範疇內之所有修改、改進及其他實施例。因此,就法律容許之最大範圍而言,該範疇應由以下申請專利範圍及其等效物之最廣義之可容許解釋決定,且不應被前述詳細說明限制或界限。 The above subject matter is to be regarded as illustrative and not limiting, and the scope of the appended claims is intended to cover all All modifications, improvements and other embodiments within the true spirit and scope of the subject matter. Therefore, to the extent permitted by law, the scope should be construed as the broadest interpretation of the scope of the following claims and their equivalents, and should not be limited or limited by the foregoing detailed description.
500-570‧‧‧方塊 500-570‧‧‧ square
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US20160087101A1 (en) | 2016-03-24 |
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