JP2006135340A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having shallow source and drain layers of high density. <P>SOLUTION: The semiconductor device comprises a substrate which has a surface region of silicon, a gate insulating film formed on the surface region, a gate electrode formed on the gate insulating film, side wall insulating films provided on both sides of the gate electrode, and burying formation type source and drain layers formed by depositing a silicon film containing impurities in grooves formed on a substrate surface at parts extending from below to outside the side wall insulating films. The impurity density of silicon films at bottoms of the grooves are 1×10<SP>19</SP>to 1×10<SP>22</SP>cm<SP>-3</SP>, the impurity density of the silicon films along the depths of the grooves is constant, and the burying formation type source and drain layers are formed outside the side wall insulating films and thicker than the 1st burying formation type source and drain layers, are include 1st burying formation type source and drain layers formed below the side wall insulating films and 2nd burying formation type source and drain layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a high concentration shallow source / drain layer.

  In recent years, large-scale integrated circuits (LSIs) formed by integrating a large number of transistors, resistors, and the like so as to achieve an electric circuit and integrating them on a single chip are often used in important parts of computers and communication devices. ing.

  Recently, a selective vapor deposition method (selective CVD method) has been studied as an LSI technology. The selective CVD method is applied to, for example, elevated source / drain technology and self-aligned contact technology. With this technique, it is possible to form a source / drain impurity diffusion layer having excellent characteristics and a silicon layer serving as a direct contact layer by a single selective growth process.

As a conventional typical selective silicon layer CVD method, for example, as shown in FIG. 13, a gas of Si / Cl / H ₂ reduction reaction system, particularly dichlorosilane (SiH ₂ Cl ₂ ) source gas is hydrochloric acid (HCl). An exposed surface of the silicon substrate 1 in the opening by using the insulating film 2 such as a silicon oxide film (SiO ₂ ) or a nitride film (Si ₃ N ₄ ) as a mask by a CVD method using a gas and a gas containing H ₂ gas. Further, there is known one that selectively grows the silicon layer 3. Further, doping of the selectively grown silicon layer 3 with impurities is performed by mixing a gaseous compound containing impurity atoms in the reaction gas.

  However, in this type of selective CVD method, the gas types that can provide good selectivity are limited, and the silicon layer 3 is normally epitaxially grown. Therefore, as shown in FIG. 13B, a (111) facet is usually formed in the silicon layer 3.

  When forming a shallow impurity diffusion layer, a silicide film is usually formed to reduce the resistance of the impurity diffusion layer. Specifically, for example, a titanium film is formed by sputtering on the impurity diffusion layer, and a titanium silicide film is formed by performing heat treatment at 700 ° C. for 30 seconds by RTA.

  At this time, the refractory metal film serving as the silicide film reacts with the silicon of the impurity diffusion layer to form the silicide film, so that the silicon of the impurity diffusion layer is consumed. For this reason, when the depth of the impurity diffusion layer is shallow, it is necessary to selectively grow a silicon layer on the impurity diffusion layer to increase the effective thickness of the impurity diffusion layer.

  However, when this silicon layer is an epitaxially grown film, facets are formed as in the silicon layer 3 of FIG. 12, so that the edge of the silicon layer becomes thin, and the effect of stacking the silicon layers decreases.

  In order to avoid such a problem, when an amorphous silicon layer is selectively deposited, it is necessary to lower the deposition temperature or the substrate temperature. Problems arise.

  FIG. 14 is a process sectional view showing a conventional direct contact technique.

First, as shown in FIG. 14A, BF ^{2 +} is ion-implanted into the surface of a p-type silicon substrate 11 to selectively form an n-type impurity diffusion region 13. Next, as shown in FIG. 2A, after an insulating film 12 is deposited on the p-type silicon substrate 11, an opening (contact hole) is formed in the insulating film 12.

  Next, as shown in FIG. 14B, the opening is filled with a single crystal silicon layer 14 as an electrode containing an impurity by selective epitaxial growth.

  Finally, as shown in FIG. 14C, after depositing a polycrystalline silicon layer on the entire surface, the wiring 15 is formed by patterning it.

  When such a method is used, since the single crystal silicon layer 14 is an epitaxial silicon layer, a facet of the (111) plane appears and it is difficult to fill the opening smoothly.

  Further, in order to deposit the polycrystalline silicon layer as the wiring 15, when it is exposed to the atmosphere when it is transferred from the selective deposition furnace to the polycrystalline silicon layer deposition furnace, it is naturally oxidized on the upper part of the single crystal silicon layer 14. A film is formed, and the contact resistance with the wiring 15 increases. Further, when exposed to the atmosphere, good selectivity cannot be obtained due to contaminants such as dust, and silicon may be deposited on the insulating film 12 to cause a wiring short circuit.

  By the way, in order to suppress the short channel effect of the MOS transistor, the diffusion depth of the source / drain diffusion layer is conventionally made shallower, and the concentration of the source / drain diffusion layer is increased in order to maintain low resistance. It is requested.

  These requirements are particularly required at the end of the source / drain diffusion layer. That is, as the miniaturization progresses, it is desirable that the end portions of the source / drain diffusion layers have a higher concentration and a smaller diffusion depth. In order to realize such a requirement, an LDD (Lightly Doped Drain) structure has heretofore been adopted as the structure of the source / drain diffusion layer.

  In the LDD structure, after forming the gate electrode, first, a low-concentration shallow source / drain diffusion layer is formed by ion implantation with a low acceleration / low dose, and then a sidewall gate insulating film is formed. It can be obtained by forming a high concentration deep source / drain diffusion layer by high dose ion implantation. In order to reduce the resistance, a silicide film is usually formed on the source / drain diffusion layer.

  In order to further advance the miniaturization by the LDD structure, it is necessary to reduce the acceleration of impurities implanted into the end portion of the gate electrode or to reduce the dose.

  However, if the acceleration of ion implantation is reduced in order to form a shallower source / drain diffusion layer having a lower concentration, there arises a problem that the beam current at the time of ion implantation is lowered and the throughput is lowered. Further, even at the low acceleration, the substrate surface is sputtered during ion implantation.

  If the acceleration voltage is lowered to about ½, for example, if the acceleration voltage is lowered to about 1/2, the depth of the tail portion of the ion implantation cannot be lowered to about ½ due to channeling or the like.

  As described above, in ion implantation, the formation of a shallow junction is theoretically limited. That is, the implanted impurity distribution greatly depends on the acceleration energy at the time of ion implantation, and it is necessary to obtain a shallow ion implantation distribution in order to obtain a shallow junction.

Since the implantation depth is almost inversely proportional to the mass of ions, it becomes more problematic in forming a p ⁺ layer without appropriate impurities other than boron. Conventionally, BF ²⁺ ions have been used as a method for effectively reducing acceleration energy. An example of this method is shown in FIG.

  In this method, first, as shown in FIG. 47A, a silicon oxide film and a polycrystalline silicon film are formed in an element region divided by an element isolation insulating film 42 formed on a silicon substrate 41, and a resist pattern is formed. By patterning as a mask, the gate insulating film 43 and the gate electrode 44 are formed.

Then, as shown in FIG. 47B, BF ²⁺ ions 46 are implanted using the gate electrode 44 as a mask. The implanted BF ²⁺ ions repeatedly collide inside the silicon substrate and are distributed around the peak depth depending on the acceleration energy. Thereafter, a heat treatment is performed at 850 ° C. for 30 minutes in a nitrogen atmosphere to diffuse and activate boron in silicon, thereby forming a diffusion layer 45 serving as a source / drain region, as shown in FIG.

However, even with this method, it is difficult to form a diffusion layer having a depth of 0.1 μm or less. For example, when BF ²⁺ ions are implanted at an acceleration voltage of 20 keV and a doping amount of 5 × 10 ¹⁵ cm ⁻² , the diffusion layer depth x (the width of the region having a boron concentration of 1 × 10 ¹⁷ cm ⁻³ or more) is Immediately after ion implantation, 0.125 μm, and heat treatment in a nitrogen atmosphere at 850 ° C. for 30 minutes yields 0.175 μm.

  Thus, when a fine device having a channel length of about 0.1 μm such as 1 Gbit (RAM) is formed, a shallow diffusion layer having a diffusion layer depth of 0.1 μm or less is required. Have difficulty.

  Further, when the dose of ion implantation is lowered, there arises a problem that the parasitic resistance of the MOS transistor increases.

  As another method of making the edge of the source / drain diffusion layer shallow and highly concentrated, a thin film containing impurities is deposited after forming a sidewall gate insulating film, and solid phase diffusion is performed using this thin film as a diffusion source. There is a method of forming a source / drain diffusion layer.

In order to solve this problem, impurities are adsorbed and diffused on the surface of the silicon substrate from a gas containing impurities, or an impurity-added silicon film containing impurities is deposited. A diffusion method is proposed. For example, there is a method in which boron is adsorbed on the silicon surface from the thermal decomposition of diborane (B ₂ H ₆ ) and diffused in the silicon substrate.

  According to this method, the concentration of boron in the diffusion layer can be increased by the heat treatment temperature, that is, by increasing the heat treatment temperature. The depth of the diffusion layer can be determined by the heat treatment temperature and time after adsorption. That is, the extension of the depth of the diffusion layer due to an increase in the heat treatment temperature can be suppressed by shortening the heat treatment time. Therefore, it is an effective method for forming a shallow and high-concentration diffusion layer.

  However, in the method using the thermal decomposition of impurities, the impurities are adsorbed also in a region other than the silicon surface, and it is necessary to remove the impurity layer adsorbed in the region other than the silicon surface in a subsequent process.

In addition, a diffusion layer is formed in the thermal diffusion method of diborane or the method of diffusing impurities from a material serving as a diffusion source using a boron-added silicon film using diborane and silane (SiH ₄ ) or disilane (Si ₂ H ₆ ). When the surface of the silicon to be exposed is exposed to the atmosphere, a natural oxide film is formed, which inhibits impurity diffusion.

  For this reason, it is necessary to clean the surface of the silicon substrate before forming a material to be a diffusion source.

  Further, since the boron distribution after the heat treatment follows a complementary error function, the boron concentration near the bonding interface is lower than the surface concentration, and the diffusion layer resistance is increased. For example, under the condition that the diffusion layer depth can be 0.075 μm, the value of the sheet resistance is 250Ω / □.

  In addition, this method has a problem that the impurity concentration immediately below the sidewall gate insulating film is particularly low at the end of the gate electrode, and this low impurity concentration region becomes the series resistance of the transistor, thereby increasing the parasitic resistance. .

  Further, when a method of forming a silicide film on the source / drain diffusion layer is used, it is required that the diffusion layer has a certain depth or more before the formation of the silicide film.

  In general, as a method of forming a silicide film, a method of forming a refractory metal film on a silicon substrate by sputtering and reacting the refractory metal film with silicon in a source / drain diffusion layer is used. This is because silicon in the source / drain diffusion layer is consumed during the formation of the film, and the diffusion layer depth decreases.

  Another reason is that the interface between the metal film and the source / drain diffusion layer has irregularities, so that a point defect may pass through the source / drain diffusion layer and enter the substrate due to a reaction during the formation of the silicide film. It may be diffused to deteriorate the bonding characteristics.

  In order to solve such problems, a method called elevated source / drain has been proposed. In this method, after the source / drain diffusion layer is formed by ion implantation, the height of the source / drain diffusion layer is raised by selective growth of silicon.

  According to this method, the silicide technique can be applied without increasing the depth of the diffusion layer. However, there is a problem that a selective growth process of silicon is added and the manufacturing process is increased.

  In addition, by thinning the silicon film of the SOI substrate, when the MOSFET is formed, the entire silicon film is depleted, and excellent performance such as suppression of the short channel effect and improvement of current driving capability can be obtained. Sex was found.

  FIG. 48 is a process sectional view showing a method of forming a MOS transistor using a conventional SOI substrate.

  First, as shown in FIG. 48A, the element isolation insulating film 24 is formed on the SOI silicon film 22 of the SOI substrate (silicon support plate 21, SOI insulating film 22, SOI silicon film 23). Next, a gate portion including the gate oxide film 29, the doped polycrystalline silicon film 25, the tungsten silicide film 26, the side silicon nitride film 27, and the upper silicon nitride film 8 is formed.

  Next, as shown in FIG. 48B, after implanting impurity ions 30 using the gate portion as a mask, the impurity ions 30 are activated by heat treatment as shown in FIG. 31 is formed.

  However, the method for forming such a MOS transistor has the following problems.

  In this forming method, since the source / drain diffusion layer 31 is formed by ion implantation, the source / drain diffusion layer 31 is gradually doped with impurities in the lateral direction from the bottom of the side silicon nitride film 27 to the gate edge. A profile with decreasing concentration occurs.

  For this reason, the resistance of the source / drain diffusion layer 31 increases as a whole, and there arises a problem that the parasitic resistance between the two source / drain diffusion layers 31 increases and the current driving capability decreases. This problem becomes more serious as the SOI silicon film 23 becomes thinner.

  Further, when the semiconductor film of the SOI substrate is formed of silicon like the MOS transistor, the drain voltage is increased with the gate voltage being 0 or the MOS transistor being OFF, particularly in the n-channel MOS transistor. Then, a minute leak current is generated and a subthreshold current flows.

  As a result, holes are generated by impact ionization due to the subthreshold current, and the holes accumulate in the lower part of the channel to increase the potential, thereby causing a phenomenon in which electrons are injected from the source. Such a phenomenon causes a decrease in the source / drain breakdown voltage at the OFF time. In addition, there is a problem that the subthreshold characteristic is deteriorated.

  As described above, in the conventional MOS transistor technology, for example, when further miniaturization by the LDD structure is advanced, there is a problem that the resistance of the source / drain diffusion layer increases and the parasitic resistance increases. Also, in the case of the method of forming the source / drain diffusion layer by solid phase diffusion, there is a problem that the concentration of the source / drain diffusion layer at the end of the gate electrode is lowered and the parasitic resistance is increased.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device having a shallow high-concentration source / drain layer.

In order to achieve the above object, a semiconductor device according to the present invention includes a substrate having a surface region made of silicon, a gate insulating film formed on the surface region, and a gate electrode formed on the gate insulating film. And a sidewall insulating film provided on both sides of the gate electrode, and a silicon film containing impurities in a groove formed in the surface of the substrate in a portion from the bottom of the sidewall insulating film toward the outside of the sidewall insulating film And an impurity concentration of the silicon film at the bottom of the trench is 1 × 10 ¹⁹ cm ⁻³ or more and 1 × 10 ²² cm ^−3. In the following, the impurity concentration of the silicon film along the depth direction of the groove is constant, and the source and drain layers of the buried type are formed under the sidewall insulating film. Buried A buried source and drain layer, and a second buried source and drain layer formed outside the sidewall insulating film and thicker than the first buried source and drain layer. It is characterized by that.

  Here, the semiconductor substrate is, for example, a silicon substrate or an SOI substrate. In this case, the semiconductor region is the silicon substrate itself or a silicon film constituting the SOI substrate.

  The source / drain layer according to the present invention is not formed by introducing impurities into the surface of the semiconductor region by a method such as ion implantation or solid phase diffusion, and the semiconductor layer of the semiconductor region is formed on the surface of the semiconductor region. It is formed by embedding a semiconductor layer containing another impurity.

  Such a semiconductor layer can be formed by, for example, a CVD method, and can be a thin semiconductor layer having a uniform impurity concentration and a high concentration. For this reason, unlike the case of using ion implantation, solid phase diffusion or the like, a high concentration shallow source / drain layer can be formed even if miniaturization proceeds. Therefore, even if miniaturization progresses, the occurrence of the channel effect can be effectively prevented, and a highly reliable semiconductor device can be realized.

  Further, the source / drain layer formed on the SOI substrate has impurities on the surface of the SOI semiconductor film on the substrate (SOI substrate) in which the semiconductor film (SOI semiconductor film) is formed on the insulating film (SOI insulating film). It is not formed by ion implantation, but is formed by embedding a semiconductor layer containing impurities different from the semiconductor film on the surface of the SOI semiconductor film.

  Therefore, even if miniaturization progresses, a high concentration shallow source / drain layer can be formed. Therefore, even if miniaturization progresses, the occurrence of the channel effect can be effectively prevented, and a highly reliable semiconductor device can be realized.

  Furthermore, the present inventors can determine whether the etching shape can be controlled in this way by combining the step of isotropically etching silicon and the step of anisotropically etching in which etching proceeds in a different plane orientation. In order to investigate in advance, the following experiment was conducted.

The isotropic etching was performed by supplying a mixture gas of CF ₄ gas and oxygen to the sample after microwave discharge.

For anisotropic etching in which etching proceeds while forming facets, a method of supplying a gas containing Cl, for example, ClF ₃ gas, which is considered to be mainly acting on the etching, to the sample was used.

Here, in a method using a different plane orientation, for example, ClF ₃ gas, at the time of etching, the etching can be performed in the direction parallel to the silicon substrate and the (111) plane of the silicon substrate. That is, etching can be performed while providing a taper.

First, the results when anisotropic etching using ClF ₃ gas and isotropic etching using a mixed gas of CF ₄ gas and oxygen are combined are shown.

  Forming a thermal oxide film on a silicon substrate having a (100) plane orientation, patterning the oxide film, anisotropically etching silicon in different plane orientations, and etching the silicon isotropically The etching shape was observed with a scanning electron microscope.

  Here, FIGS. 38A to 38E show etching shapes when the etching depth of anisotropic etching is changed. Etching was set to 100 nm as a whole, and the etching depth by anisotropic etching was set to 100 nm, 75 nm, 50 nm, and 0 nm for each of FIGS.

  As can be seen from this result, the etching shape can be freely controlled.

  Further, the etching shape by anisotropic etching when the plane orientation on the silicon substrate was changed little by little from (100) was examined. FIGS. 39A to 39C show the etching shapes when using a substrate tilted by 10 °, 20 °, and 30 ° in the (110) plane direction from the (100) plane.

  In any case, since the etching proceeds in the (111) plane orientation, it can be seen that the etching angle can be changed depending on the plane orientation on the substrate.

  From the above results, the present invention combines the step of isotropically etching silicon and the step of anisotropically etching silicon in a different plane orientation as shown in FIGS. 38 (b) to (d). By changing the plane orientation of the substrate, the etching profile and the etching can be performed while providing a taper just under the insulating film of the gate electrode, so that the lateral impurity profile can be controlled.

  Next, the results when RIE (Reactive Ion Etching) using a mixed gas of HBr and oxygen is combined are shown. Here, in RIE using a mixed gas of HBr and oxygen, vertical etching using a silicon oxide film as a mask can be performed. After forming the shape of FIG. 38C, RIE using a mixed gas of HBr and oxygen was performed.

  The result at this time is shown in FIG. From this figure, it can be seen that only the region without the insulating film can be etched, and the shape under the insulating film and the shape of the region not covered with the sidewall insulating film can be controlled independently.

  According to the present invention, since a high-concentration shallow source / drain layer can be realized, the channel effect of the MOS transistor can be effectively prevented even if miniaturization proceeds.

  Hereinafter, embodiments will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

  First, as shown in FIG. 1A, an element isolation insulating film 102 is formed on the surface of an n-type silicon substrate 101 having a specific resistance of 4 to 5 Ωcm by a well-known method. A silicon oxide film is formed as the insulating film 103.

  Next, as shown in FIG. 2A, after a polycrystalline silicon film 104 to be a gate electrode is formed on the gate insulating film 103, an impurity is added to the polycrystalline silicon film 104 by a thermal diffusion method or the like. Next, after depositing a silicon oxide film 108 on the entire surface, the silicon oxide film 108 and the polycrystalline silicon film 104 are patterned by the RIE method to form a gate portion.

  Next, as shown in FIG. 6A, a silicon oxide film to be a sidewall gate insulating film 106 is deposited on the entire surface, and then etched back by RIE to selectively leave the silicon oxide film on the sidewall of the gate portion. Thus, the sidewall gate insulating film 106 is formed.

  Next, as shown in FIG. 6A, after removing the gate insulating film 103 in the region other than the gate portion (source / drain region), the sample is dipped in the HF solution, and the dissolved oxygen amount is 10 ppm or less. A chemically active silicon surface is exposed by rinsing the substrate in pure water.

  Here, when pure water with a large amount of dissolved oxygen is used, a natural oxide film is formed on the silicon surface during rinsing and subsequent drying, so that uniform etching cannot be performed and smooth etching is performed. The surface cannot be obtained. Therefore, it is desirable to use pure water with a small amount of dissolved oxygen, such as 10 ppm or less.

  Thereafter, etching and film formation can be performed continuously, and the substrate is placed in the etching chamber of the reduced-pressure reactor comprising the etching chamber and the film formation chamber connected to each other.

Next, the substrate is cooled or heated to a predetermined temperature of 0 ° C. to 700 ° C. in the etching chamber. Subsequently, carbon tetrafluoride (CF ₄ ) is allowed to flow at 1 to 500 cc / min. After the flow rate and pressure are stabilized, microwave discharge is performed, and the generated active species is supplied to the substrate.

As a result, silicon and fluorine radicals mainly react on the silicon surface, desorb from the silicon surface in the form of silicon tetrafluoride (SiF ₄ ), and etching proceeds. As a result, as shown in FIG. 1B, the surface of the silicon substrate 101 in the source / drain region is etched by a predetermined depth, and a groove 105 is formed on the substrate surface. The etching rate was 1 to 20 nm / min.

  Next, the substrate is transferred to the film formation chamber in vacuum or in a non-oxidizing gas, and heated to a predetermined film formation temperature of 300 ° C. to 550 ° C.

Next, 10-100 cc / min of disilane gas (Si ₂ H ₆ ) and 0.1-100 cc / min of diborane gas (B ₂ H ₆ ) are flowed. The Si ₂ H ₆ and B ₂ H ₆ are thermally decomposed only on the silicon surface, and an amorphous boron-added silicon film 107 is selectively formed on the exposed surface of the silicon substrate 101 as shown in FIG. To deposit.

The deposition rate at this time was 1 to 10 nm / min. Further, depending on the flow rate ratio of Si ₂ H ₆ and B ₂ H ₆ at this time, the boron concentration of the deposited amorphous boron-added silicon film is a desired concentration of 1 × 10 ¹⁹ to 1 × 10 ²² atoms / cm ^3. Can be. Further, the diborane gas can be determined with good controllability by diluting it to a desired concentration with an inert gas such as helium.

  When the amorphous boron-added silicon film 107 deposited in this way is subjected to solid phase growth at 600 ° C. for 2 hours, as shown in FIG. 1D, a p-type source / drain made of an amorphous boron-added silicon film is formed. Layers 110 and 111 are formed. Since these p-type source / drain layers 110 and 111 do not have facets, there is no fear of adversely affecting subsequent processes such as a source / drain electrode forming process. Although not distinguished here, when actually used, one of the p-type source / drain layers 110 and 111 is a source and the other is a drain. The same applies to the other embodiments.

When the etching depth is 50 nm and an amorphous boron-added silicon film containing 3 × 10 ²⁰ atoms / cm ^{3 of} boron is grown to 50 nm, the sheet resistance of the source / drain layer is measured. It was □.

  Furthermore, as a result of analyzing the depth direction of the boron by SIMS on this sample, the junction depth and the etching depth coincide with each other, and the boron concentration rapidly decreases at the junction interface, and a steep concentration profile is obtained. I confirmed.

  In this way, it is possible to form shallow and high-concentration p-type source / drain layers 110 and 111 with extremely good controllability and selectivity.

  Next, as shown in FIG. 1E, a titanium film is formed on the p-type source / drain layers 110 and 111 by sputtering, and then heat-treated at 700 ° C. for 30 seconds by RTA to form a titanium silicide film 109.

  Next, as shown in FIG. 5E, silicon oxide films 112 and 113 are sequentially deposited by the CVD method, then contact holes are formed by the RIE method, and boron as source / drain electrodes 114 and 115 is added thereto. A silicon film is deposited. Although not distinguished here, in actual use, one of the source / drain electrodes 114 and 115 becomes a source electrode and the other becomes a drain electrode. The same applies to the other embodiments.

The boron-added silicon films as the source / drain electrodes 114 and 115 can also be selectively deposited only in the contact holes by performing the CDE of CF _{4 in} the same manner.

  Here, a titanium silicide film is used as a silicide film, but the present invention is not limited to this. For example, a nickel silicide film or a cobalt silicide film can provide the same effect.

(Second Embodiment)
FIG. 2 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. This is an example in which the present invention is applied to a direct contact, and specifically, an example of selective formation of a boron-added silicon layer.

First, as shown in FIG. 2A, a resist pattern (not shown) is formed on an n-type silicon substrate 131, and using this as a mask, for example, BF ^{2 +} is ion-implanted into the n-type silicon substrate 131. Thus, the p-type impurity diffusion layer 133 is formed.

  Next, after removing the resist pattern, as shown in FIG. 5A, a silicon oxide film 132 having a thickness of 600 nm is deposited on the entire surface by CVD, followed by silicon oxide on the p-type impurity diffusion layer 133. A part of the film 132 is removed by etching by RIE to form a contact hole.

  Thereafter, etching and film formation can be performed continuously, and the substrate is placed in the etching chamber of the reduced-pressure reactor comprising the etching chamber and the film formation chamber connected to each other.

Next, fluorine radicals are supplied to the substrate surface for about 1 minute by microwave discharge at a CF ₄ flow rate of 25 cc / min and a pressure of 0.3 Torr [× 133 Pa]. At this time, the p-type impurity diffusion layer 133 in the contact hole is etched by about 10 nm.

  Thereafter, the substrate is transferred to the film forming chamber in a vacuum or in a non-oxidizing atmosphere, and then the substrate is heated to a predetermined temperature of 300 ° C. to 550 ° C.

Next, 10-100 cc / min of disilane gas (Si ₂ H ₆ ) and 0.1-100 cc / min of diborane gas (B ₂ H ₆ ) are flowed. The Si ₂ H ₆ and B ₂ H ₆ are thermally decomposed only on the surface of the p-type impurity diffusion layer 133 in the contact hole, and as shown in FIG. 2B, the contact electrode 134 is selectively formed on the surface. As a result, an amorphous boron-added silicon film is deposited.

Further, the boron concentration of the amorphous boron-added silicon film 134 to be deposited is 1 × 10 ¹⁹ to 1 × 10 ²² atoms / cm ³ depending on the flow rate ratio of Si ₂ H ₆ and B ₂ H ₆ at this time. The surface of the deposited film is smooth because the concentration can be increased and facets are not formed.

  If the amorphous boron-added silicon film thus obtained is grown in a solid phase at 600 ° C. for 2 hours and used in place of the boron-added silicon films 114 and 115 shown in FIG. The amorphous boron-added silicon film can be used as a source electrode and a drain electrode.

  Finally, as shown in FIG. 2C, a CVD polycrystalline silicon film as a wiring 135 is formed on the contact electrode 134.

  Here, in the case of the conventional method, when it is transferred from the furnace for selective growth to the CVD furnace for forming the CVD polycrystalline silicon, it is exposed to the atmosphere, so that a natural oxide film is formed on the electrode, and the contact electrode and Contact resistance with the wiring increases.

  Therefore, in this embodiment, after depositing an amorphous boron-added silicon film that is the contact electrode 134, the substrate temperature is continuously heated to 700 ° C. or higher without being exposed to the atmosphere, so that the non-selection as the wiring 135 is performed. A CVD polycrystalline silicon film is formed to prevent an increase in contact resistance due to a natural oxide film.

In the present embodiment, BF ^{2 +} ion implantation is used as a method of forming the p-type impurity diffusion layer 133 in the contact hole, but the same effect can be obtained even if this boron-added silicon film is used. .

  For example, first, a 600 nm-thick silicon oxide film is deposited on an n-type semiconductor substrate by CVD, and then the silicon oxide film on the region where the p-type impurity diffusion layer is to be formed is removed by RIE.

Next, the substrate is placed in the above-described reduced pressure reactor that can perform etching and film formation continuously, the bottom of the contact hole is etched by CF ₄ down flow, and an amorphous boron-added silicon film is selectively deposited in this region. As a result, both the p-type impurity diffusion layer and the electrode on the substrate side can form contacts with a desired boron concentration, and further, an increase in contact resistance due to the formation of a natural oxide film can be suppressed due to the continuous process.

In other methods, for example, a contact hole is first formed in the silicon oxide film by the same procedure as described above, and then the substrate surface is exposed to fluorine radicals generated by CF ₄ downflow.

Next, after depositing an amorphous boron-added silicon film, heat treatment is performed in this state at 950 ° C. for 30 minutes in a vacuum or in a non-oxidizing gas atmosphere. As a result, the amorphous boron-added silicon film is solid-phase grown, and at the same time, boron diffuses into the substrate, and a p-type impurity diffusion layer can be formed without ion implantation of BF ^{2 +} . Even if the direct contact is formed in this way, the same effect can be obtained.

FIG. 3 shows the relationship between the etching rate and the substrate temperature at a CF ₄ flow rate of 25 cc / min and a pressure of 0.3 Torr [× 133 Pa].

  From FIG. 3, it can be seen that at a substrate temperature of 0.degree. On the other hand, at a temperature of 700 ° C. or higher, selectivity cannot be maintained because a large amount of fluorine cannot remain on the oxide film as will be described later. Therefore, the substrate temperature when supplying fluorine radicals to the substrate is set to 0 ° C. to 700 ° C.

  Further, in order to suppress the formation of a natural oxide film on the silicon surface during heating, it is preferable to flow a vacuum of 1 × 10 −3 Torr or less or argon at 100 to 5000 cc / min. This is because the partial pressure of the oxidizing gas in the reduced pressure reactor (film formation chamber) is reduced. The same effect can be obtained even if a non-oxidizing gas other than argon is used as the non-oxidizing gas.

  FIG. 4 shows the relationship between the oxidizing gas partial pressure in the vacuum apparatus (film formation chamber) and the amount of oxidation at the interface between the deposited film (silicon film) and the silicon substrate.

  From FIG. 4, when an amorphous silicon film is deposited and solid-phase grown, the oxidizing gas partial pressure needs to be 1 × 10 −3 Torr or less in order to obtain a single crystal silicon film. I understand.

FIG. 5 shows the amount of oxygen at the interface between the deposited film (silicon film) and the silicon substrate, and the selectivity of the deposited film (when silicon is deposited to a thickness of 100 nm on a substrate on which an SiO ₂ film having an opening is formed on the silicon substrate). The average film thickness of the silicon film) is shown.

FIG. 5 shows that the amount of oxidation on the silicon surface must be suppressed to 1 × 10 ¹⁵ atoms / cm ² or less in order to suppress the amount of oxidation at the interface and obtain good selectivity.

  In this embodiment, the processing atmosphere is maintained in a vacuum or non-oxidizing atmosphere using a reduced pressure reactor in which the etching chamber and the film forming chamber are connected to each other, as shown in FIG. This is to suppress the oxidation of the silicon surface exposed by etching and to ensure good selectivity.

When the amount of oxygen at the interface exceeds 1 × 10 ¹⁵ atoms / cm ² , when the deposited film is solid-phase grown, it is crystallized as shown in FIG. 49, and boron is diffused from the boron-added silicon film. This is because impurity diffusion is hindered and excellent in controllability.

  FIG. 6 shows the results of studying the selectivity between the amount of fluorine on the silicon oxide film and the deposited silicon layer.

FIG. 6 shows that the fluorine amount on the silicon oxide film needs to be 7 × 10 ¹⁴ atoms / cm ² or more in order to obtain good selectivity.

FIG. 7 shows the result of XPS analysis of the change in the amount of fluorine on the silicon surface and oxide film surface of a sample subjected to CDE at a CF ₄ flow rate: 25 cc / min, pressure: 0.3 Torr, and substrate temperature: 25 ° C.

From FIG. 7, the fluorine on the silicon surface is desorbed as SiFx by raising the temperature of the substrate, and decreases to about 1 × 10 ¹⁴ atoms / cm ^{2 at} 500 ° C. In contrast, about 1 × 10 ¹⁵ atoms / cm ² of fluorine remains on the oxide film even at around 500 ° C.

  When an amorphous boron-added silicon film was deposited at a substrate temperature of 500 ° C. on the sample etched under these conditions, it was confirmed that it could be selectively deposited only on the silicon surface as shown in FIG. As described above, since the amorphous film is deposited, the facet of the (111) plane is not formed unlike the selective epitaxial growth, and the end has a rounded shape.

  FIG. 8 shows the relationship between the deposition time (film formation time) and the film thickness of each amorphous boron-added silicon film formed on the silicon surface and the oxide film when the film is formed at 500 ° C. as an example.

FIG. 8 shows that no boron-added silicon film is deposited on the oxide film for about one hour after Si ₂ H ₆ and B ₂ H ₆ start to flow, and about 200 nm of amorphous boron-added silicon on the silicon surface. It can be seen that the film grows selectively.

Further, when the boron-added silicon film was deposited at 600 ° C. under the same conditions as described above, the fluorine amount on the oxide film was 8 × 10 ¹⁴ atoms / cm ² , and the deposited film was as shown in FIG. Thus, a selective epitaxial growth film having facets is formed.

When the temperature is further raised, especially at 700 ° C. or higher, the fluorine amount on the oxide film becomes 2 × 10 ¹⁴ atoms / cm ² or less as shown in FIG. 7, and the selectivity is greatly lost, and polycrystalline silicon is also formed on the oxide film. Layer deposition occurs.

FIG. 9 shows the substrate temperature and the deposition rate of the boron-added silicon layer deposited on the silicon surface when the Si ₂ H ₆ flow rate is 100 cc / min and the B ₂ H ₆ (1% He dilution) flow rate is 5 cc / min. The relationship is shown.

  When the crystallinity of the sample deposited at each substrate temperature was examined by a cross-sectional TEM, it was amorphous at 500 ° C. or lower, and was epitaxially grown at 550 ° C., and at a temperature higher than that, a single crystal silicon film was formed. It was obtained.

  Therefore, an amorphous silicon film is selectively deposited only on the silicon surface at a temperature range of 300 ° C. to 550 ° C. and a single crystal silicon film is selectively deposited at a temperature of 550 ° C. to 700 ° C. or higher.

  FIG. 10 shows the relationship between the deposition time and the film thickness when an amorphous boron-added silicon film is formed at 550 ° C. after etching under the above CDE conditions.

As shown in FIG. 7, about 1 × 10 ¹⁵ atoms / cm ² of fluorine remains on the oxide film, and, similar to FIG. 8, after Si ₂ H ₆ and B ₂ H ₆ begin to flow, A boron-added silicon film is selectively deposited for 30 minutes.

  Here, if CDE is performed for about one minute every about 20 minutes before amorphous silicon starts to be selected on the oxide film, deposition on the oxide film can be suppressed as shown in FIG.

Even if a silicon film is deposited on the oxide film, the same effect can be obtained and good selective deposition can be achieved by etching the silicon film on the oxide film by CF ₄ downflow etching.

  According to this method, it is possible to obtain an epitaxial silicon layer when the substrate temperature is in the range of 550 ° C. to 700 ° C.

In the above embodiment, CF ₄ is used as the fluorine-containing gas and the active species is supplied to the substrate by CDE. However, the present invention is not limited to this, and other halogen-based etching gases are used. It may be activated by microwave discharge to supply fluorine radicals to the substrate.

The same effect can be obtained even when a plasma-less gas containing fluorine such as chlorine trifluoride (ClF ₃ ) is used.

  For example, an opening is opened in the silicon oxide film by RIE to expose the active silicon surface, and then placed in the above-described reduced pressure reactor capable of continuously performing etching and film formation. After evacuation, 25 ° C. to 400 ° C. The substrate is heated to a predetermined temperature.

Next, after stabilizing the flow rate of nitrogen gas under appropriate conditions, for example, setting the nitrogen gas flow rate to 3000 cc / min, chlorine trifluoride gas (ClF ₃ ) is allowed to flow for 1 to 1000 cc / min.

Here, the nitrogen gas is flowed because ClF ₃ is extremely reactive with silicon and it is difficult to control the etching rate, so that ClF ₃ is diluted with nitrogen to lower the etching rate. is there. Note that the same effect can be obtained by using other inert gas.

FIG. 52 shows an SEM image of a sample etched at a ClF ₃ flow rate: 200 cc / min, an N ₂ flow rate: 3800 cc / min, a pressure: 1.0 Torr [× 133 Pa], and a substrate temperature: 300 ° C. In this case, etching is performed. It can be seen that (111) facets are formed on the surface.

Further, when the silicon oxide film of the sample etched under the same conditions was analyzed, it was confirmed that fluorine remained at 1 × 10 ¹⁵ atoms / cm ² or more.

  Next, after evacuation, the substrate is heated in vacuum or in a non-oxidizing gas to a predetermined film formation temperature of 300 ° C. to 550 ° C.

At this time, as described above, the oxidation of the silicon surface is suppressed to 1 × 10 ¹⁵ atoms / cm ² or less by the oxidizing gas such as moisture and oxygen remaining in the furnace. The reactive gas partial pressure is maintained at 1 × 10 −3 Torr [× 133 Pa].

Next, Si ₂ H ₆ is supplied at 10 to 100 cc / min, and B ₂ H ₆ is supplied at 0.1 to 100 cc / min.

At this time, Si ₂ H ₆ and B ₂ H ₆ are decomposed and suppressed by fluorine remaining on the silicon oxide film on the silicon oxide film, and no boron-added silicon film is deposited. Only the silicon surface can be selectively grown.

In FIG. 11, after etching under conditions of substrate temperature: 300 ° C., ClF ₃ : 200 cc / min, nitrogen gas: 3800 cc / min, substrate temperature: 350 ° C., Si ₂ H ₆ : 100 cc / min, and 10% with helium. The relationship between the deposition time and the film thickness when a boron-added silicon film is grown under the condition of diluted B ₂ H ₆ : 20 cc / min is shown.

From FIG. 11, in about 30 minutes after starting to flow Si ₂ H ₆ and B ₂ H ₆ , no boron-added silicon film was deposited on the silicon oxide film, and about 1500 angstroms of boron-added silicon was formed on the silicon surface. It can be seen that the film grows selectively.

FIG. 12 shows the substrate temperature: 300 ° C., the ClF ₃ flow rate: 200 cc / min, the N ₂ flow rate: 3800 cc / min, the substrate temperature: 350 ° C., the Si ₂ H ₆ flow rate: 100 cc / min, B ₂ H ₆ diluted to 10% with helium: a step of growing boron-added silicon for 15 minutes under a condition of 20 cc / min, a step of flowing ClF ₃ flow rate: 200 cc / min, N ₂ flow rate: 3800 cc / min for 30 seconds, The relationship between the film thickness of the boron-added silicon film deposited on the silicon surface and the silicon oxide film and the deposition time when the above is repeated several times is shown.

  12 that growth of the boron-added silicon film on the silicon oxide film can be suppressed.

As described above, the case where ClF ₃ is used has been described as an example here, but the same effect can be obtained even when other gas containing fluorine is used.

Further, although disilane (Si ₂ H ₆ ) and diborane (B ₂ H ₆ ) are taken as examples of the boron-added silicon film growth gas, the present invention is not limited to this, but includes silane (SiH ₄ ) and the like. SiH ₂ Cl ₂ , SiCl ₄ , SiF ₄ , Si ₂ H ₄ Cl ₂ , SiH ₂ F ₂ , Si ₂ H ₂ Cl ₄ , Si ₂ Cl ₆ , Si ₂ H ₄ F ₂ , Si ₂ H ₂ F ₄ , Si ₂ F ₆ , further BF ₃ , BCl ₃ may be used.

In the case of forming an n-type impurity diffusion layer, the same effect can be obtained by using a phosphine (PH ₃ ), arsine (AsH ₃ ), or a halide containing phosphorus or arsenic.

  Moreover, it can be implemented not only by deposition by simple thermal decomposition reaction but also by combining methods for promoting dissociation reaction such as light irradiation.

In addition, although an oxide film (SiO ₂ ) is used as the insulating film, the present invention is not limited to this, and the same effect can be obtained with other insulating films such as PSG, BSG, BPSG, Si ₃ N ₄ .

(Third embodiment)
15 and 16 are process cross-sectional views illustrating a method of manufacturing a p-channel MOS transistor according to the third embodiment of the present invention.

  First, as shown in FIG. 15A, for example, an n-type silicon substrate 201 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is prepared, and the surface of the n-type silicon substrate 201 is formed by a normal selective oxidation method. An element isolation insulating film 202 having a thickness of about 0.6 μm is formed.

  Next, as shown in FIG. 6A, a gate oxide film 203 having a thickness of 10 nm is formed by thermal oxidation, and an impurity-doped polycrystalline silicon film 204 having a thickness of 100 nm as a gate electrode is formed thereon, and a 300 nm-thickness is formed. A tungsten silicide film 205 is sequentially formed.

  Next, as shown in FIG. 5A, after a silicon oxide film 206 having a thickness of 150 nm is formed on the entire surface by LPCVD, these stacked films are etched by reactive ion etching to form a gate portion. .

  Next, as shown in FIG. 15B, a sidewall gate insulating film 207 made of a silicon nitride film having a thickness of about 100 nm is formed on the sidewall of the gate portion. The sidewall gate insulating film 207 is obtained, for example, by depositing a silicon nitride film having a thickness of 50 nm on the entire surface by the CVD method and then etching the entire surface by anisotropic dry etching.

Next, as shown in FIG. 15C, the surface of the silicon substrate 201 in the source / drain regions is selectively and isotropically etched so that the total etching depth is 50 nm. This etching is performed, for example, by discharging a mixed gas of CF ₄ and oxygen by microwaves and then supplying the mixture onto the sample.

  Next, as shown in FIG. 16A, a silicon thin film 208 having a thickness of 100 nm containing 2% boron is selectively deposited only on the source / drain regions where the surface of the silicon substrate 201 is exposed.

The selective deposition at this time is performed, for example, using a mixed gas of SiH ₂ Cl ₂ and BCl ₃ and setting the substrate temperature to 800 ° C. Thereby, a high concentration p-type source / drain diffused layer 209 can be formed. Here, the boron concentration in the deposited layer needs to be at least 10 ¹⁹ cm ⁻³ in order to form the low-resistance p-type source / drain diffused layer 209.

  Thereafter, as shown in FIG. 16B, a silicon oxide film 213 having a thickness of 300 nm is deposited on the entire surface by a CVD method, and then a contact hole is opened in the silicon oxide film 313 by anisotropic dry etching.

  Next, as shown in FIG. 16B, after depositing an 800 nm-thick aluminum film containing 0.5% of silicon and copper, for example, this is patterned to form source / drain electrodes 214. . Thereafter, heat treatment was performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% hydrogen.

  The characteristics of such a MOS transistor were compared with a sample in which the thickness of the silicon thin film 208 to be the source / drain layer 209 was changed.

  FIG. 17 shows the result of examining the state of change in the drain current with respect to the drain voltage of the MOS transistor when the deposition thickness is 50 nm, 100 nm, and 150 nm.

  As can be clearly seen from this result, it can be seen that when the deposition thickness is reduced to 50 nm, only a low drain current value is obtained as compared with the case where the same drain voltage is applied. This is because the deposited film thickness, that is, the thickness of the source / drain layer is thin, so that this resistance component acts as a series resistance, and the drain current value is lowered.

  On the other hand, when the deposition thickness is increased to a certain extent, such as 100 nm or more, since what determines the series resistance value is another factor, there is no significant difference in the drain current value.

  The required value for the deposited film thickness varies depending on the structure of the transistor, etc., but generally, a silicon thin film having a thickness that is thicker than the silicon substrate surface before etching, that is, thicker than the etched depth is deposited. Thus, the effect of reducing the parasitic resistance can be obtained.

  This is because the cross-sectional area of the source / drain layer (the area of the cross section perpendicular to the substrate surface) is effectively increased, and a lower resistance value can be obtained than when doping is performed using the ion implantation method. is there.

  In this embodiment, boron-containing silicon is deposited to form a p-channel MOS transistor. However, to form an n-type MOS transistor, silicon containing phosphorus or arsenic is used instead of boron. Just deposit. Further, by combining them, a CMOS transistor can be formed as described later.

(Fourth embodiment)
FIG. 18 is a process sectional view showing a method of manufacturing a p-channel MOS transistor according to the fourth embodiment of the present invention.

  First, the manufacturing process up to FIG. 16A of the fourth embodiment is performed.

  Next, as shown in FIG. 18A, a titanium thin film 210 having a thickness of 25 nm and a titanium nitride thin film 211 having a thickness of 50 nm are sequentially deposited on the entire surface by sputtering.

  Next, as shown in FIG. 18B, the titanium thin film 210 is completely reacted with the silicon substrate 201 by heat treatment at 700 ° C. for 1 minute in a nitrogen atmosphere, and the titanium silicide film 212 is formed only on the source / drain regions. Form. Thereafter, for example, the titanium nitride film 211 and the unreacted titanium thin film 210 on the element isolation insulating film 202 are selectively separated with an aqueous solution of hydrofluoric acid or a mixed solution of sulfuric acid and hydrogen peroxide.

  Next, as shown in FIG. 18C, after a silicon oxide film 213 having a thickness of 300 nm is deposited on the entire surface by a CVD method, a contact hole is opened in the silicon oxide film 213 by anisotropic dry etching.

  Next, as shown in FIG. 3C, after depositing an 800 nm thick aluminum film containing 0.5% of silicon and copper, for example, the aluminum film is patterned to form source / drain electrodes 214. To do. Thereafter, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% hydrogen.

  The characteristics of this MOS transistor were compared with a sample in which the deposition thickness of the silicon thin film deposited to form the source / drain layers was changed.

  FIG. 19 shows the result of investigating how the drain current changes with respect to the gate voltage of MOS transistors having deposited silicon thin films of 50 nm, 100 nm, and 150 nm.

  From FIG. 19, it can be seen that when the deposition thickness is reduced to 50 nm, the drain current value is higher even when no gate voltage is applied than when the deposition thickness is larger (100 nm, 150 nm). I understand.

  FIG. 20 is a characteristic diagram showing the relationship between the thickness of the silicon film (source / drain layer) and the drain current. This is the result when the thickness of the titanium thin film is 25 nm, the gate voltage is 0 V, and the drain voltage is 3.3 V.

  As can be seen from FIG. 20, a certain amount of deposited film thickness is necessary to keep the drain current value low. This is because silicon on the substrate surface is consumed by the reaction between titanium and silicon (the film thickness of titanium consumed is about 2.2 times that of titanium film thickness 1).

  When the deposited film thickness is small, the position of the junction depth of the source / drain layer and the interface between the source / drain layer and the silicide film are close to each other. As a result, leakage current flows.

  On the other hand, when the deposition thickness is increased to a certain extent, such as 100 nm or more, the distance between the position of the junction depth and the interface between the source / drain layer and the silicide film can be secured to some extent. The value of can be kept low.

  In the present embodiment. Although the case where titanium is used as the metal for forming the silicide has been described, the same effect can be obtained by using any other metal such as nickel, cobalt, platinum, vanadium, and palladium.

  However, the thickness of silicon consumed by silicide formation differs depending on the metal. Therefore, in order to suppress drain current leakage, pay attention to the thickness of the silicon film as the source / drain layer and the metal film that will become the silicide film. Need to pay. At least the silicon film needs to be thicker than the thickness corresponding to the amount of silicon consumed with silicidation.

  In addition, according to the third and fourth embodiments (embedding the source / drain layers), the shallow and low-resistance source / drain layers are formed which are required as the elements of the MOS integrated circuit are miniaturized. I was able to confirm that I could do it.

  As for the number of manufacturing steps, in the case of the fourth embodiment, after the formation of the sidewall gate insulating film and before the formation of the silicide film, (1) etching of the source / drain regions, and (2) the etching depth. It is only necessary to deposit thick doped silicon. On the other hand, in the case of the conventional method, (1) ion implantation before forming the gate sidewall insulating film, (2) ion implantation after forming the gate sidewall insulating film, and (3) recovering defects caused by the ion implantation. Heat treatment, and (4) deposition of a silicon film is necessary. From this, it can be seen that the structure of the present invention (buried source / drain layer) is advantageous for reducing the number of manufacturing steps. That is, this structure is a structure in which a high concentration and shallow source / drain layer can be easily formed.

(Fifth embodiment)
FIG. 21 is a process cross-sectional view illustrating a method of manufacturing a MOS transistor using an SOI (Semiconductor On Insulator) substrate according to the fifth embodiment of the present invention.

  In the present embodiment and the following other embodiments, a case where a silicon oxide film and a silicon film are mainly used as an SOI insulating film and an SOI semiconductor film, respectively, will be described. However, other insulating films and semiconductor films are used. May be.

  First, as shown in FIG. 21A, an SOI substrate in which a silicon oxide film (SOI insulating film) 302 and an n-type silicon layer (SOI semiconductor film) 303 are sequentially provided on a silicon support 301 is prepared. For example, the n-type silicon layer 303 has a plane orientation (100), a specific resistance of 4 to 6 Ωcm, and a thickness of 50 nm.

  Next, as shown in FIG. 6A, a trench is formed in the n-type silicon layer 303 by RIE, a silicon oxide film is embedded using an organic silicon compound such as TEOS, and then heat treatment is performed at a high temperature. Then, a normal buried element isolation insulating film 304 is formed.

  Next, as shown in FIG. 6A, after forming a gate oxide film 309 having a thickness of 10 nm by thermal oxidation, an impurity-doped polycrystalline silicon film 305 having a thickness of 70 nm as a gate electrode is formed thereon, and a thickness of 20 nm. The tungsten silicide film 306 is sequentially formed, and a silicon oxide film 308 having a thickness of 10 nm is formed on the surface by LPCVD. Thereafter, these laminated films are etched by RIE to form gate portions.

  Next, as shown in FIG. 6A, after depositing a silicon nitride film having a thickness of 50 nm to be the sidewall gate insulating film 307 on the entire surface by the CVD method, the silicon nitride film is deposited on the entire surface by an anisotropic dry etching method. By etching, the sidewall gate insulating film 307 is formed.

  Next, as shown in FIG. 21B, the surface of the n-type silicon layer 303 in the source / drain region is selectively isotropically etched so that the etching depth becomes 40 nm.

Here, the etching is performed, for example, by supplying fluorine radicals obtained by discharging CF ₄ gas with microwaves to the substrate. Also, the underlying silicon oxide film 302 is not exposed during etching.

  Next, as shown in FIG. 21C, a p-type source containing boron, which is a p-type impurity, selectively only on the silicon surface exposed continuously (by a continuous vacuum process) without exposing the substrate to the atmosphere. A silicon film as the drain layer 312 was deposited with a thickness of 50 nm.

This selective deposition is performed, for example, using a mixed gas of Si ₂ H ₆ and B ₂ H ₆ at a substrate temperature of 300 ° C. In addition, the silicon film deposited under these conditions is in an amorphous state and no facets appear.

Here, if the substrate temperature during deposition is 550 ° C. or higher, the resulting silicon film becomes a selective epitaxial growth film. Further, the boron concentration contained in the silicon film is required to be at least 1 × 10 ¹⁹ / cm ³ in order to form a low resistance source / drain layer. A silicon film having such a concentration can be obtained by controlling the mixing ratio of Si ₂ H ₆ and B ₂ H ₆ .

  Next, as shown in FIG. 21 (d), a titanium thin film having a thickness of 30 nm and a titanium nitride thin film having a thickness of 50 nm are sequentially deposited on the entire surface by sputtering, and then heat-treated at 700 ° C. for 1 minute in a nitrogen atmosphere. All of the titanium thin film is reacted with the silicon layer to form a titanium silicide film 313 only in the source / drain regions.

  Thereafter, only the titanium nitride thin film and the unreacted titanium thin film on the insulating film are selectively peeled off by, for example, an aqueous solution of hydrofluoric acid or a mixed solution of sulfuric acid and hydrogen peroxide.

  Next, as shown in FIG. 21E, after depositing a silicon oxide film 314 having a thickness of 300 nm on the entire surface by CVD, a contact hole is opened in the silicon oxide film 314 by anisotropic dry etching.

  Next, as shown in FIG. 21E, after an aluminum film having a thickness of 800 nm containing, for example, 0.5% each of silicon and copper is deposited. The aluminum film is patterned to form source / drain electrodes 315. Thereafter, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 100% hydrogen.

  Also in this embodiment, as in the previous embodiment, by embedding the source / drain layers, it becomes possible to form a high-concentration shallow source / drain layer even if the miniaturization progresses. However, the channel effect can be effectively prevented.

(Sixth embodiment)
FIG. 22 is a process cross-sectional view illustrating a method of manufacturing a MOS transistor using an SOI substrate according to the sixth embodiment of the present invention.

  First, as shown in FIG. 22A, an SOI substrate made of, for example, an n-type silicon layer 303 having a plane orientation (100), a specific resistance of 4 to 6 Ωcm, and a thickness of 50 nm, as in the fifth embodiment. In use, an element isolation insulating film 304 and a gate portion are formed.

Next, as shown in FIG. 22B, for example, CF ₄ gas is discharged by microwaves, and fluorine radicals are supplied to the substrate so that the etching depth is deeper than the thickness of the n silicon layer 303. Then, the silicon oxide film 302 is exposed. As a result, etching can be performed up to the vicinity of the gate edge.

  Next, as shown in FIG. 22C, a p-type silicon film 312a containing a desired concentration of boron, which is a p-type impurity, was continuously deposited on the entire surface to a thickness of 50 nm without exposing the substrate to the atmosphere.

This deposition is performed at a substrate temperature of 300 ° C. using a mixed gas of Si ₂ F ₆ and B ₂ H ₆ , for example. Further, the silicon film deposited under these conditions is in an amorphous state and is uniformly deposited on the entire surface.

  Next, as shown in FIG. 22 (d), the silicon film 312a is etched on the entire surface by anisotropic dry etching to select the silicon film 312a on the side wall of the gate portion and the end portion of the element isolation insulating film 302. Leave behind.

  Next, as shown in FIG. 22E, a titanium thin film having a thickness of 30 nm and a titanium nitride thin film having a thickness of 50 nm are sequentially deposited on the entire surface by sputtering, and then heat-treated at 700 ° C. for 1 minute in a nitrogen atmosphere. Thus, the titanium thin film is all reacted with the n silicon layer, and the titanium silicide film 313 is formed only in the source / drain regions.

  Thereafter, the titanium nitride thin film and the unreacted titanium thin film on the insulating film are selectively peeled off by, for example, an aqueous solution of hydrofluoric acid or a mixed solution of sulfuric acid and hydrogen peroxide.

  Next, as shown in FIG. 22F, after depositing a silicon oxide film 314 having a thickness of 300 nm on the entire surface by a CVD method, a contact hole is opened in the silicon oxide film 314 by anisotropic dry etching.

  Next, as shown in FIG. 5F, after depositing an aluminum film having a thickness of 800 nm containing, for example, 0.5% each of silicon and copper, the aluminum film is patterned to form source / drain electrodes 315. To do. Thereafter, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% hydrogen.

(Seventh embodiment)
FIG. 23 is a process cross-sectional view illustrating a method of manufacturing a MOS transistor using an SOI substrate according to the seventh embodiment of the present invention.

  First, as shown in FIG. 23A, as in the fifth embodiment, for example, an SOI substrate including an n-type silicon layer 303 having a plane orientation (100), a specific resistance of 4 to 6 Ωcm, and a thickness of 50 nm is formed. In use, an element isolation insulating film 304 and a gate portion are formed.

Next, as shown in FIG. 23B, for example, CF ₄ gas is discharged by microwaves, and fluorine radicals are supplied to the substrate, so that the etching depth is deeper than the thickness of the n silicon layer 303. Then, the silicon oxide film 302 is exposed. As a result, etching can be performed up to the vicinity of the gate edge.

  Next, as shown in FIG. 23C, a silicon film 312a containing a desired concentration of boron, which is a p-type impurity, is continuously deposited to a thickness of 50 nm on the entire surface without exposing the substrate to the atmosphere.

This deposition is performed at a substrate temperature of 300 ° C. using a mixed gas of Si ₂ F ₆ and B ₂ H ₆ , for example. Further, the silicon film deposited under these conditions is in an amorphous state and is uniformly deposited on the entire surface.

  Next, as shown in FIG. 23 (d), the silicon film 312a is etched on the entire surface by anisotropic dry etching to select the silicon film 312a on the side wall of the gate portion and the end portion of the element isolation insulating film 302. Leave behind.

Next, as shown in FIG. 23E, after CF ₄ gas is discharged by microwaves and fluorine radicals are supplied to the substrate, the silicon film containing boron at a desired concentration continuously without exposing the substrate to the atmosphere. 312b is selectively deposited on the silicon film 312a.

This selective deposition is performed, for example, using a mixed gas of Si ₂ H ₆ and B ₂ H ₆ at a substrate temperature of 300 ° C. Further, the silicon film deposited under these conditions is in an amorphous state.

  Next, as shown in FIG. 23 (f), a titanium thin film having a thickness of 30 nm and a titanium nitride thin film having a thickness of 50 nm are sequentially deposited on the entire surface by sputtering, and then heat-treated at 700 ° C. for 1 minute in a nitrogen atmosphere. Thus, the titanium thin film is entirely reacted with the n-type silicon layer, and the titanium silicide film 313 is selectively formed on the source / drain regions. Thereafter, the titanium nitride thin film and the unreacted titanium thin film on the insulating film are selectively peeled off by, for example, a hydrofluoric acid aqueous solution or a mixed solution of sulfuric acid and hydrogen peroxide.

  Next, as shown in FIG. 23G, after a silicon oxide film 314 having a thickness of 300 nm is deposited on the entire surface by a CVD method, a contact hole is opened in the silicon oxide film 314 by anisotropic dry etching.

  Next, as shown in FIG. 23 (g), after depositing an 800 nm thick aluminum film containing 0.5% of silicon and copper, for example, the aluminum film is patterned to form source / drain electrodes 315. Form. Thereafter, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% hydrogen.

(Eighth and ninth embodiments)
24 and 25 are process cross-sectional views illustrating a method of manufacturing a MOS transistor using an SOI substrate according to the eighth and ninth embodiments of the present invention, respectively.

  First, as shown in FIGS. 24A and 25A, as in the fifth embodiment, for example, the n-type silicon layer 303 having a plane orientation (100), a specific resistance of 4 to 6 Ωcm, and a thickness of 50 nm is used. An element isolation insulating film 304 and a gate portion are formed using an SOI substrate made of, for example.

Next, as shown in FIGS. 24B and 25B, for example, CF ₄ gas is discharged by microwaves, and fluorine radicals are supplied to the substrate so that the etching depth is the thickness of the n silicon layer 303. A deeper etching is performed to expose the silicon oxide film 302. As a result, etching can be performed up to the vicinity of the gate edge.

  Next, as shown in FIG. 25C, a silicon film 312b containing a desired concentration of boron, which is a p-type impurity, is selectively deposited on the surface of the n-type silicon layer without exposing the substrate to the atmosphere.

This selective deposition is performed, for example, using a mixed gas of Si ₂ F ₆ and B ₂ H ₆ at a substrate temperature of 300 ° C. Further, the silicon film deposited under these conditions is in an amorphous state.

  Here, if the substrate temperature is set to 550 ° C. or higher, as shown in FIG. 24C, the resulting silicon film 312c becomes a selective epitaxial growth film.

  Next, as shown in FIGS. 24D and 25D, a titanium thin film having a thickness of 30 nm and a titanium nitride thin film having a thickness of 50 nm are sequentially deposited on the entire surface by a sputtering method, followed by 700 ° C. in a nitrogen atmosphere. The titanium thin film is all reacted with the n-type silicon layer by heat treatment for 1 minute to selectively form a titanium silicide film 313 on the source / drain regions. Thereafter, the titanium nitride thin film and the unreacted titanium thin film on the insulating film are selectively peeled off by, for example, a hydrofluoric acid aqueous solution or a mixed solution of sulfuric acid and hydrogen peroxide.

  Next, as shown in FIGS. 24E and 25E, a silicon oxide film 314 having a thickness of 300 nm is deposited on the entire surface by a CVD method, and then contact holes are formed in the silicon oxide film 314 by anisotropic dry etching. Open.

  Next, as shown in FIG. 25 (e), an aluminum film having a thickness of 800 nm containing 0.5% of silicon and copper, for example, is deposited, and then the aluminum film is patterned to form source / drain electrodes 315. Form. Thereafter, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% hydrogen.

  FIG. 26 shows a two-dimensional distribution of impurities (boron) in which the source and drain are formed by the method of the present invention and the conventional method.

  From FIG. 26, it can be seen that a steep profile can be obtained in the vicinity of the bonding position as compared with the conventional method.

  Therefore, even when the junction depth is the same, for example, the source / drain formed according to the present invention has a lower resistance, and the parasitic resistance that affects the driving capability of the MOS transistor can be reduced.

For example, FIG. 27 shows the dependence of the sheet resistance ρs on the source / drain depth xj. According to the present invention (black circle and white circle in the figure), the sheet resistance ρs is inversely proportional to xj. When the concentration is 1 × 10 ²⁴ / cm ³ , the specific resistance is 0.2 Ωcm even if xj is 20 nm, whereas the source / drain formed by conventional ion implantation (triangle, + in the figure) It is difficult to realize xj of 100 nm or less, and the sheet resistance ρs shows a high value even with the same xj.

  A ring oscillator was constructed using the CMOS inverter having the source / drain formed in the present invention, and the delay time per stage was measured. FIG. 28 shows the dependency of the delay time on the power supply voltage. For comparison, FIG. 28 also shows the result of the same measurement performed on a CMOS transistor having a source / drain formed by an ion implantation method which is a conventional method.

  Here, in the present invention, since the method of etching the SOI semiconductor film until the surface of the SOI insulating film is exposed is adopted, the effective junction depth is the thickness of the source / drain layer. On the other hand, in the conventional method, impurities are ion-implanted under the condition that the junction interface is formed deeper than the thickness of the SOI semiconductor film.

  FIG. 28 shows that the delay time in the present invention is shorter when the delay time in the case where the present invention is formed by the conventional method is compared with the same power supply voltage.

  As shown in FIG. 26, the source / drain layer formed according to the present invention has a steep profile near the junction interface as compared with the conventional method. For example, even at the same junction depth, the driving of the transistor is performed. It is possible to reduce the parasitic resistance (sheet resistance ρs) that lowers the capability. Thus, when a CMOS inverter is configured by the method of the present invention, the delay time is shortened.

(Tenth embodiment)
The present embodiment relates to a method for manufacturing an n-channel MOS transistor using an SOI substrate.

  First, as in the fifth embodiment, for example, an SOI substrate made of an n-type silicon layer having a plane orientation (100), a specific resistance of 4 to 6 Ωcm, and a thickness of 50 nm is used. Form.

Next, for example, CF ₄ gas is discharged by microwaves, and fluorine radicals are supplied to the substrate, so that the etching depth is deeper than the thickness of the n silicon layer to expose the silicon oxide film. As a result, etching can be performed up to the vicinity of the gate edge.

  Next, without exposing the substrate to the atmosphere, an SiGe film containing boron as a p-type impurity at a desired concentration is selectively formed only on the surface of the n silicon layer.

This selective deposition is performed, for example, using a mixed gas of Si ₂ H ₆ , GeH ₄ and AsH ₄ at a substrate temperature of 300 ° C. The film deposited under these conditions is in an amorphous state. However, if the substrate temperature during deposition is 550 ° C. or higher, the resulting SiGe film becomes a selective epitaxial growth film.

  Next, a titanium thin film having a thickness of 30 nm and a titanium nitride thin film having a thickness of 50 nm are sequentially deposited on the entire surface by sputtering, and then heat-treated at 700 ° C. for 1 minute in a nitrogen atmosphere, so that the titanium thin film is entirely formed of an n-type silicon layer. And a titanium silicide film is selectively formed on the source / drain regions. Thereafter, the titanium nitride thin film and the unreacted titanium thin film on the insulating film are selectively peeled off by, for example, a hydrofluoric acid aqueous solution or a mixed solution of sulfuric acid and hydrogen peroxide.

  Next, after a silicon oxide film having a thickness of 300 nm is deposited on the entire surface by CVD, a contact hole is opened in the silicon oxide film by anisotropic dry etching.

  Next, after depositing an aluminum film having a thickness of 800 nm containing, for example, 0.5% each of silicon and copper, the aluminum film is patterned to form source / drain electrodes. Thereafter, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% hydrogen.

  FIG. 29 shows the MOS transistor (SiGe film in which the source / drain layer contains impurities: FIG. 29A) and the MOS transistor (silicon film in which the source / drain layers contain impurities: FIG. 29B). ID-VD characteristics of ().

  FIG. 29 shows that when the source / drain layer is a silicon film, the breakdown voltage is low, and even when the gate voltage is 0V, the drain current flows when the drain voltage VD is 3V.

  On the other hand, when the source / drain layer is a SiGe film, the breakdown voltage is improved, and it can be seen that no drain current flows even when the MOS transistor has a drain voltage VD of 3V when the drain voltage VD is 3V.

  This is presumably because holes generated by impact ionization escape to the source side without accumulating in the lower part of the channel by using the SiGe film. The above effect can be obtained even if only the source side is a SiGe film.

In the fifth to tenth embodiments, CF ₄ is used as an example of the etching gas, but the same effect can be obtained by using other etching gas, for example, ClF _3. can get.

In the fifth to tenth embodiments, a mixed gas of Si ₂ H ₆ and B ₂ H ₆ is used as a gas for forming a silicon film containing boron, and GeH _{4 is} used as a gas for forming a SiGe film containing boron. The mixed gas of B ₂ H ₆ is taken as an example, but is not limited thereto.

That is, as the material gas containing silicon, including _{SiH 4 SiH2Cl 2, SiCl 4,} SiF 4, Si 2 H 4 Cl 2, SiH 2 F 2, Si 2 H 2 Cl 4, Si 2 Cl 5, Si 3 H ₄ F ₂ , Si ₂ H ₂ F ₄ , Si ₂ F ₆ , and higher-order hydrides of silicon may be used.

In addition to GeH ₄ as the gas containing germanium, the same effect can be obtained with a Ge hydride.

In the case of forming a p-type source-drain layer, in addition to B ₂ H _6, BF3 or it may be a BCl _3.

Further, when forming an n-type source / drain layer, the same effect can be obtained by using, for example, a halide containing PH ₃ , AsH _4, or phosphorus or arsenic.

(Eleventh embodiment)
30 to 33 are process cross-sectional views illustrating a method of manufacturing a CMOS transistor according to the eleventh embodiment of the present invention.

First, as shown in FIG. 30A, for example, an n-type silicon substrate 401 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is prepared, and the region of the n-type MOS transistor is masked with a resist 400, and p Boron is ion-implanted only in a region where the mold well layer is formed under the conditions of an acceleration voltage of 220 kV and a dose of 5 × 10 ¹³ cm ⁻² . Thereafter, heat treatment is performed in a nitrogen atmosphere at 1150 ° C. for 6 hours to form a p-type well layer 402 as shown in FIG.

  Next, as shown in FIG. 30C, an element isolation insulating film 403 having a thickness of about 0.6 μm is formed by a normal selective oxidation method.

  Next, as shown in FIG. 30D, a gate oxide film 404 having a thickness of 10 nm is formed by thermal oxidation, and an impurity-added polycrystalline silicon film 405 having a thickness of 70 nm as a gate electrode is formed thereon. A tungsten silicide film 406 is sequentially formed, and a silicon oxide film 407 having a thickness of 100 nm is formed on the surface by LPCVD.

  Next, as shown in FIG. 31A, these stacked films are etched by reactive ion etching to form a gate portion, and then a silicon nitride film 408 having a thickness of 40 nm is deposited on the entire surface by CVD. .

  Next, as shown in FIG. 6A, the region for forming the p-channel MOS transistor is covered with a resist 400 by photolithography, and then the silicon nitride film 408 is etched on the entire surface by anisotropic dry etching. A silicon nitride film 408 is left on the side wall of the gate portion of the channel MOS transistor. This silicon nitride film 408 becomes a sidewall gate insulating film of the n-channel MOS transistor. Thereafter, as shown in FIG. 31B, the resist 400 is peeled off.

  Next, as shown in FIG. 31C, the surface of the p-type well layer 402 is etched in the same direction so that the total etching depth is 40 nm.

This etching is performed, for example, by discharging a mixed gas of CF ₄ and oxygen by microwaves and supplying fluorine radicals to the substrate.

  Next, as shown in FIG. 31D, a silicon thin film having a thickness of 100 nm containing 2% arsenic is selectively deposited on the source / drain regions where the surface of the p-type well layer 402 is exposed.

This selective deposition is performed, for example, using a mixed gas of SiH ₂ Cl ₂ and ABH ₅ at a substrate temperature of 750 ° C. The silicon thin film 409 becomes a high-concentration shallow n-type source / drain layer in an n-channel MOS transistor. The arsenic concentration in the deposited layer needs to be at least 10 ¹⁹ cm ⁻³ in order to form a low resistance source / drain.

  Next, as shown in FIG. 32A, after depositing a silicon nitride film 410 having a thickness of 40 nm on the entire surface by the CVD method, a resist 400 covering the region of the n-channel MOS transistor is formed by photolithography.

  Next, as shown in FIG. 6A, the silicon nitride films 410 and 408 are etched on the entire surface by anisotropic dry etching to leave the silicon nitride films 410 and 408 on the side walls of the gate of the p-channel MOS transistor. These silicon nitride films 410 and 408 serve as sidewall gate insulating films of the p-channel MOS transistor. Thereafter, as shown in FIG. 32B, the resist 400 is peeled off.

  Next, as shown in FIG. 32C, the surface of the n silicon substrate 401 in the p channel MOS transistor region is isotropically etched so that the total etching depth becomes 80 nm.

This etching is performed, for example, by discharging a mixed gas of CF ₄ and oxygen by microwaves and supplying fluorine radicals to the substrate.

  Next, as shown in FIG. 32D, a 100 nm thick silicon thin film 411 containing 2% boron is selectively deposited on the source / drain regions where the surface of the n-type silicon substrate 401 is exposed. .

This selective deposition is performed, for example, using a mixed gas of SiH ₂ Cl ₂ and BCl ₃ at a substrate temperature of 800 ° C. This silicon thin film 411 becomes a high-concentration and shallow p-type source / drain layer in the p-channel transistor. Note that the boron concentration in the deposited layer needs to be at least 10 ¹⁹ cm ⁻³ in order to form a low-resistance n-type source / drain layer.

  Next, as shown in FIG. 33A, the silicon nitride film 410 on the n-type source / drain layer in the n-channel MOS transistor region is removed by anisotropic etching. That is, the silicon nitride film 410 is left on the gate side wall.

  Next, as shown in FIG. 33B, a titanium thin film 412 having a thickness of 30 nm and a titanium nitride thin film 413 having a thickness of 50 nm are sequentially deposited on the entire surface by sputtering, and then at 700 ° C. for 1 minute in a nitrogen atmosphere. By performing heat treatment, the titanium thin film 412 is completely reacted with the silicon substrate, and the titanium silicide film 414 is formed only on the n-type source / drain layer.

  Next, as shown in FIG. 33C, the titanium nitride thin film 413 and the unreacted titanium thin film 412 on the insulating film are selectively formed by, for example, an aqueous solution of hydrofluoric acid or a mixed solution of sulfuric acid and hydrogen peroxide. Peel off.

  Next, as shown in FIG. 33D, a silicon oxide film 415 having a thickness of 300 nm is deposited on the entire surface by a CVD method, and then a contact hole is opened in the silicon oxide film 415 by anisotropic dry etching.

  Next, as shown in FIG. 4D, after depositing a 300 nm thick aluminum film containing 0.5% of silicon and copper, for example, the aluminum film is patterned to form source / drain electrodes 416. To do. Thereafter, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% hydrogen.

  Using a CMOS inverter formed by this method, a ring oscillator was constructed, and the delay time per stage was measured. FIG. 34 shows the operating voltage dependence of the delay time. In addition, for comparison, the results of the conventional method of forming source / drain diffusion layers by ion implantation are also shown. Here, the junction depth is set to the same value as 700 angstroms. That is, in the method using the present invention, the junction depth is determined, the silicon etching depth is 700 angstroms, and in the conventional method, the junction depth in the LDD region is 700 angstroms. FIG. 34 shows that the delay time is shorter in the present invention regardless of the operating voltage.

FIG. 35 shows a two-dimensional distribution of impurities in each case where the source and drain are formed by the method of the present invention and the conventional method. The unit is cm ⁻² .

  According to the method of the present invention (FIG. 35A), a steep profile can be obtained in the vicinity of the joining position as compared with the conventional method (FIG. 35B). Therefore, even in the case of the same junction depth, the present invention can reduce the sheet resistance of the source / drain, which becomes a parasitic resistance for the operation of the MOS transistor, as compared with the conventional case. Thus, when a CMOS inverter is configured using the present invention, the delay time is shortened as shown in FIG.

  In this embodiment, the p-type source / drain layer is formed after the n-type source / drain layer is formed. However, this order is not necessarily the same, but the order may be reversed.

  In addition, only one channel type MOS transistor is formed by embedding an impurity-doped silicon film, and the other channel type MOS transistor is formed by ion implantation, which is a conventional technique, if necessary. Also good.

  In addition, it is confirmed that the method of this embodiment can form a shallow and low-resistance source / drain layer, which is required as the elements of the CMOS integrated circuit are miniaturized, and is effective in increasing the operation speed. It was.

  Further, the number of manufacturing steps is compared with the number of mask steps. According to the method of the present invention, only two steps are required, whereas in the conventional method, the sidewall gates of the n-channel and p-channel MOS transistors are used. Ion implantation for forming the LDD before forming the insulating film and ion implantation after forming the sidewall gate insulating film are necessary, which is a total of four steps. From this, it can be seen that the structure of the present invention (buried source / drain layer) is advantageous for reducing the number of manufacturing steps. That is, this structure is a structure in which a high concentration and shallow source / drain layer can be easily formed.

(Twelfth embodiment)
36 and 37 are process cross-sectional views illustrating a method of manufacturing a MOS transistor according to the twelfth embodiment of the present invention.

  First, as shown in FIG. 36A, a semiconductor substrate, for example, an n-type silicon substrate 501 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is used, and an element isolation insulation of about 0.6 μm is obtained by a normal selective oxidation method. A film 502 is formed. Subsequently, a gate insulating film 503 having a thickness of 10 nm is formed by thermal oxidation, and an impurity-doped polycrystalline silicon film 504 having a thickness of 100 nm and a tungsten silicide film 505 having a thickness of 300 nm are sequentially formed on the gate insulating film 503. A silicon oxide film 506 having a thickness of 150 nm is formed by CVD. Thereafter, these stacked films are etched by a reactive ion etching method to form a gate portion.

  Thereafter, as shown in FIG. 36B, a silicon oxide film 507 having a thickness of about 100 nm is formed on the side wall of the gate portion. The silicon oxide film 507 is obtained by depositing a silicon oxide film having a thickness of 150 nm on the entire surface by the CVD method and then etching the entire surface by anisotropic dry etching.

  Thereafter, the etching shape was controlled by combining the step of isotropically etching silicon and the step of anisotropically etching silicon.

First, the etching conditions were anisotropic etching with ClF ₃ gas so that the etching depth was 30 nm. The shape at this time is shown in FIG. In FIG. 36C, a surface (surface orientation (100)) where etching proceeds in a direction perpendicular to the substrate, and a surface (surface orientation (111)) formed so as to dig under the side wall of the gate electrode. However, it can be seen that it is formed.

Furthermore, etching was performed by isotropic etching so that the entire etching depth was as thin as 50 nm. Here, the etching was performed by discharging a mixed gas of CF ₄ and oxygen by microwaves and supplying the mixture onto the sample. The shape at this time is shown in FIG.

  Thereafter, as shown in FIG. 37B, the substrate was etched by 50 nm by RIE. Here, RIE was performed using a mixed gas of HBr and oxygen.

Thereafter, as shown in FIG. 37C, a silicon thin film 508 containing boron is formed in the source / drain regions where the substrate is exposed. At this time, the concentration of boron is preferably 10 ¹⁹ cm ⁻³ or more from the viewpoint of forming a low-resistance diffusion layer.

  Thereafter, a silicon oxide film 509 having a thickness of 300 nm was deposited on the entire surface by a CVD method, and then contact holes were opened in the silicon oxide film 509 by anisotropic dry etching, as shown in FIG. Subsequently, an aluminum film 510 containing 0.5% of silicon and copper, for example, was deposited to 800 nm. After patterning as this aluminum film and electrode, it was heat-treated at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% hydrogen.

This MOS transistor, when performed both isotropic etching using a mixed gas of the anisotropic etching and CF ₄ and oxygen by ClF _3, when performed only anisotropic etching using ClF _3, CF ₄ When only etching using a mixed gas of oxygen and oxygen was performed, the characteristics of the MOS transistors were compared. Using the gate length as a parameter, the change in the threshold value of the MOS transistor was examined.

As shown in FIG. 40, in the case of performing only isotropic etching (Δ mark in the figure), the threshold voltage was lowered as the gate length was shortened. On the other hand, in the case of only anisotropic etching (marked with □ in the figure) and both anisotropic etching and isotropic etching (marked with ○ in the figure), the threshold voltage was lowered. There wasn't. Therefore, it was found that anisotropic etching is effective for the short channel effect. This is considered to be because when only etching using a mixed gas of CF ₄ and oxygen is performed, the distance of the high concentration region is closer to the deep region under the gate as a result of the isotropic etching.

  As shown in FIG. 41, when the static characteristics are compared, there is almost no difference in drain current in the region of low drain voltage. This means that when only isotropic etching is performed (b in the figure), the high concentration region in the diffusion layer can be enlarged, but the high concentration layer is formed deep in the region near the channel. It shows that it is not effective in reducing the parasitic resistance.

In addition, even when anisotropic etching and isotropic etching were performed, a curve as shown in FIG. However, when only anisotropic etching with ClF ₃ is performed (a in the figure), it can be seen that the drain current increases as the drain voltage increases. This is presumably because a portion with an extremely small radius of curvature was formed by anisotropic etching, and the electric field strength in this region became extremely strong, so that the current value increased due to breakdown. In addition, even when anisotropic etching and isotropic etching were performed, a curve as shown in FIG.

  Furthermore, FIG. 41 shows the results when RIE was performed after anisotropic etching and isotropic etching (c in the figure). When the RIE is performed, the drain current rises sharply. This indicates that the RIE can form the diffusion layer at a high concentration in the depth direction and the parasitic resistance is reduced.

  From this result, after performing anisotropic etching and isotropic etching according to the present invention, the process of depositing and diffusing silicon containing a high concentration of impurities is effective in suppressing the short channel effect and at the same time reducing the drain breakdown voltage. It has been confirmed that it is effective in forming a high transistor and effective in forming a shallow diffusion layer associated with the fine elements of a MOS integrated circuit.

  Note that by using a silicon substrate having a different plane orientation, the shape of the etching details can be controlled, whereby an optimum diffusion layer shape can be formed for each transistor. .

  In this embodiment, silicon containing boron is used to form a p-type MOS transistor. However, silicon containing phosphorus or arsenic instead of boron is used to form an n-type MOS transistor. A film may be formed.

In this embodiment, anisotropic etching in which etching proceeds in different plane orientations is performed using ClF ₃ gas, but a gas containing Cl or a plasma gas can also be used.

Further, wet etching such as KOH may be used. In addition, although isotropic etching is performed with a mixed gas of CF ₄ and oxygen, only CF ₄ may be used, or a gas containing a halogen other than chlorine, for example, fluorine, for example, a gas such as F or NF ₃ may be used. Also, hydrofluoric acid based wet etching may be used.

  In this embodiment, isotropic etching is performed after anisotropic etching is performed in different plane orientations. However, the order of etching may be reversed depending on the shape of a desired diffusion layer.

(13th Embodiment)
FIG. 42 is a process sectional view showing the method for manufacturing the semiconductor device according to the thirteenth embodiment of the present invention.

  First, as in the conventional example, an element isolation insulating film 602 is formed on the surface of an n-type silicon substrate 601 having a resistance of 4 to 5 Ωcm, and a silicon oxide film serving as the gate insulating film 3 is interposed in the divided element region. Then, a polycrystalline silicon film 604 is formed, and then an impurity is added to the polycrystalline silicon film 604 by a thermal diffusion method or the like. Then, a silicon oxide film 608 is deposited on the entire surface, and the silicon oxide film 608 and the polycrystalline silicon film 604 are patterned by the RIE method, leaving only the channel region, and the gate electrode 4 is formed. Thereafter, a silicon oxide film 608 is further deposited on the upper layer and etched back by RIE to leave the silicon oxide film 608S only on the side wall of the gate electrode. Subsequently, the gate insulating film 603 in the diffusion layer region to be the source / drain is removed. Thereafter, the sample is put in an HF solution, and then the sample is washed in pure water having a dissolved oxygen content of 10 ppm or less, thereby exposing a chemically active silicon surface (FIG. 42A). Here, when pure water with a large amount of dissolved oxygen is used for cleaning, a natural oxide film is formed on the silicon surface during cleaning and subsequent drying, and a uniform deposited film cannot be grown. Furthermore, it becomes an obstacle when the dopant is diffused using the deposited film as a diffusion source. Therefore, it is desirable to use pure water with a small amount of dissolved oxygen, such as 10 ppm or less.

Thereafter, the substrate is put into a normal diffusion furnace type reduced pressure CVD furnace, hydrogen is allowed to flow at 100 to 3000 cc / min, and the substrate is heated to a predetermined temperature of 180 to 400 ° C. Thereafter, the flow rate of hydrogen gas is stabilized by setting an appropriate deposition condition, for example, the hydrogen gas flow rate is set to 1000 cc / min, and then silane gas (SiH ₄ ) is allowed to flow for 1 to 100 cc / min. At this time, the phenomenon that silane was decomposed and silicon was deposited on the substrate in the temperature range was not observed. This is because the temperature of the substrate is sufficiently lower than the temperature at which normal selective growth of silicon occurs, and the decomposition of the silane gas is suppressed by flowing hydrogen gas.

  In this way, boron trichloride gas is further supplied for 0.1 to 100 cc / min while hydrogen gas and silane gas are supplied. This boron trichloride is adsorbed on the silicon surface, which is a conductive part, and is reduced by receiving electrons. Furthermore, the chlorine formed by this reduction is detached from the silicon surface by reacting with silane or other chlorine. As a result, as shown in FIG. 42B, a boron deposition film is selectively formed only on the silicon surface exposing the source / drain regions. At this time, the deposition rate was 1 to 50 nm / min.

FIG. 43 shows an example in which a boron deposited film is selectively grown at a substrate temperature of 370 ° C., a boron trichloride gas flow rate of 50 sccm, a silane gas flow rate of 50 sccm, and a hydrogen gas flow rate of 1000 sccm. As can be seen from FIG. In addition, the boron deposition film of about 300 nm grew on the silicon surface without growing on the silicon oxide film for about 20 minutes after starting to flow silane gas. When the substrate temperature is 400 to 800 ° C. with silane gas 1 to 100 cc / min, boron trichloride gas 0.1 to 50 cc / min, decomposition of silane gas is induced, and boron-doped silicon film is selectively formed only on the silicon surface. Formed. At this time, the boron concentration of the boron-added silicon film to be deposited can be set to a desired concentration of 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²² cm ⁻³ depending on the flow ratio of the silane gas and the boron trichloride gas.

Thereafter, by performing heat treatment in a nitrogen atmosphere at 1000 ° C. for 2 minutes, boron atoms are taken into the silicon substrate from the boron deposited film or boron-added silicon film thus formed, and FIG. A diffusion layer 605 is formed as shown in FIG. Here, when the boron-added silicon film containing 3 × 10 ²⁰ cm ^{−3 of} boron was grown to 50 nm, the junction depth and the sheet resistance of the diffusion layer were measured and found to be 75 nm and 120Ω / □, respectively. In this way, a shallow diffusion layer could be formed with good controllability and selectivity.

  Further, as shown in FIG. 42D, titanium is sputtered on the diffusion layer, and heat treatment is performed at 700 ° C. for 30 seconds to form a silicide layer 609. Subsequently, a silicon oxide film 610 is deposited by CVD, a contact hole is patterned by RIE, and an aluminum film 611 is deposited thereon as an electrode. At this time, boron diffuses into the silicide layer. However, since the boron concentration of the boron deposition film or boron-added silicon film formed in FIG. 42C is sufficiently high, even if boron diffuses into the silicide, the source / drain There is little influence on the boron concentration in the diffusion layer. Here, the titanium silicide layer is provided on the diffusion layer. However, the present invention is not limited to this, and a similar effect can be obtained with a nickel or cobalt silicide layer.

In this embodiment, hydrogen gas is mixed with silane gas as the second gas, but hydrogen may be omitted. Further, although boron trichloride has been described as the boron halide, the present invention is not limited to this, and other halides such as boron trifluoride (BF ₃ ), boron tribromide (BBr ₃ ), etc. Good. Furthermore, although monosilane was taken as an example of the silane-based gas, disilane (Si ₂ H ₆ ), SiH ₂ Cl ₂ , SiCl ₄ , SiF ₄ , Si ₂ H ₄ Cl ₂ , SiH ₂ F ₂ , Si _{2 were used.} H ₂ Cl ₄ , Si ₂ Cl ₆ , Si ₂ H ₄ F ₂ , Si ₂ H ₂ F ₄ , and Si ₂ F ₆ may be used.

  Moreover, the decomposition of the gas can be performed not only by a simple thermal decomposition reaction but also by a combination of methods for promoting a dissociation reaction such as light irradiation.

  In addition, as a method for incorporating boron atoms into the silicon crystal from the deposited boron layer or boron-added silicon film, heat energy is applied, but UV light is irradiated from the surface, etc., using light, ions, or electron beams. You may make it take in a boron atom in silicon | silicone using energy. Among these methods, the method of irradiating UV light from the surface can impart energy only to the silicon surface, so that boron is incorporated near the surface without changing the impurity state other than the surface in the silicon substrate. be able to.

(Fourteenth embodiment)
FIG. 44 is a process sectional view showing the method for manufacturing the semiconductor device according to the fourteenth embodiment of the present invention.

  First, in the same manner as in the conventional example, an element isolation insulating film 602 is formed on the surface of an n-type silicon substrate 601 having a resistance of 4 to 5 Ωcm, and the element region is decomposed, with a silicon oxide film serving as a gate insulating film 603 interposed therebetween. A polycrystalline silicon film 604 is formed, and then an impurity is added to the polycrystalline silicon film 604 by a thermal diffusion method or the like. Then, a silicon oxide film 608 is deposited on the entire surface, and the silicon oxide film 608 and the polycrystalline silicon film 604 are patterned by the RIE method leaving only the channel region, thereby forming a gate electrode 604. Thereafter, a silicon oxide film 608 is further deposited on the upper layer and etched back by RIE to leave the silicon oxide film 608S only on the side wall of the gate electrode. Subsequently, the gate insulating film 603 in the diffusion layer region to be the source / drain is removed. Thereafter, the sample is put in an HF solution, and then the sample is washed in pure water having a dissolved oxygen content of 10 ppm or less to expose a chemically active silicon surface (FIG. 44 (a)). Here, when pure water with a large amount of dissolved oxygen is used, a natural oxide film is formed on the silicon surface during cleaning and subsequent drying, and uniform etching cannot be performed. The surface cannot be obtained. Therefore, it is desirable to use pure water with a small amount of dissolved oxygen, such as 10 ppm or less.

  Thereafter, the sample is put in a vacuum apparatus in which the etching chamber and the CVD chamber are connected, and first, the substrate is cooled or heated to a predetermined temperature of −196 ° C. to 300 ° C. in the etching chamber. At this time, in order to suppress the formation of a natural oxide film on the silicon surface, a vacuum of 0.133 Pa or less or argon is flowed at 100 to 5000 cc / min. Here, argon is used as the non-oxidizing gas, but the same effect can be obtained by using other non-oxidizing gases.

Next, carbon tetrafluoride (CF ₄ ) is allowed to flow at 1 to 500 cc / min. After the flow rate and pressure are stabilized, the carbon tetrafluoride is activated by microwave discharge, and the generated radicals are supplied to the sample. On the silicon surface, silicon and fluorine radicals mainly react to desorb from the silicon surface in the form of silicon tetrafluoride (SiF ₄ ), and etching proceeds. At this time, the etching rate was 1 to 20 nm / min. In this way, after etching to a desired depth, the sample is vacuum-transferred to the CVD chamber, and the substrate is heated with the oxidizing gas partial pressure kept at 1330 Pa or lower to a predetermined film formation temperature of 300 ° C. to 800 ° C. .

Next, dichlorosilane (SiH ₂ Cl ₂ ) gas is supplied at 10 to 100 cc / min, and boron trichloride (BCl ₃ ) is supplied at 0.1 to 100 cc / min. The dichlorosilane and boron trichloride are thermally decomposed only on the silicon surface, and a boron-added silicon film is selectively deposited. At this time, the deposition rate was 1 to 10 nm / min. Further, the boron concentration of the boron-added silicon film to be deposited can be set to a desired concentration of 1 × 10 ¹⁹ to 1 × 10 ²² cm ⁻³ depending on the flow rate ratio of dichlorosilane gas and boron trichloride gas at this time. .

  As described above, the process proceeds to the film forming process continuously after etching. At this time, the amount of oxygen adsorbed on the interface between the silicon substrate and the boron-added silicon film differs depending on the atmosphere to which the silicon substrate is exposed. For example, if the sample is exposed to the atmosphere after etching or if the sample is heated in an atmosphere containing a large amount of oxidizing gas such as oxygen or water, the water molecules and oxygen molecules are adsorbed on the etched silicon surface and oxidation proceeds. .

  FIG. 45 (a) shows an example in which the oxygen concentration in the region including the interface between the silicon substrate and the boron-added silicon film is analyzed by SIMS. When the silicon surface is oxidized between the etching process and the film forming process, A large amount is detected.

FIG. 45B shows the relationship between the oxygen partial pressure in the vacuum apparatus at 350 ° C. and the oxygen amount at the interface between the silicon substrate and the boron-added silicon film when the sample is exposed to the atmosphere for 1 hour. According to this, when the oxygen partial pressure is 1330 Pa or more, the oxidation of the silicon surface proceeds and oxygen of 1 × 10 ¹⁵ cm ⁻² or more is detected.

  As described above, when the boron-added silicon film is grown on the oxidized silicon surface, not only good selectivity is not obtained as shown in FIG. 46A, but also the boron-added silicon film on the silicon substrate is obtained. The crystal becomes polycrystalline. In addition, when such a natural oxide film exists, the diffusion of boron from the boron-added silicon film is hindered, making it difficult to diffuse impurities with excellent controllability.

  On the other hand, when this oxygen partial pressure was lowered to 1330 Pa or less, the oxidation of the silicon surface was suppressed, and selective growth became possible as shown in FIG.

In particular, if the amount of oxygen at the interface between the silicon substrate and the boron-added silicon film can be suppressed to 4 × 10 ¹⁴ cm ⁻² or less, the boron-added silicon film on the silicon substrate grows epitaxially.

Further, even if a silicon substrate whose surface has been oxidized after etching is dipped in an HF solution, and then the sample is rinsed in pure water having a dissolved oxygen content of 10 ppm or less, and placed in a CVD furnace to form a film. The amount of oxygen adsorbed on the silicon surface can be reduced to 4 × 10 ¹⁴ cm ^−2, but at the same time, the gate oxide film 3 is also etched as shown in FIG. Therefore, it is desirable to continuously perform the etching process and the film forming process while suppressing the oxidizing gas partial pressure to 1330 Pa or less in the connected vacuum apparatus.

The boron-added silicon film 607 deposited in this way forms a direct diffusion layer as shown in FIG. When the etching depth was 50 nm and a boron-added silicon film containing 3 × 10 ²⁰ cm ^{−3 of} boron was grown to 50 nm, the sheet resistance of the diffusion layer was measured and found to be 120Ω / □. Furthermore, as a result of analyzing the depth direction of boron for this sample by SIMS, the junction depth and the etching depth are in agreement, and the boron concentration rapidly decreases at the junction interface, and a steep profile is obtained. It was confirmed. Thus, according to this embodiment, oxidation and contamination of the silicon surface can be avoided, and a shallow and high-concentration diffusion layer can be formed with extremely good controllability and selectivity.

  Further, as shown in FIG. 44D, titanium is sputtered on the diffusion layer, and heat treatment is performed at 700 ° C. for 30 seconds by annealing to form a silicide layer 609. Subsequently, a silicon oxide film 610 is deposited by CVD, a contact hole is patterned by RIE, and an aluminum film 611 is deposited thereon as an electrode. At this time, boron is diffused into the silicide layer when the silicide layer is formed. However, since the boron concentration of the boron-added silicon film 607 formed in FIG. 44C is sufficiently high, boron diffuses into the silicide layer. Even so, there is little influence on the boron concentration in the diffusion layer serving as the source and drain. Here, the titanium silicide layer is provided on the diffusion layer. However, the present invention is not limited to this, and the same effect can be obtained with a nickel or cobalt silicide layer.

In the above embodiment, carbon tetrafluoride is used as an etching gas and etching is performed with fluorine radicals generated by discharging with microwaves. However, the present invention is not limited to this. A halogen-based etching gas such as chlorine (ClF ₃ ), sulfur hexafluoride (SF ₆ ), fluorine (F ₂ ), chlorine (Cl ₂ ) or the like may be used.

Furthermore, although dichlorosilane (SiH ₂ Cl ₂ ) is given as an example of a gas containing at least hydrogen and silicon as a boron-added silicon film growth gas, silane (SiH ₄ ), Si ₂ H ₆ , SiCl ₄ , Si ₂ F ₄ Cl ₂ , Si ₂ H ₄ Cl ₂ , SiH ₂ F ₂ , Si ₂ H ₂ Cl ₄ , Si ₂ Cl ₆ , Si ₂ H ₄ F ₂ , Si ₂ H ₂ F ₄ , Si ₂ F ₆ Good. In addition, boron trichloride (BCl ₃ ) is taken as an example of a gas containing a halide of a group 3 or group 5 element, but B ₂ H ₆ , BF ₃ or the like may be used. In the case of forming an n-type impurity diffusion layer, the same effect can be obtained by using a halide containing PH ₃ or AsH ₃ or phosphorus or arsenic.

  Further, not only a simple thermal decomposition reaction but also a combination of methods for promoting a dissociation reaction such as light irradiation can be performed.

Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Characteristic diagram showing the relationship between etching rate and substrate temperature Characteristic diagram showing the relationship between the oxidizing gas partial pressure and the amount of oxidation at the interface Characteristic diagram showing the relationship between the amount of interfacial oxygen and the average film thickness of the silicon film Characteristic diagram showing the relationship between fluorine content on silicon oxide film and selectivity ratio of deposited silicon film Diagram showing the substrate temperature dependence of the fluorine content on the silicon and oxide surfaces The figure which shows the dependence of the film formation time of the film thickness of the amorphous boron addition silicon film formed on the silicon surface and an oxide film Characteristic diagram showing relationship between substrate temperature and deposition rate of boron-doped silicon film deposited on silicon surface Characteristic diagram showing the relationship between deposition time, film thickness and substrate Characteristic diagram showing the relationship between deposition time, film thickness and substrate under other conditions Characteristic diagram showing the relationship between deposition time, film thickness and substrate under other conditions Process cross section showing conventional selective CVD method Process cross section showing conventional direct contact technology Process sectional drawing which shows the manufacturing method of the first half of the p channel MOS transistor which concerns on the 3rd Embodiment of this invention Process sectional drawing which shows the manufacturing method of the second half of the p channel MOS transistor which concerns on the 3rd Embodiment of this invention Characteristic diagram showing the relationship between drain voltage, drain current and source / drain layer thickness Process sectional drawing which shows the manufacturing method of the p channel MOS transistor which concerns on the 4th Embodiment of this invention Characteristic diagram showing the relationship between gate voltage, drain current and source / drain layer thickness Characteristic diagram showing the relationship between source / drain layer thickness and drain current Process sectional drawing which shows the manufacturing method of the MOS transistor using the SOI substrate based on the 5th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the MOS transistor using the SOI substrate based on the 6th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the MOS transistor using the SOI substrate based on the 7th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the MOS transistor using the SOI substrate based on the 8th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the MOS transistor using the SOI substrate based on the 9th Embodiment of this invention The figure which shows the two-dimensional distribution of the impurity (boron) of the source / drain by this invention and the conventional method The figure which shows the relationship between the depth of the source / drain by this invention, the conventional method, and sheet resistance The figure which shows the power supply voltage dependence of the delay time of the ring oscillator by this invention and the conventional method The figure which shows ID-VD characteristic of the source / drain layer which consists of silicon, and the source / drain layer which consists of SiGe Process sectional drawing which shows the manufacturing method of the first half of the CMOS transistor which concerns on the 11th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the middle half of the CMOS transistor which concerns on the 11th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the middle half of the CMOS transistor which concerns on the 11th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the latter half of the CMOS transistor which concerns on the 11th Embodiment of this invention The figure which shows the power supply voltage dependence of the delay time of the ring oscillator by this invention and the conventional method The figure which shows the two-dimensional distribution of the impurity of the source / drain by this invention and the conventional method Process sectional drawing which shows the manufacturing method of the first half of the MOS transistor which concerns on the 12th Embodiment of this invention Process sectional drawing which shows the manufacturing method of the second half of the MOS transistor which concerns on the 12th Embodiment of this invention Sectional drawing which shows the relationship between the etching depth of anisotropic etching, and an etching shape Sectional drawing which shows the relationship between the etching shape and surface orientation of anisotropic etching The characteristic view which shows the relationship between the gate length and threshold voltage for demonstrating the effect of this invention The characteristic view which shows the relationship between the drain voltage and drain current for demonstrating the effect of this invention Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 13th Embodiment of this invention. Characteristic diagram showing the relationship between deposition time, film thickness and substrate Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 14th Embodiment of this invention. Characteristic diagram for explaining the effect of the present invention Characteristic diagram and sectional view for explaining the effect of the present invention Cross-sectional process drawing showing a conventional MOS transistor manufacturing method Process sectional drawing which shows the manufacturing method of the MOS transistor using the conventional SOI substrate A photograph showing a fine pattern formed on a substrate Photo showing other fine patterns formed on the substrate Photo showing other fine patterns formed on the substrate Photo showing other fine patterns formed on the substrate

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... N-type silicon substrate, 102 ... Element isolation insulating film, 103 ... Gate insulating film, 104 ... Polycrystalline silicon film, 105 ... Groove, 106 ... Side wall gate insulating film, 107 ... Boron addition silicon film, 108 ... Silicon oxide film 109 ... Titanium silicide film, 110 ... p-type source / drain layer, 111 ... p-type source / drain layer, 112 ... silicon oxide film, 113 ... silicon oxide film, 114 ... source / drain electrode, 115 ... source / drain electrode , 201 ... n-type silicon substrate, 202 ... element isolation insulating film, 203 ... gate oxide film, 204 ... impurity doped polycrystalline silicon film, 205 ... tungsten silicide film, 206 ... silicon oxide film, 207 ... sidewall gate insulating film, 208 ... Silicon thin film, 209 ... p-type source / drain diffused layer, 210 ... titanium thin film, 211 Titanium nitride thin film, 212 ... Titanium silicide film, 213 ... Silicon oxide film, 214 ... Source / drain electrode, 301 ... Silicon support, 302 ... Silicon oxide film, 303 ... n-type silicon layer, 304 ... element isolation insulating film, 305... Doped polycrystalline silicon film, 306. Tungsten silicide film, 307. Sidewall gate insulating film, 308. ... Silicon oxide film, 315 ... Source / drain electrode, 400 ... Resist, 401 ... n-type silicon substrate, 402 ... p-type well layer, 403 ... element isolation insulating film, 404 ... gate oxide film, 405 ... impurity doped polycrystalline silicon Film, 406 ... tungsten silicide film, 407 ... silicon oxide film, DESCRIPTION OF SYMBOLS 08 ... Silicon nitride film, 409 ... Silicon thin film (n-type source / drain layer), 410 ... Silicon nitride film, 411 ... Silicon thin film (p-type source / drain layer), 412 ... Titanium thin film, 413 ... Titanium nitride thin film, 414 ... titanium silicide film, 415 ... silicon oxide film, 416 ... source / drain electrode, 501 ... silicon substrate, 502 ... element isolation insulating film, 503 ... gate insulating film, 504 ... impurity doped polycrystalline silicon film, 505 ... tungsten silicide 506 ... Silicon oxide film, 507 ... Silicon oxide film, 508 ... Silicon film containing boron, 509 ... Silicon oxide film, 510 ... Aluminum film, 511 ... Oxide film, 601 ... Silicon substrate, 602 ... Element isolation insulating film 603 ... Gate insulating film 604 ... Gate electrode 605 ... Diffusion layer 606 ... Ions, 607 ... Si doped silicon film, 608 ... Silicon oxide film, 609 ... Silicide layer, 610 ... CVD silicon oxide film, 611 ... Aluminum film, 612 ... etching surface.

Claims (2)

A substrate having a surface region made of silicon;
A gate insulating film formed on the surface region;
A gate electrode formed on the gate insulating film;
Sidewall insulating films provided on both sides of the gate electrode;
Buried source and drain layers formed by depositing a silicon film containing impurities in a groove formed in the surface of the substrate in a portion from the bottom of the sidewall insulating film to the outside of the sidewall insulating film And comprising
The impurity concentration of the silicon film at the bottom of the trench is 1 × 10 ¹⁹ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less, and the impurity concentration of the silicon film along the depth direction of the trench is constant. And the buried-type source and drain layers are formed on the outside of the first buried-type source and drain layers formed under the sidewall insulating film and the sidewall insulating film, A semiconductor device comprising: a second buried type source and drain layer thicker than the first buried type source and drain layer. 2. The semiconductor device according to claim 1, wherein the concentration of the impurity in the surface region made of silicon is less than 1 × 10 ¹⁷ cm ⁻³ .

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