JP2012124489A - Method of manufacturing semiconductor structure from silicon carbide, and silicon carbide semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor structure from a silicon carbide, which allows accurate and uniform structuring that can be reproduced.SOLUTION: The method is characterized by including the following steps: a polysilicon layer is deposited on a substrate, and a structure of masking is transferred into the polysilicon layer; a spacer comprising polysilicon is provided between a trench and an implantation region; the masking is removed, and the substrate is oxidized under heat; an SIOHTO layer is precipitated; the implantation region is implanted, to release an oxide layer; and the spacer is removed, and a remaining oxide cover and an integral oxide are removed.

Description

  The present invention relates to a method of manufacturing a semiconductor structure from silicon carbide and a semiconductor manufactured in accordance with the method.

  When manufacturing semiconductor devices from silicon carbide (SiC), especially when manufacturing transistors, especially MOSFETs (metal oxide semiconductor field effect transistors), high demands are placed on the horizontal control of the implant region. This control of the channel length is important in the case of a MOSFET, for example. In order to make such a channel length reproducible, various methods have been proposed and used in the prior art.

  The established technology, which is most effective and advantageous when the channel length is short, is the so-called “self-alignment” technique (self-alignment process), which is basically realized by two different techniques. So-called spacer technology (also called Purdue technology) and etching technology.

  Each technique is common in that it uses only one exposure surface and allows different implantations of various areas without exposure tolerances. That is, self-adjustment of two different exposures.

  Spacer technology is the so-called spacer positioning, and after the first implantation, the area for the next implantation is made smaller as expected.In the implantation area etching technique, the masking layer is peeled off. Expand the area for the next implantation. This technique is described, for example, in WO 99/07011. The essential disadvantage of this technique or this method is that the distribution width is scattered too much by masking under-etching, and therefore the channel length is scattered too much for special MOSFET applications. It is. This is clearly shown in the drawings of the present application.

  In order to produce microstructures in silicon, deep reactive ion etching (DRIE) is known. This is a dry etching process that etches perpendicular to the wafer surface.

WO99 / 07011

  It is an object of the present invention to provide a method of manufacturing a semiconductor structure from silicon carbide that allows an accurate, uniform and reproducible structuring.

The above issues
Depositing a polysilicon layer on a substrate made of silicon carbide;
Masking the polysilicon layer, the mask having at least one window for forming a trench and at least one window for forming an implantation region;
Transferring the masking structure into the polysilicon layer by a DRIE dry etching process, and providing a spacer made of polysilicon between the trench and the implantation region;
Removing the masking;
Thermally oxidizing the laminated substrate at a temperature lower than that required for silicon carbide oxidation;
Depositing a SIO ₂ HTO layer;
A step of implanting an implantation area;
Opening the oxide layer at a transition of the polysilicon layer to the implantation region by a dry etching process;
Removing the spacer by a plasmaless etching process using chlorotrifluoride or xenon difluoride;
Removing the remaining oxide coating on the substrate and the polysilicon layer as well as the step of removing the complete oxide.

Cut-away side view of a substrate made of silicon carbide, partially laminated with a polysilicon layer Side cut view of substrate after thermal oxidation Cutaway side view of substrate trench ripple detail Cutaway view of a substrate with an HTO layer and a doped implantation layer Detailed view of substrate trench ripple cut Cutaway view of substrate after etching process to partially thin oxide layer Sectional view of substrate after CIF ₃ etching process Sectional view of the substrate after removal of all oxide layers Sectional view of a substrate with a scattering oxide layer and a second implantation surface Sectional view of a substrate provided with a semiconductor structure manufactured by the method of the invention

  In the present invention, a method of manufacturing a semiconductor structure made of silicon carbide is disclosed. This method enables accurate, uniform and reproducible structuring. Here, the implantation area is advantageously determined not by the time control process but by determining the design.

  The present invention further provides a semiconductor manufactured according to this method.

  Particularly advantageously, the method of the invention is used when very high requirements are imposed on the uniformity when the individual transistors are connected in parallel. This method for constructing a vertical MOSFET device is advantageous. Here, the horizontal channel region is defined by the horizontal overlap of the base region across the source region, which is manufactured substantially uniformly and reproducibly from wafer to wafer.

The manufacturing method of the present invention for a semiconductor structure made of silicon carbide includes the following steps. Here, the cleaning steps and the standard process steps are omitted or summarized. This is because these steps are well known to those skilled in the art.
Depositing a polysilicon layer on a substrate or wafer made of silicon carbide (SiC); masking the polysilicon layer. Here, the mask has at least one window for forming a groove (trench) and at least one window for forming an implantation region.
Transferring the masking structure into the polysilicon layer by a DRIE dry etching process (deep reactive ion etching), thereby creating a defined dividing region (spacer) between the trench and the implantation region; This spacer has a trench ripple, i.e. a characteristic corrugated wall structure, produced by a dry etching process and pointing towards the implantation region. The implantation region can be slightly etched on the surface. This is because this process has a high selectivity from silicon to silicon carbide (SiC). However, the step formed by this etching is in the nanometer range.
Removing the masking and optionally cleaning the substrate; thermally oxidizing the laminated substrate at a temperature lower than that required for SiC oxidation. This temperature is preferably in the range of 900 ° C. to 1000 ° C. in oxygen. Here, the trench is sealed and the structured polysilicon layer is covered by an oxide layer. The key to this step is that in other cases the oxidation is uniform, but at the transition edge from the polysilicon layer to the trench ripple, an inhomogeneous oxide layer is formed. . On the other hand, a sealed trench does not function. This is because it is completely filled and covered. The implantation area consisting of silicon carbide remains unstacked.
Depositing an HTO layer (high temperature oxide) of SiO2 to strengthen the oxide on the polysilicon layer and as a scattering oxide for implantation. This deposition is preferably performed by an LPCVD process (low pressure chemical vapor deposition), although other CVD techniques can also be used. This is, for example, PECVD (plasma enhanced chemical vapor deposition), SACVD (quasi-atmospheric chemical vapor deposition) or the like. The advantage of the HTO layer is good penetration. This avoids excessive thickness at the edges and covers the corners of the trench as well. The trench ripple geometry is also covered by this layer. But not as much as a flat layer.
Implanting the implantation region according to the desired doping and the required dopant profile. This creates the desired new characteristics in the implantation region, unlike the remaining substrates.
Opening the oxide layer at the edge of the transition of the polysilicon layer to the trench ripple by a dry etching process, preferably by a DRIE process. A flat etching surface can provide a uniform etching rate, but an edge has a high etching rate. For this reason, and because of the thin oxide thickness at the edges described above, the etching thins quickly and gaps are formed in the oxide. This process is stopped when a passage to the spacer is formed. Alternatively, a process of forming a passage to the spacer can be included by forming a split in the leg of the trench ripple. In other areas, an oxide layer remains thick enough to protect the silicon.
Removing the spacers by a plasmaless etching process using chlorotrifluoride or xenon difluoride. This etching is performed through a pre-formed passage to the spacer to completely remove the spacer polysilicon. The etching action is not performed on trenches that are completely protected by oxide and on polysilicon surfaces that are completely flat and protected by oxide, so that only the spacers are selectively removed. Trench ripples that are only partially open and not open to the surroundings are not a problem. This is because a wide under-etching width can be realized by the capillary action of CIF ₃ -etching gas. The collapse of the oxide coating is not a problem. Advantageously, the surface of the substrate exposed to the etching gas is also improved simultaneously with the removal of the polysilicon spacer with respect to roughness and lattice defects. It is advantageous to obtain an etching stop due to the high selectivity of the etching gas (CIF ₃ ) that is advantageously used for the sacrificial layer (Si) and the passivation part (SiO 2). This allows for large process tolerances and at the same time allows for narrow tolerances that are determined in the design.
Removing the remaining oxide coating as well as complete oxide. This is advantageously done by isotropic wet etching with an etching solvent containing hydrofluoric acid. After removing the complete oxide, a pre-oxide protected trench edge is obtained that limits the next implantation plane.
-Implanting the next implantation surface.

  By the series of steps of the present invention described above, a method for self-adjusting two implantation regions with one mask plane is obtained.

  The advantages of the method of the present invention over the known technology are that the use of a process with a stop layer (oxide coating) can eliminate the time-controlled etching process, and is very advantageous when using FET devices. It is possible to realize a long channel length and a short channel length with high accuracy. Advantageously, very short channel lengths are also realized. Here, this is determined by the resolution limit at the time of masking.

  In an advantageous embodiment, this is readjusted to the submicrometer range by a controlled dry oxidation process. Therefore, the tolerance is very small in the semiconductor of the present invention. This is because the tolerance fluctuation caused by the equipment can be adjusted later when necessary.

  Advantageous developments of the invention are described in the dependent claims and the description.

  Embodiments of the present invention will be described in more detail with reference to the drawings and the following specification.

  FIG. 1 shows a substrate 10 made of silicon carbide (SiC). For example, a MOSFET having a channel length of 500 nm is realized by this substrate. The substrate 10 is provided with a structured polysilicon layer 11. The polysilicon layer 11 has a predetermined region divided by the trench 12. Here this region is shown as spacer 13. The spacer 13 is adjacent to the implantation region 14 of the substrate 10. Here, the implantation region is not stacked. By performing the process by the DRIE trench process (deep reactive ion etching), a trench ripple 15 is generated at the edge of the spacer 13 facing the implantation region 14. The spacer may have multiple trench ripples depending on the layer thickness and process. The surface of the implantation region 14 can be slightly etched. This is because the DRIE trench process has a high selectivity from silicon to silicon carbide (SiC). The step formed by etching is in the nanometer region. Examples of dimensions for realizing a MOSFET having a channel length of 500 nm will be described in the drawings or the following description. If a polysilicon layer thickness different from 500 nm is selected and different mask dimensions (as defined by the layout) are selected, shorter or longer channel lengths can be realized. Such a structure results in a trench 12 with a width 17 of 100 nm. This trench is separated from the implantation region 14 by a spacer 13 having a width 18 of 300 nm. The aspect ratio for the trench 12 is about AR = 5 (500/100), but this can be varied depending on the task, depending on the thickness 16 of the polysilicon layer 11 and the width 17 of the trench 12.

  FIG. 2 shows a state after thermal oxidation at, for example, 900 ° C. to 1000 ° C. in oxygen. At this time, an oxide layer 19 grows on the polysilicon layer 11. Here, the duration of this process is selected such that the trench 12 is completely sealed. For the selected dimension, the growth thickness d of the oxide layer 19 is greater than 50 nm. At 44% silicon consumption, the trench edge 20 shifts by 22 nm to the side of the trench 12 opposite the spacer 13. The oxidation caused by the process is only poorly uniform at the transition edge 21 from the polysilicon layer 11 to the trench ripple 15 (see FIG. 3). In contrast, the sealed trench 12 forms the base for subsequent horizontal deposition of another oxide. This blocks trench ripples that are present at this location but not shown in detail and will fail. This is because these trench ripples are completely filled and covered.

Such subsequent deposition is illustrated in FIG. A thin HTO layer 22 is deposited by the LPCVD process. In principle, other processes (eg PECVC, SACVD) are also suitable for the deposition of the HTO layer 22. The HTO layer 22 has good penetration (Spaltgaengigkeit). As a result, the thickness does not increase excessively at the edge, and the corners of the trench 12 are similarly covered. The trench ripple 15 is also covered by the HTO layer 22. However, it is not to the same extent as the flat, flat oxide layer 19 on the polysilicon layer 11. The HTO layer 22 also covers the implantation region 14 and is used as a scattering oxide for subsequent implantation. In the applications described in the present application, the HTO layer 22 is based on a layer thickness of 50 to 100 nm in accordance with the desired channel length. However, thinner or markedly thicker oxides may be deposited if desired. Similarly, FIG. 4 shows that the implantation region 14 is implanted with the desired doping and with the required dopant profile. Accordingly, the implantation region 14 has a desired new characteristic in this region 23 of the implantation region 14, unlike the substrate 10. The trench ripple 15 has an important influence on the success or failure of the subsequent steps, and is shown enlarged in FIG. The DRIE trench process has a substantially uniform etch rate on a flat surface without topology, but has a higher etch rate at the edge. Under such circumstances and the preceding process implementation, the oxide layer 19 to be deposited becomes thin at the edge 21 at the transition from the polysilicon layer 11 to the trench ripple 15 (factor f is about 0.75). ˜0.5), as shown in FIG. 6, during the etching process, the oxide layer 19 becomes thinner faster at the edge 21, and a gap 24 is formed in the oxide layer 19. When a passage in the form of a gap 24 is formed for the CIF ₃ etch process, the process stops. Otherwise, the oxide layer 19 remains intact.

FIG. 7 shows the state after performing the plasmaless CIF ₃ etching process. Here, the spacer 13 is removed through the gap 24. A cavity 25 is formed instead of the spacer. The remainder of the oxide layer 19 is removed as shown in FIG. This is advantageously done by isotropic wet etching with a hydrofluoric acid-containing etching solvent. This exposes the trench edge 26 of the trench 12 that no longer exists. This sets the implantation edge 28 of the second implantation surface 27. Implant edge 28 is opposed to a first edge formed by trench 12 and offset by 22 nm. Therefore, in this embodiment, an offset of 500 nm occurs. For a specific component, this will be the channel length of the FET.

  In FIG. 9, a scattering oxide layer 29 has been deposited for subsequent implantation. As a result, the implantation edge 28 is shifted by the thickness of the scattering oxide layer 29. Alternatively, this may be done with a resist mask or not at all. After the implantation, a modified SiC layer 30 with the desired properties is produced below the second implantation surface 27.

  In FIG. 10, both the scattering oxide layer 29 and the polysilicon layer 11 have been removed by an isotropic wet chemical process. Alternatively, this may be done by a dry etching process. The dry etching process further modifies the surface of the substrate 10.

Claims (7)

A method of manufacturing a semiconductor structure from silicon carbide comprising:
The method is
Depositing a polysilicon layer (11) on a substrate (10) made of silicon carbide;
Masking said polysilicon layer (11), said mask comprising at least one window for forming trench (12) and at least one window for forming implantation region (14) And a step having
A step of transferring the masking structure into the polysilicon layer (11) by a DRIE dry etching process, wherein a spacer made of polysilicon (between the trench (12) and the implantation region (14)) 13) providing,
Removing the masking;
Thermally oxidizing the laminated substrate (10) at a temperature lower than that required for the oxidation of silicon carbide;
Depositing the SIO ₂ HTO layer (22);
-Implanting the implantation area (14);
Opening the oxide layer (19) at the transition of the polysilicon layer (11) to the implantation region (14) by a dry etching process;
Removing the spacer (13) by a plasmaless etching process using chlorotrifluoride or xenon difluoride;
Removing residual oxide coating on the substrate and polysilicon layer (11) as well as complete oxide;
A method characterized by that.   The method according to claim 1, wherein the second implantation surface (27) is implanted after removing the residual oxide coating and the complete oxide.   The second implantation surface is readjusted after removing the residual oxide coating and the complete oxide and before implantation of the second implantation surface (27). Or the method of 2.   The method according to any one of claims 1 to 3, wherein the thermal oxidation of the laminated substrate (10) is performed at a temperature in the range of 900C to 1000C. The method according to claim 1, wherein the deposition of the SiO ₂ HTO layer is performed by an LPCVD process.   The opening of the oxide layer (19) at the transition edge (21) from the polysilicon layer to the trench ripple (12) is performed by a DRIE process. Method.   A silicon carbide semiconductor manufactured according to the method according to claim 1.

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