TWI833182B - Semiconductor device structure - Google Patents

Abstract

A semiconductor device structure includes a substrate, a first gate structure, a second gate structure, a first well region, and a first structure. The substrate has a first surface and a second surface opposite to the first surface. The first gate structure is disposed on the first surface. The second gate structure is disposed on the first surface. The first well region is in the substrate and between the first gate structure and the second gate structure. The first structure is disposed in the first well region. A shape of the first structure has an acute angle.

Description

Semiconductor element structure

This application claims priority to U.S. Patent Application Nos. 17/562,362 and 17/562,210 (that is, the priority date is "December 27, 2021"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor structure, and in particular to a semiconductor element structure including a cobalt silicide structure with an acute angle.

As the area occupied by integrated circuits decreases, the distance between the contact and gate structures also decreases, which may lead to source/drain leakage. Silicon oxide or silicon nitride can be used to prevent metal silicide from forming on the contact side surface of the semiconductor device. However, silicon oxide or silicon nitride may cause an increase in contact resistance, thereby adversely affecting the performance of the semiconductor device.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

One aspect of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first gate structure, a second gate structure, a first well region and a first structure. The base has a first surface and a second surface opposite to the first surface. The first gate structure is disposed on the first surface. The second gate structure is disposed on the first surface. The first well region is located in the substrate between the first gate structure and the second gate structure. The first structure is disposed in the first well zone. The shape of the first structure has an acute angle.

Another aspect of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first gate structure, a second gate structure, a conductive contact, a first well region and a first structure. The substrate has a surface. The first gate structure is disposed on the surface. The second gate structure is disposed on the surface. The conductive contact is between the first gate structure and the second gate structure. The first well region is located in the substrate between the first gate structure and the second gate structure. The first structure is embedded in the first well region and tapers from a bottom of the conductive contact. The first structure includes cobalt silicide.

Another aspect of the present disclosure provides a method of fabricating a semiconductor device structure. The preparation method includes: providing a substrate having a surface; forming a first gate structure on the surface; forming a second gate structure on the surface; in the substrate and on the first gate A first well region is formed between the structure and the second gate structure; a conductive contact is formed in a trench between the first gate structure and the second gate structure; and in the first well region A first structure is formed therein, wherein the first structure tapers from a bottom of the conductive contact.

Embodiments of the present disclosure disclose a semiconductor device structure having metal silicide in a substrate. The metal silicide does not exist in the trench sidewalls between the gate structures of the semiconductor device structure. The contact resistance in the semiconductor element structure is thereby reduced. In addition, the semiconductor element structure includes a titanium nitride layer. The titanium nitride layer serves as a diffusion barrier layer for forming metal silicide. The thickness of the titanium nitride layer is adjustable to prevent metal silicide from forming on the trench sidewalls between the gate structures of the semiconductor device structure and to prevent an increase in contact resistance. In a comparative example, silicon oxide/silicon nitride is formed on the sidewalls of trenches between gate structures of semiconductor device structures. Silicon oxide/silicon nitride has a large contact resistance, thus increasing the contact resistance between the gate structure and the metal silicide. Compared with the comparative example, in the embodiment of the present disclosure, the thickness of titanium nitride can be adjusted to prevent metal silicide from forming on the trench sidewalls between the gate structures of the semiconductor device structure and prevent the contact resistance from increasing. Therefore, The performance of semiconductor device structures can be improved.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific language will now be used to describe the embodiments, or examples, of the present disclosure illustrated in the drawings. It should be understood that there is no intention to limit the scope of the present disclosure. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are deemed to be commonly made by one of ordinary skill in the art to which this disclosure relates. Reference numerals may be repeated throughout the embodiments, but it is not intended that features of one embodiment apply to another embodiment even if they share the same reference numerals.

It will be understood that the terms first, second, third, etc. may be used to describe various elements, components, regions, layers or sections. May be used to describe various elements, components, regions, layers or sections but these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for describing particular embodiments only and is not intended to be limiting of the concepts of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should be further understood that the terms "comprising" and "comprising", when used in this specification, indicate the presence of stated features, integers, steps, operations, elements or elements, but do not exclude the presence or addition of one or more other features, An integer, step, operation, element, component, or group thereof.

Please refer to Figure 1A and Figure 1B. FIG. 1A is a schematic top view of the layout of the semiconductor element structure 1 . The layout includes gate region 101 and source/drain regions 102 . FIG. 1B is a cross-sectional view of the semiconductor element structure 1 along the dotted line AA′ shown in FIG. 1A .

Referring to FIG. 1A , the contact area 103 is separated from the gate area 101 by a distance L. When the size of the semiconductor element structure 1 is reduced, the distance L needs to be reduced accordingly, because when the gate length of the semiconductor element structure 1 is reduced, the semiconductor element structure The threshold voltage of 1 becomes difficult to control, which may cause unexpected current leakage. In a conventional manufacturing process, cobalt silicide is formed on the contact sidewalls. The cobalt silicide may be oval in shape. Cobalt silicide formed on the contact sidewalls may cause current leakage. To prevent cobalt silicide from forming on the contact sidewalls, a layer of silicon nitride is formed on the contact sidewalls. Although the silicon nitride layer prevents cobalt silicide from forming on the sidewalls of the contact, it increases the contact resistance. The method disclosed herein eliminates the silicon nitride layer. Cobalt silicide is pyramid-shaped. Cobalt silicide allows the length L to be reduced without causing current leakage and also reduces the contact resistance.

Referring to FIG. 1B , the semiconductor device structure 1 may include a substrate 10 , a gate structure 11 , a drain region 12 , a source region 13 , a silicide metal structure 14 , spacers 15 and 16 , and a lightly doped drain (LDD) region 17 , halo area 18 and conductive contact 19c. For the sake of simplicity, some elements of the semiconductor element structure 1 are omitted from FIG. 1B.

Substrate 10 may have surface 10s. Gate structure 11 is formed on surface 10s. Drain region 12 is formed below surface 10s. Source region 13 is formed below surface 10s. A siliconized metal structure 14 is formed beneath surface 10s. The siliconized metal structure 14 may be pyramid-shaped. The siliconized metal structure 14 may be conical in shape. In some embodiments, the cross-section of siliconized metal structure 14 may be triangular. Conductive contact 19c includes side walls 19s1 and 19s2. The side walls 19s1 and 19s2 of the conductive contact 19c do not contain the siliconized metal structure 14. The siliconized metal structure 14 is spaced apart from the side walls 19s1 and 19s2 of the conductive contact 19c.

The dashed line shows the current path 19p through the conductive contact 19c and from the drain region 12 to the source region 13. Using the siliconized metal structure 14, the resistance of the conductive contact 19c can be reduced.

As the semiconductor device structure 1 shrinks, the distance between the drain region 12 and the source region 13 also shrinks accordingly, which causes the carriers at the junctions at both ends of the gate structure 11 to operate in a large electric field. Accelerate under the influence of . In some embodiments, an LDD region 17 is formed near the junction between the drain region 12 and one end of the gate structure 11 . In some embodiments, another LDD region 17 is formed near the junction between the source region 13 and the other end of the gate structure 11 . The LDD region 17 can reduce the number of carriers at the junction, thereby reducing the hot carrier effect of the semiconductor device structure 1 . In some embodiments, LDD region 17 is adjacent to gate structure 11 and is formed using a different dopant material having the same conductivity type as drain region 12 and source region 13 .

In some embodiments, halo region 18 is a doped region formed next to drain region 12 and source region 13 . In some embodiments, halo region 18 is formed deeper in substrate 10 than LDD region 17 . The halo region 18 is formed to increase the threshold voltage of the semiconductor element structure 1 . The halo region 18 can reduce the short channel effect of the semiconductor device structure 1 . In some embodiments, halo region 18 is formed using a dopant material of the same conductivity type as substrate 10 .

2A is a cross-sectional view illustrating the structure of a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 2A , the semiconductor element structure 2 may include a substrate 20 , gate structures 21 a and 21 b , a structure 23 , spacers 24 and 25 , and layers 28 and 29 . The substrate 20 may have a surface (or upper surface) 20s1 and a surface (or lower surface) 20s2. Surface 20s1 is opposite surface 20s2. In this disclosure, surface 20s1 may also be referred to as the active surface. In this disclosure, surface 20s2 may also be referred to as the backside surface.

The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. In some embodiments, substrate 20 includes a first conductivity type. In some embodiments, the first conductivity type is p-type. In some embodiments, the p-type dopant includes boron (B), other Group III elements, or any combination thereof. In some embodiments, the first conductivity type is n-type. In some embodiments, the n-type dopant includes arsenic (As), phosphorus (P), other Group V elements, or any combination thereof.

Gate structures 21a and 21b are formed on surface 20s1. Spacer 24 may include two portions 24a and 24b. In some embodiments, portion 24a of spacer 24 is formed on gate structure 21a. In some embodiments, portion 24b of spacer 24 is formed on gate structure 21b. Semiconductor element structure 2 includes spacers 25 . Spacer 25 includes portions 25a and 25b formed on portions 24a and 24b of spacer 24. Spacer 25 includes portions 25c and 25d between substrate 20 and spacer 24. In some embodiments, portion 25a of spacer 25 is formed on portion 24a of spacer 24. In some embodiments, portion 25b of spacer 25 is formed on portion 24b of spacer 24.

Well regions 22 are formed in substrate 20 . Well area 22 is formed below surface 20s1. Well region 22 is formed between gate structures 21a and 21b. In some embodiments, well region 22 includes a second conductivity type that is different from the first conductivity type of substrate 20 . Structure 23 is formed in substrate 20 . In some embodiments, structure 23 is formed in well region 22 . In some embodiments, structure 23 is embedded within well region 22 .

In some embodiments, portion 24a of spacer 24 extends continuously from gate structure 21a to well region 22. In some embodiments, portion 24b of spacer 24 extends continuously from gate structure 21b to well region 22. In some embodiments, portions 25c and 25d of spacer 25 are encapsulated by substrate 20 and spacer 24.

Well regions 26 are formed in substrate 20 . In some embodiments, well region 26 is formed beneath surface 20s1. In some embodiments, well region 26 is embedded within substrate 20 . In some embodiments, well region 26 includes a second conductivity type that is different from the first conductivity type of substrate 20 . In some embodiments, portion 24a of spacer 24 contacts well region 26. In some embodiments, portion 24a of spacer 24 extends continuously from gate structure 21a to well region 26 of substrate 20. In some embodiments, well region 26 is spaced apart from well region 22 .

Well regions 27 are formed in substrate 20 . In some embodiments, well region 27 is formed below surface 20s1. In some embodiments, well region 27 is embedded within substrate 20 . In some embodiments, well region 27 includes the second conductivity type, which is different from the first conductivity type of substrate 20 . In some embodiments, portion 24b of spacer 24 contacts well region 27. In some embodiments, portion 24b of spacer 24 extends continuously from gate structure 21b to well region 27 of substrate 20. In some embodiments, well zone 27 is spaced apart from well zone 22.

Layer 28 is formed on spacer 25 . In some embodiments, structure 23 is in contact with layer 28. In some embodiments, vertical surface 28s of layer 28 does not contain structure 23. In some embodiments, structure 23 is spaced apart from vertical surface 28s1 of layer 28. In some embodiments, layer 28 includes metal oxide. In some embodiments, layer 28 includes metal nitride. In some embodiments, layer 28 includes metal silicide. In some embodiments, layer 28 includes titanium nitride. In some embodiments, the thickness of layer 28 can be adjusted as desired.

Layer 29 is formed on layer 28 . In some embodiments, layer 28 acts as a barrier layer to isolate layer 29 from substrate 20 and spacer 25 . Layer 29 includes electrically conductive contact 29c disposed between gate structures 21a and 21b. Conductive contact 29c may be disposed in the trench between gate structures 21a and 21b. Structure 23 is provided below electrically conductive contact 29c. In some embodiments, layer 28 covers three sidewalls of conductive contact 29c. Layer 28 is formed on the sidewalls of conductive contact 29c. In some embodiments, layer 29 includes metallic material. In some embodiments, layer 29 includes tungsten.

Figure 2B is an enlarged view of the dashed rectangle A shown in Figure 2A. In some embodiments, the cross-section of structure 23 has an acute angle 23A. In some embodiments, structure 23 may be pyramid-shaped. In some embodiments, structure 23 tapers toward surface 20s2 of substrate 20. In some embodiments, vertical surface 28s1 of layer 28 does not contain structure 23 . In some embodiments, structure 23 is spaced apart from vertical surface 28s1 of layer 28.

In some embodiments, structure 23 includes metal silicide. In some embodiments, structure 23 includes cobalt silicide. In some embodiments, cross section 23C1 of structure 23 is closer to surface 20s1 than cross section 23C2 of structure 23 . Section 23C1 of structure 23 has length L1. Section 23C2 of structure 23 has length L2. In some embodiments, length L2 is different than length L1. In some embodiments, length L1 is greater than length L2.

In some embodiments, layer 28 includes base 28b embedded within substrate 20 . In some embodiments, structure 23 is in contact with bottom 28b of layer 28. In some embodiments, bottom 29b of layer 29 is in contact with bottom 28b of layer 28. Structure 23 tapers from the bottom 28b of layer 28. Structure 23 tapers from base 29b of conductive contact 29c.

3A, 3B, 3C, 3D, 3F, 3G, 3H, 3I, and 3J illustrate various preparation stages of semiconductor device structures according to some embodiments of the present disclosure.

Referring to Figure 3A, a substrate 20 may be provided. The gate structure 21a may be formed on the surface 20s1 of the substrate 201. The gate structure 21b may be formed on the surface 20s1 of the substrate 20. Well region 22 may be formed in substrate 20 . In some embodiments, well region 22 may be formed between gate structures 21a and 21b. Spacers 24 may be formed on the gate structures 21a and 21b. Spacers 25 may be formed on the spacers. Well regions 26 may be formed in substrate 20 . In some embodiments, well region 26 may be formed beneath surface 20s1 of substrate 201 .

In some embodiments, a portion of spacer 24 contacts well region 26 . In some embodiments, a portion of spacer 24 is embedded in well region 26 . Well region 27 may be formed in substrate 20 . The well region 27 may be formed under the surface 20s1 of the substrate 201. In some embodiments, a portion of spacer 24 contacts well region 27 . In some embodiments, a portion of spacer 24 is embedded in well region 27 . In some embodiments, base 20 has recess 20r. The recessed portion 20r is sunk below the surface 20s1. In some embodiments, a trench 29t is formed between the gate structures 21a and 21b, the trench 29t being defined by the spacer 25 and the recess 20r of the substrate 20.

Referring to FIG. 3B , layer 28 ′ may be formed on spacer 25 . Layer 28' may be formed by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), flowable CVD (FCVD), spin coating, sputtering, or similar methods. Layer 28' is also formed on the sidewalls of recess 20r and trench 29t of substrate 20. In some embodiments, layer 28' includes one of titanium, titanium nitride, tantalum, tantalum nitride, silicon oxide, silicon nitride, or similar materials. In some embodiments, layer 28' includes titanium nitride.

Referring to Figure 3C, a portion of layer 28' is removed, while a portion of layer 28' formed on sidewalls 29s of trench 29t is retained. In some embodiments, layer 28' formed on spacer 25 is removed. In some embodiments, a portion of layer 28' formed on recess 20r of substrate 20 is removed. This portion of layer 28' may be removed by, for example, etching techniques. In some embodiments, the etching technique includes dry etching, wet etching, or similar techniques. In some embodiments, layer 28' serves to prevent structures 23 shown in Figure 2A from forming on sidewalls 29s of trench 29t.

Referring to FIG. 3D , a layer 30 is formed on the spacer 25 and the recess 20r of the substrate 20 . In some embodiments, layer 30 is formed at the bottom of trench 29t. In some embodiments, layer 30 may be formed by, for example, physical vapor deposition (PVD). Layer 28' formed by CVD has a different deposition concentration than layer 30 formed by PVD. The crystal density of layer 28' formed by CVD is different from that of layer 30 formed by PVD. In some embodiments, layer 30 includes one of titanium, titanium nitride, tantalum, tantalum nitride, silicon oxide, silicon nitride, or similar materials. In some embodiments, layer 30 includes titanium nitride.

Referring to Figure 3F, layer 32 is formed on layer 30. Layer 32 is in contact with layer 30. A portion of layer 32 is formed within trench 29t. A portion of layer 32 fills trench 29t. In some embodiments, layer 32 includes metallic material. In some embodiments, layer 32 includes cobalt. In some embodiments, layer 32 is formed by plasma enhanced atomic layer deposition (ALD).

Referring to FIG. 3G, a thermal process is performed on the structure shown in FIG. 3F. In some embodiments, layer 30 serves as a diffusion barrier layer for forming structure 23 in substrate 20 . In some embodiments, layer 30 serves as a silicide phase change layer. During this thermal process, the material of layer 32 interacts with the material of substrate 20 and structure 23 is gradually formed from layer 30 toward well region 22 .

Structure 23 is in contact with layer 30 . In some embodiments, structures 23 are not on vertical surfaces 28's of layer 28'. In some embodiments, structure 23 does not contact layer 28'. In some embodiments, structure 23 does not contact layer 32. Structure 23 is formed in well area 22 . In some embodiments, structure 23 tapers from surface 20s1.

Referring to Figure 3H, layer 32 is removed. Layer 32 is removed by, for example, etching techniques. In some embodiments, etching techniques include dry etching, wet etching, or similar methods. In some embodiments, a portion of layer 30 is retained on spacer 25 and recess 20r of substrate 20 . In some embodiments, a portion of layer 28' is retained on sidewalls 29s of trench 29t.

Referring to Figure 3I, layer 28 may be formed on the structure shown in Figure 3H. In some embodiments, layer 28 is formed over the remainder of layer 30 and the remainder of layer 28'. In some embodiments, layer 28 may be formed by chemical vapor deposition (CVD). In some embodiments, layer 28 includes one of titanium, titanium nitride, tantalum, tantalum nitride, silicon oxide, silicon nitride, or similar materials. In some embodiments, layer 28 includes titanium nitride. The thickness of layer 28 can be adjusted as desired. In some embodiments, the total thickness of layer 28 and layer 28' may range from about 1 to 5 nanometers (nm). In some embodiments, the total thickness of layer 28 and layer 30 may range from approximately 1 to 5 nanometers. In some embodiments, the total thickness of layer 28 and layer 28' may be approximately 3 nanometers. In some embodiments, the total thickness of layer 28 and layer 30 may be about 3 nanometers.

Referring to Figure 3J, layer 29 may be formed on layer 28. In some embodiments, layer 28 acts as a barrier layer to prevent layer 29 from penetrating into substrate 20 . In some embodiments, layer 29 may be formed by chemical vapor deposition (CVD). Layer 29 is also formed within trench 29t. In some embodiments, layer 29 formed within trench 29t is conductive contact 29c. Conductive contact 29c is formed between gate structures 21a and 21b. In some embodiments, layer 29 includes metallic material. In some embodiments, layer 29 includes tungsten.

3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, and 3J illustrate various preparation stages of semiconductor device structures according to some embodiments of the present disclosure.

The stages of Figures 3A, 3B, 3C, 3D, 3F, 3G, 3H, 3I and 3J are the same as previously described. Figure 3E is performed after the stage of Figure 3D. Referring to Figure 3E, an amorphous implant (PAI) 31 is performed on layer 30. After PAI, the structure of layer 30 is degraded. In some embodiments, layer 30 becomes amorphous. Thereafter, the stages of Figure 3F, Figure 3G, Figure 3H, Figure 3I and Figure 3J follow the stage of Figure 3E. In some embodiments, the stages of Figure 3E may be optional. By implementing the stage of FIG. 3E , the amorphous atoms of layer 32 can more easily migrate into substrate 20 to form structure 23 .

3A, 3B, 3C, 3D, 3F, 3G, 3K, 3L, and 3M illustrate various preparation stages of semiconductor device structures according to some embodiments of the present disclosure.

The stages of Figures 3A, 3B, 3C, 3D, 3F and 3G are the same as previously described. Figures 3K, 3L and 3M are performed after the stage of Figure 3G.

Referring to FIG. 3K , layer 28 ′, layer 30 and layer 32 may be completely removed, leaving spacer 25 and recess 20r of substrate 20 exposed. Layer 28', layer 30 and layer 32 are removed by, for example, etching techniques. In some embodiments, etching techniques include dry etching, wet etching, or similar methods.

Referring to Figure 3L, layer 28 may be formed on the structure shown in Figure 3K. In some embodiments, layer 28 may be formed on spacer 25 and recess 20r of substrate 20 . In some embodiments, layer 28 is formed on sidewalls 29s of trench 29t. In some embodiments, layer 28 may be formed by chemical vapor deposition (CVD). In some embodiments, layer 28 includes one of titanium, titanium nitride, tantalum, tantalum nitride, silicon oxide, silicon nitride, or similar materials. In some embodiments, layer 28 includes titanium nitride. In some embodiments, the thickness of layer 28 can be adjusted as desired. In some embodiments, the thickness of layer 28 may range from approximately 1 to 5 nanometers. In some embodiments, layer 28 may be approximately 3 nanometers thick.

Referring to Figure 3M, layer 29 may be formed on layer 28. In some embodiments, layer 28 acts as a barrier layer to prevent layer 29 from penetrating into substrate 20 . In some embodiments, layer 29 may be formed by chemical vapor deposition (CVD). Layer 29 is also formed within trench 29t. In some embodiments, layer 29 formed within trench 29t is conductive contact 29c. Conductive contact 29c is formed between gate structures 21a and 21b. In some embodiments, layer 29 includes metallic material. In some embodiments, layer 29 includes tungsten.

3A, 3B, 3C, 3D, 3E, 3F, 3G, 3K, 3L, and 3M illustrate various preparation stages of semiconductor device structures according to some embodiments of the present disclosure.

The stages of Figures 3A, 3B, 3C, 3D, 3E, 3F, and 3G are the same as described before. Figures 3K, 3L and 3M are also the same as described above. Figures 3K, 3L and 3M are performed after the stage of Figure 3G.

FIG. 4 is a flowchart illustrating a method 40 for fabricating a semiconductor device structure according to various aspects of the present disclosure.

The preparation method 40 begins with operation S41, in which a substrate is provided. The substrate has a surface.

The manufacturing method 40 continues with operation S42, in which a first gate structure is formed. The first gate structure is formed on the surface.

The preparation method 40 continues with operation S43, in which a second gate structure is formed. The second gate structure is formed on the surface.

The preparation method 40 continues with operation S44, in which a first well region is formed in the substrate. The first well region is formed between the first gate structure and the second gate structure.

The manufacturing method 40 continues with operation S45, in which a conductive contact is formed in a trench. The trench is formed between the first gate structure and the second gate structure.

The preparation method 40 continues with operation S46, in which a first structure is formed in the first well region. The first structure tapers from a base of the conductive contact.

The preparation method 40 is only an example and is not intended to limit the disclosure beyond the scope explicitly mentioned in the patent application. Additional operations may be provided before, during, or after each operation of the preparation method 40, and some of the operations may be replaced, eliminated, or reorganized for other embodiments of the preparation method. In some embodiments, the preparation method 40 may also include operations not depicted in FIG. 4 .

5A and 5B are flow charts illustrating methods of fabricating semiconductor device structures in various aspects of the present disclosure.

Referring to FIG. 5A, the preparation method 50 begins with operation S51A, in which a substrate is provided. The substrate has a surface.

The manufacturing method 50 continues with operation S51B, in which a first gate structure and a second gate structure are formed. The first and second gate structures are formed on the surface of the substrate.

The manufacturing method 50 continues with operation S51C, in which a spacer is formed on the first and second gate structures.

The manufacturing method 50 continues with operation S51D, in which a trench is formed between the first and second gate structures. Operation S51D corresponds to the stage of Figure 3A.

The preparation method 50 continues with operation S51E, in which a first layer is formed on the substrate and the spacer. Operation S51E corresponds to the stage of Figure 3B. In some embodiments, the first layer includes titanium nitride.

The preparation method 50 continues with operation S51F, in which the portion of the first layer not formed on the sidewall of the trench is removed. Operation S51F corresponds to the stage of Figure 3C.

Referring to FIG. 5B, operation S51G follows operation S51F. The preparation method 50 continues with operation S51G, wherein a second layer is formed on the substrate and the spacer. Operation S51G corresponds to the stage of Figure 3D. In some embodiments, the second layer includes titanium nitride.

The preparation method 50 continues with operation S51H, in which a third layer is formed on the second layer. Operation S51H corresponds to the stage of Figure 3F. In some embodiments, the third layer includes cobalt.

The preparation method 50 continues with operation S51I, in which a first structure is formed in the substrate. The first structure tapers from the surface of the substrate. Operation S51I corresponds to the stage of Figure 3G.

The preparation method 50 continues with operation S51J, in which the third layer, and portions of the first and second layers are removed. Operation S51J corresponds to the stage of Figure 3H.

The preparation method 50 continues with operation S51K, in which a fourth layer is formed on the remaining portions of the first and second layers. Operation S51K corresponds to the stage of Figure 3I. In some embodiments, the fourth layer includes titanium nitride.

The preparation method 50 continues with operation S51L, in which a fifth layer is formed on the fourth layer. Operation S51L corresponds to the stage of Figure 3J. In some embodiments, the fifth layer includes tungsten.

The preparation method 50 is only an example and is not intended to limit the content of the present disclosure beyond the scope explicitly mentioned in the patent application. Additional operations may be provided before, during, or after each operation of the preparation method 50, and some of the described operations may be replaced, eliminated, or reorganized for additional embodiments of the preparation method. In some embodiments, the preparation method 50 may also include operations not depicted in Figures 5A and 5B.

6A and 6B are flow charts illustrating methods of fabricating semiconductor device structures in various aspects of the present disclosure.

Referring to FIG. 6A, the preparation method 60 begins with operation S61A, in which a substrate is provided. The substrate has a surface.

The manufacturing method 60 continues with operation S61B, in which a first gate structure and a second gate structure are formed. The first and second gate structures are formed on the surface of the substrate.

The manufacturing method 60 continues with operation S61C, in which a spacer is formed on the first and second gate structures.

The manufacturing method 60 continues with operation S61D, in which a trench is formed between the first and second gate structures. Operation S61D corresponds to the stage of Figure 3A.

The preparation method 60 continues with operation S61E, in which a first layer is formed on the substrate and the spacer. Operation S61E corresponds to the stage of Figure 3B. In some embodiments, the first layer includes titanium nitride.

The preparation method 60 continues with operation S61F, in which the portion of the first layer not formed on the trench sidewall is removed. Operation S61F corresponds to the stage of Figure 3C.

Referring to FIG. 6B, operation S61G follows operation S61F. The preparation method 60 continues with operation S61G, in which a second layer is formed on the substrate and the spacer. Operation S61G corresponds to the stage of Figure 3D. In some embodiments, the second layer includes titanium nitride.

The preparation method 60 continues with operation S61H, in which an amorphization implant is performed on the second layer. Operation S61H corresponds to the stage of Figure 3E.

The preparation method 60 continues with operation S61I, in which a third layer is formed on the second layer. Operation S61I corresponds to the stage of Figure 3F. In some embodiments, the third layer includes cobalt.

The preparation method 60 continues with operation S61J, in which a first structure is formed in the substrate. The first structure tapers from the surface of the substrate. Operation S61J corresponds to the stage of Figure 3G.

The preparation method 60 continues with operation S61K, in which the third layer, and portions of the first and second layers are removed. Operation S61K corresponds to the stage of Figure 3H.

The preparation method 60 continues with operation S61L, in which a fourth layer is formed on the remaining portions of the first and second layers. Operation S61L corresponds to the stage of Figure 3I. In some embodiments, the fourth layer includes titanium nitride.

The preparation method 60 continues with operation S61M, in which a fifth layer is formed on the fourth layer. Operation S61M corresponds to the stage of Figure 3J. In some embodiments, the fifth layer includes tungsten.

The preparation method 60 is only an example and is not intended to limit the content of the present disclosure beyond the scope explicitly stated in the patent application. Additional operations may be provided before, during, or after each operation of preparation method 60, and some of the described operations may be replaced, eliminated, or reorganized for additional embodiments of the preparation method. In some embodiments, the preparation method 60 may also include operations not depicted in Figures 6A and 6B.

7A and 7B are flowcharts illustrating methods of fabricating semiconductor device structures in various aspects of the present disclosure.

Referring to FIG. 7A, the preparation method 70 begins with operation S71A, in which a substrate is provided. The substrate has a surface.

The manufacturing method 70 continues with operation S71B, in which a first gate structure and a second gate structure are formed. The first and second gate structures are formed on the surface of the substrate.

The manufacturing method 70 continues with operation S71C, in which a spacer is formed on the first and second gate structures.

The manufacturing method 70 continues with operation S71D, in which a trench is formed between the first and second gate structures. Operation S71D corresponds to the stage of Figure 3A.

The preparation method 70 continues with operation S71E, in which a first layer is formed on the substrate and the spacer. Operation S71E corresponds to the stage of Figure 3B. In some embodiments, the first layer includes titanium nitride.

The preparation method 70 continues with operation S71F, in which the portion of the first layer not formed on the trench sidewall is removed. Operation S71F corresponds to the stage of Figure 3C.

Referring to FIG. 7B, operation S71G follows operation S71F. The preparation method 70 continues with operation S71G, wherein a second layer is formed on the substrate and the spacer. Operation S71G corresponds to the stage of Figure 3D. In some embodiments, the second layer includes titanium nitride.

The preparation method 70 continues with operation S71H, in which a third layer is formed on the second layer. Operation S71H corresponds to the stage of Figure 3F. In some embodiments, the third layer includes cobalt.

The preparation method 70 continues with operation S71I, in which a first structure is formed in the substrate. The first structure tapers from the surface of the substrate. Operation S71I corresponds to the stage of Figure 3G.

The preparation method 70 continues with operation S71J, where the first, second and third layers are removed. Operation S71J corresponds to the stage of Figure 3K.

The preparation method 70 continues with operation S71K, in which a fourth layer is formed on the substrate and the spacer. Operation S71K corresponds to the stage of Figure 3L. In some embodiments, the fourth layer includes titanium nitride.

The preparation method 70 continues with operation S71L, in which a fifth layer is formed on the fourth layer. Operation S71L corresponds to the stage of Figure 3M. In some embodiments, the fifth layer includes tungsten.

The preparation method 70 is only an example and is not intended to limit the content of the present disclosure beyond the scope explicitly stated in the patent application. Additional operations may be provided before, during, or after each operation of preparation method 70, and some of the operations described may be replaced, eliminated, or reorganized for additional embodiments of the preparation method. In some embodiments, the preparation method 70 may also include operations not depicted in Figures 7A and 7B.

8A and 8B are flow charts illustrating methods of fabricating semiconductor device structures in various aspects of the present disclosure.

Referring to FIG. 8A, the preparation method 80 begins with operation S81A, in which a substrate is provided. The substrate has a surface.

The preparation method 80 continues with operation S81B, in which a first gate structure and a second gate structure are formed on the substrate. The first and second gate structures are formed on the surface.

The manufacturing method 80 continues with operation S81C, in which a spacer is formed on the first and second gate structures.

The manufacturing method 80 continues with operation S81D, in which a trench is formed between the first and second gate structures. Operation S81D corresponds to the stage of Figure 3A.

The preparation method 80 continues with operation S81E, in which a first layer is formed on the substrate and the spacer. Operation S81E corresponds to the stage of Figure 3B. In some embodiments, the first layer includes titanium nitride.

The preparation method 80 continues with operation S81F, in which the portion of the first layer not formed on the trench sidewall is removed. Operation S81F corresponds to the stage of FIG. 3C.

Referring to FIG. 8B, operation S81G follows operation S81F. The preparation method 80 continues with operation S81G, wherein a second layer is formed on the substrate and the spacer. Operation S81G corresponds to the stage of Figure 3D. In some embodiments, the second layer includes titanium nitride.

The preparation method 80 continues with operation S81H, in which an amorphization implant is performed on the second layer. Operation S81H corresponds to the stage of Figure 3E.

The preparation method 80 continues with operation S81I, in which a third layer is formed on the second layer. Operation S81I corresponds to the stage of Figure 3F. In some embodiments, the third layer includes cobalt.

The preparation method 80 continues with operation S81J, in which a first structure is formed in the substrate. The first structure tapers from the surface of the substrate. Operation S81J corresponds to the stage of Figure 3G.

The preparation method 80 continues with operation S81K, where the first, second and third layers are removed. Operation S81K corresponds to the stage of Figure 3K.

The preparation method 80 continues with operation S81L, in which a fourth layer is formed on the substrate and the spacer. Operation S81L corresponds to the stage of Figure 3L. In some embodiments, the fourth layer includes titanium nitride.

The preparation method 80 continues with operation S81M, in which a fifth layer is formed on the fourth layer. Operation S81M corresponds to the stage of Figure 3M. In some embodiments, the fifth layer includes tungsten.

The preparation method 80 is merely an example and is not intended to limit the disclosure beyond the scope explicitly stated in the patent application. Additional operations may be provided before, during, or after each operation of the preparation method 80, and some of the described operations may be replaced, eliminated, or reorganized for additional embodiments of the preparation method. In some embodiments, the preparation method 80 may also include operations not depicted in Figures 8A and 8B.

FIG. 9A is a schematic top view illustrating the layout of the gate 101 ′ and the source/drain 102 ′ of the semiconductor device structure 1 ′ according to some comparative embodiments of the present disclosure.

Referring to FIG. 9A , the contact region 103' is separated from the gate region 101' by a distance L'. When the size of the semiconductor element structure 1 is reduced, the distance L' needs to be reduced accordingly, because when the gate length of the semiconductor element structure 1 is reduced, the threshold voltage of the semiconductor element structure 1 becomes difficult to control, which may lead to unexpected current leakage. . In a conventional process, cobalt silicide is formed on the contact sidewalls. The cobalt silicide may be oval in shape. Cobalt silicide formed on the contact sidewalls may cause current leakage. To prevent cobalt silicide from forming on the contact sidewalls, a layer of silicon nitride is formed on the contact sidewalls. Although the silicon nitride layer prevents cobalt silicide from forming on the sidewalls of the contact, it increases the contact resistance. The method disclosed herein eliminates the silicon nitride layer. Cobalt silicide is pyramid-shaped. Cobalt silicide allows the length L' to be reduced without causing current leakage and also reduces the contact resistance.

9B is a cross-sectional view illustrating a semiconductor device structure of some comparative embodiments of the present disclosure along the dotted line BB' shown in FIG. 9A.

Referring to FIG. 9B , the semiconductor device structure 1' may include a substrate 10', a gate structure 11', a conductive contact 19c', a drain region 12', a source region 13', a siliconized metal structure 14', and spacers 15' and 16 ', lightly doped drain (LDD) region 17' and halo region 18'. Substrate 10' may have surface 10s'. Gate structure 11' is formed on surface 10s'. Drain region 12' is formed below surface 10s'. Source region 13' is formed below surface 10s. A siliconized metal structure 14' is formed beneath the surface 10s'. The siliconized metal structure 14' has a curved/rounded profile. In some embodiments, the siliconized metal structure 14' is elliptical.

Referring to Figure 9B, portion 14a' of siliconized metal structure 14' is formed on sidewall 19s1' of conductive contact 19c', and portion 14b' of siliconized metal structure 14' is formed on sidewall 19s2' of conductive contact 19c'. Since the actual distance between portion 14a', conductive contact 19c' and gate structure 11' is less than distance L', current leakage from conductive contact 19c' to gate structure 11' is increased. Therefore, the performance of the semiconductor element structure 1' may be adversely affected.

The current path 19p' from the drain region 12' to the source region 13' is represented by a dashed line. When comparing the semiconductor element structure 1' shown in FIG. 9B with the semiconductor element structure 1 shown in FIG. 1B, the silicide metal structure (cobalt silicide) 14' shown in FIG. 9B is oval, while the silicide metal structure 14' shown in FIG. 1B Structure (cobalt silicide) 14 is pyramid-shaped. As mentioned before, cobalt silicide 14' is more likely to cause leakage current than cobalt silicide 14. When reducing the size of a semiconductor element, it is preferable to use cobalt silicide 14 instead of cobalt silicide 14'.

One aspect of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first gate structure, a second gate structure, a first well region and a first structure. The base has a first surface and a second surface opposite to the first surface. The first gate structure is disposed on the first surface. The second gate structure is disposed on the first surface. The first well region is located in the substrate between the first gate structure and the second gate structure. The first structure is disposed in the first well zone. The shape of the first structure has an acute angle.

Another aspect of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a substrate, a first gate structure, a second gate structure, a conductive contact, a first well region and a first structure. The substrate has a surface. The first gate structure is disposed on the surface. The second gate structure is disposed on the surface. The conductive contact is between the first gate structure and the second gate structure. The first well region is located in the substrate between the first gate structure and the second gate structure. The first structure is embedded in the first well region and tapers from a bottom of the conductive contact. The first structure includes cobalt silicide.

Another aspect of the present disclosure provides a method of fabricating a semiconductor device structure. The preparation method includes: providing a substrate having a surface; forming a first gate structure on the surface; forming a second gate structure on the surface; in the substrate and on the first gate A first well region is formed between the structure and the second gate structure; a conductive contact is formed in a trench between the first gate structure and the second gate structure; and in the first well region A first structure is formed therein, wherein the first structure tapers from a bottom of the conductive contact.

Embodiments of the present disclosure disclose a semiconductor device structure having metal silicide in a substrate. The metal silicide does not exist in the trench sidewalls between the gate structures of the semiconductor device structure. The contact resistance in the semiconductor element structure is thereby reduced. In addition, the semiconductor element structure includes a titanium nitride layer. The titanium nitride layer serves as a diffusion barrier layer for forming metal silicide. The thickness of the titanium nitride layer is adjustable to prevent metal silicide from forming on the trench sidewalls between the gate structures of the semiconductor device structure and to prevent an increase in contact resistance. In a comparative example, silicon oxide/silicon nitride is formed on the sidewalls of trenches between gate structures of semiconductor device structures. Silicon oxide/silicon nitride has a large contact resistance, thus increasing the contact resistance between the gate structure and the metal silicide. Compared with the comparative example, in the embodiment of the present disclosure, the thickness of titanium nitride can be adjusted to prevent metal silicide from forming on the trench sidewalls between the gate structures of the semiconductor device structure and prevent the contact resistance from increasing. Therefore, The performance of semiconductor device structures can be improved.

Although the disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the patent scope. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present disclosure is not limited to the specific embodiments of the process, machinery, manufacture, compositions of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure of this disclosure that they can use existing or future processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein in accordance with the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of the present disclosure.

1:Semiconductor component structure 1':Semiconductor element structure 2:Semiconductor component structure 10: Base 10s: Surface 10s': surface 10':Base 11: Gate structure 11': Gate structure 12: Drainage area 12': Drainage area 13: Source area 13': Source area 14: Siliconized metal structure 14': Siliconized metal structure 14a': part 14b': part 15: Gap 15': gap 16: Gap 16': gap 17: Lightly doped drain (LDD) region 17': Lightly doped drain (LDD) region 18: Halo zone 18':Halo area 19: Conductive contact 19c': Conductive contact 19p:Current path 19p': current path 19s1:Side wall 19s1':Side wall 19s2:Side wall 19s2': side wall 20: Base 20r: concave part 20s1: Surface 20s2: Surface 21a: Gate structure 21b: Gate structure 22:Well area 23: Structure 23A: acute angle 23C1: Section 23C2: Section 24: Gap 24a:Part 24b:Part 25: Gap 25a:Part 25b:Part 25c:Part 25d: part 26:Well area 26a:Part 26b:Part 27:Well area 28:Layer 28b: bottom 28s1: vertical surface 28':Layer 28's: vertical surface 29:Layer 29b: bottom 29c: Conductive contact 29s: Sidewall 29t:Trench 30:Layer 31:Amorphous implant 32:Layer 40:Preparation method 50:Preparation method 60:Preparation method 70:Preparation method 80:Preparation method 101: Gate area 101':gate 102: Source/drain area 102': Source/Drain 103:Contact area 103':Contact area A: Dotted rectangle A-A': dashed line B-B': dashed line L1:Length L2: length L': distance S41: Operation S42: Operation S43: Operation S44: Operation S45: Operation S46: Operation S51A: Operation S51B: Operation S51C: Operation S51D: Operation S51E: Operation S51F: Operation S51G: Operation S51H: Operation S51I: Operation S51J: Operation S51K: Operation S51L: Operation S61A: Operation S61B: Operation S61C: Operation S61D: Operation S61E: Operation S61F: Operation S61G: Operation S61H: Operation S61I: Operation S61J: Operation S61K: Operation S61L: Operation S61M: Operation S71A: Operation S71B: Operation S71C: Operation S71D: Operation S71E: Operation S71F: Operation S71G: Operation S71H: Operation S71I: Operation S71J: Operation S71K: Operation S71L: Operation S81A: Operation S81B: Operation S81C: Operation S81D: Operation S81E: Operation S81F: Operation S81G: Operation S81H: Operation S81I: Operation S81J: Operation S81K: Operation S81L: Operation S81M: Operation

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements. 1A is a schematic top view illustrating the layout of the gate and source/drain regions of a semiconductor device structure according to some embodiments of the present disclosure. FIG. 1B is a cross-sectional view illustrating a semiconductor device structure according to some embodiments of the present disclosure along the dotted line AA′ shown in FIG. 1A . 2A is a cross-sectional view illustrating the structure of a semiconductor device according to some embodiments of the present disclosure. FIG. 2B is an enlarged view of the dashed rectangle A shown in FIG. 2A illustrating some embodiments of the present disclosure. 3A, 3B, 3C, 3D, 3F, 3G, 3H, 3I, and 3J illustrate various preparation stages of semiconductor device structures according to some embodiments of the present disclosure. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, and 3J illustrate various preparation stages of semiconductor device structures according to some embodiments of the present disclosure. 3A, 3B, 3C, 3D, 3F, 3G, 3K, 3L, and 3M illustrate various preparation stages of semiconductor device structures according to some embodiments of the present disclosure. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3K, 3L, and 3M illustrate various preparation stages of semiconductor device structures according to some embodiments of the present disclosure. 4 is a flowchart illustrating a method of fabricating a semiconductor device structure according to various aspects of the present disclosure. 5A and 5B are flow charts illustrating methods of fabricating semiconductor device structures in various aspects of the present disclosure. 6A and 6B are flow charts illustrating methods of fabricating semiconductor device structures in various aspects of the present disclosure. 7A and 7B are flowcharts illustrating methods of fabricating semiconductor device structures in various aspects of the present disclosure. 8A and 8B are flow charts illustrating methods of fabricating semiconductor device structures in various aspects of the present disclosure. 9A is a schematic top view illustrating the layout of gate and source/drain regions of semiconductor device structures according to some comparative embodiments of the present disclosure. 9B is a cross-sectional view illustrating a semiconductor device structure of some comparative embodiments of the present disclosure along the dotted line BB' shown in FIG. 9A.

2:Semiconductor component structure

20: Base

20s1: Surface

20s2: Surface

21a: Gate structure

21b: Gate structure

22:Well area

23: Structure

24: Gap

24a:Part

24b:Part

25: Gap

25a:Part

25b:Part

25c:Part

25d: part

26:Well area

27:Well area

28:Layer

28s1: vertical surface

29:Layer

29c: Conductive contact

A: Dotted rectangle

Claims (20)

A semiconductor element structure includes: a substrate having a first surface and a second surface, the second surface being opposite to the first surface; a first gate structure disposed on the first surface; a second a gate structure disposed on the first surface; a first well region disposed in the substrate between the first gate structure and the second gate structure; and a first silicide metal structure, overall is disposed in the first well area, wherein the first silicide metal structure is a solid pyramid structure, and the cross section of the first silicide metal structure has an acute angle, and an upper surface of the first silicide metal structure is tied to the substrate below the first surface. The semiconductor device structure of claim 1, further comprising a first portion of a first spacer disposed on the first gate structure and a second portion of the first spacer disposed on the second gate structure. part. The semiconductor device structure as claimed in claim 2, further comprising a first part of a second spacer disposed on the first part of the first spacer and the second part of the second spacer disposed on the second part of the first spacer. The second part of the spacer. The semiconductor device structure as claimed in claim 2, wherein the first part of the first spacer is formed from The first gate structure extends continuously to the first well region. The semiconductor device structure of claim 2, wherein the first portion of the first spacer extends continuously from the first gate structure to a second well region in the substrate that is spaced apart from the first well region. The semiconductor device structure of claim 2, wherein the second portion of the first spacer is connected to a third well region in the substrate. The semiconductor device structure of claim 3, wherein the second spacer is encapsulated by the substrate and the first spacer. The semiconductor device structure of claim 3 further includes a first layer disposed on the second spacer. The semiconductor device structure of claim 7, further comprising a second layer disposed on the first layer, the second layer including a portion disposed between the first gate structure and the second gate structure. . The semiconductor device structure of claim 7, wherein the first siliconized metal structure is spaced apart from a vertical surface of the first layer. The semiconductor device structure of claim 1, wherein a first cross-section of the first silicide metal structure has a first length, and a second cross-section of the first silicide metal structure has a length different from a second length of the first length. The semiconductor device structure of claim 11, wherein the first siliconized metal structure gradually shrinks toward the second surface of the substrate. The semiconductor device structure of claim 11, wherein the first cross-section of the first siliconized metal structure is closer to the first surface than the second cross-section of the first siliconized metal structure, and the first length is greater than the first surface. Two lengths. The semiconductor device structure of claim 9, wherein the first layer includes a bottom embedded in the substrate, the first silicide metal structure is in contact with the bottom of the first layer, and the first silicide metal structure is Pyramid shape. The semiconductor device structure of claim 9, wherein the second layer includes tungsten, the first structure includes cobalt silicide, and the first layer includes titanium nitride. A semiconductor element structure includes: a substrate having a surface; a first gate structure disposed on the surface; a second gate structure disposed on the surface; and a conductive contact disposed on the first gate between the gate structure and the second gate structure; a first well region disposed in the substrate between the first gate structure and the second gate structure; and A first structure is integrally embedded in the first well region and is a solid pyramid structure tapering from a bottom of the conductive contact, wherein the first structure includes cobalt silicide, and an upper surface of the first structure Tie below the surface of the substrate. The semiconductor device structure of claim 16, further comprising a first portion of a first spacer disposed on the first gate structure and a second portion of the first spacer disposed on the second gate structure. part. The semiconductor device structure as claimed in claim 16, further comprising a first part of a second spacer disposed on the first part of the first spacer and the second part of the second spacer disposed on the second part of the first spacer. The second part of the spacer. The semiconductor device structure of claim 16, wherein the first structure has an acute angle, a vertical surface of the first layer does not contain the first structure, and the first structure is disposed below the conductive contact. The semiconductor device structure of claim 16, further comprising a first layer covering the conductive contact, wherein the first structure is in contact with the first layer.