TWI794062B - Method for preparing semiconductor device structure - Google Patents

Abstract

A method for manufacturing semiconductor device structure includes providing a substrate having a surface; forming a first gate structure on the surface; forming a second gate structure on the surface; forming a first well region in the substrate and between the first gate structure and the second gate structure; forming a conductive contact within a trench between the first gate structure and the second gate structure; forming a first structure in the first well region, wherein the first structure tapers away from a bottom portion of the conductive contact.

Description

Fabrication method of semiconductor device structure

This application claims priority to US Patent Application Nos. 17/562,362 and 17/562,210 (ie, the priority date is "December 27, 2021"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor structure, and more particularly to a semiconductor device structure including a cobalt silicide structure with an acute angle.

As the area occupied by the integrated circuit decreases, the distance between the contact and the gate structure decreases accordingly, which may lead to source/drain leakage. Silicon oxide or silicon nitride can be used to prevent metal silicide from forming on the contact side surface of the semiconductor device. However, silicon oxide or silicon nitride may cause an increase in contact resistance, thereby adversely affecting the performance of semiconductor devices.

The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" shall not form part of this case.

One aspect of the present disclosure provides a semiconductor device structure. The semiconductor element structure includes a base, a first gate structure, a second gate structure, a first well region and a first structure. The base has a first surface and a second surface opposite to the first surface. The first gate structure is disposed on the first surface. The second gate structure is disposed on the first surface. The first well region is located in the substrate and between the first gate structure and the second gate structure. The first structure is disposed in the first well region. The shape of the first structure has an acute angle.

Another aspect of the disclosure provides a semiconductor device structure. The semiconductor device structure includes a base, a first gate structure, a second gate structure, a conductive contact, a first well region and a first structure. The base has a surface. The first gate structure is disposed on the surface. The second gate structure is disposed on the surface. The conductive contact is located between the first gate structure and the second gate structure. The first well region is located in the substrate and between the first gate structure and the second gate structure. The first structure is embedded in the first well region and gradually narrows from a bottom of the conductive contact. The first structure includes cobalt silicide.

Another aspect of the disclosure provides a method for fabricating a semiconductor device structure. The preparation method includes: providing a substrate, the substrate has a surface; forming a first gate structure on the surface; forming a second gate structure on the surface; in the substrate and on the first gate forming a first well region between the structure and the second gate structure; forming a conductive contact in a trench between the first gate structure and the second gate structure; and forming a conductive contact in the first well region A first structure is formed, wherein the first structure tapers from a bottom of the conductive contact.

Embodiments of the disclosure disclose a semiconductor device structure with a metal silicide in a substrate. The aforementioned metal silicide does not exist on the trench sidewalls between the gate structures of the semiconductor device structure. The contact resistance in the structure of the semiconductor component is thus reduced. In addition, the semiconductor element structure includes a titanium nitride layer. The titanium nitride layer acts as a diffusion barrier layer for forming metal silicide. The thickness of the titanium nitride layer is adjustable to prevent metal silicide from forming on the trench sidewall between the gate structures of the semiconductor element structure and to prevent the contact resistance from increasing. In a comparative example, silicon oxide/silicon nitride is formed on trench sidewalls between gate structures of semiconductor device structures. Silicon oxide/silicon nitride has a higher contact resistance, thus increasing the contact resistance between the gate structure and the metal silicide. Compared with the comparative example, in the embodiment of the present disclosure, the thickness of titanium nitride can be adjusted to prevent metal silicide from forming on the sidewall of the trench between the gate structures of the semiconductor device structure and prevent the contact resistance from increasing, so The performance of the semiconductor element structure can be improved.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

Embodiments, or examples, of the present disclosure illustrated in the drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are considered to be within the ordinary skill of the art to which this disclosure pertains. Reference numerals may be repeated throughout the embodiments, but there is no intention that features of one embodiment apply to another, even if they share the same reference numeral.

It will be understood that although the terms first, second, third etc. may be used to describe various elements, elements, regions, layers or sections. can be used to describe various elements, components, regions, layers or sections but these elements, components, regions, layers or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms unless the context clearly dictates otherwise. It should be further understood that when the terms "comprising" and "comprising" are used in this specification, they point out the existence of said features, integers, steps, operations, elements or elements, but do not exclude the existence or addition of one or more other features, An integer, step, operation, element, component, or group thereof.

Please refer to FIG. 1A and FIG. 1B . FIG. 1A is a schematic top view of the layout of the semiconductor device structure 1 . The layout includes a gate region 101 and a source/drain region 102 . FIG. 1B is a cross-sectional view of the semiconductor device structure 1 along the dotted line AA' shown in FIG. 1A .

1A, the distance L between the contact region 103 and the gate region 101, when the size of the semiconductor element structure 1 is reduced, the distance L needs to be reduced accordingly, because, when the gate length of the semiconductor element structure 1 is reduced, the semiconductor element structure The threshold voltage (threshold voltage) of 1 becomes difficult to control, which may cause unintended current leakage. In conventional processes, cobalt silicide is formed on the sidewalls of the contacts. The cobalt silicide may be oval. Cobalt silicide formed on the sidewall of the contact may cause current leakage. To prevent cobalt silicide from forming on the sidewalls of the contacts, a layer of silicon nitride is formed on the sidewalls of the contacts. Although the silicon nitride layer prevents cobalt silicide from forming on the sidewalls of the contact, it increases contact resistance. The method disclosed herein eliminates the silicon nitride layer. Cobalt silicide is pyramidal. Cobalt silicide allows reducing the length L without causing current leakage and also reduces contact resistance.

Referring to FIG. 1B, the semiconductor device structure 1 may include a substrate 10, a gate structure 11, a drain region 12, a source region 13, a silicide metal structure 14, spacers 15 and 16, and a lightly doped drain (LDD) region 17. , halo region 18 and conductive contact 19c. For the sake of brevity, some elements of the semiconductor device structure 1 are omitted in FIG. 1B .

The substrate 10 may have a surface 10s. A gate structure 11 is formed on the surface 10s. The drain region 12 is formed below the surface 10s. Source region 13 is formed below surface 10s. A metal silicide structure 14 is formed under the surface 10s. The metal silicide structure 14 may be pyramid-shaped. The metal silicide structure 14 may be conical. In some embodiments, the cross section of the metal silicide structure 14 may be triangular. The conductive contact 19c includes sidewalls 19s1 and 19s2. The sidewalls 19s1 and 19s2 of the conductive contact 19c do not contain the metal silicide structure 14 . The suicide metal structure 14 is spaced apart from the sidewalls 19s1 and 19s2 of the conductive contact 19c.

The dashed line shows the current path 19p through the conductive contact 19c and from the drain region 12 to the source region 13 . Using the metal silicide structure 14, the resistance of the conductive contact 19c can be reduced.

Along with the shrinkage of the semiconductor device structure 1, the distance between the drain region 12 and the source region 13 is also reduced accordingly, which makes the carrier (carrier) at the junction (junction) at both ends of the gate structure 11 in a large electric field under the action of accelerating forward. In some embodiments, an LDD region 17 is formed near the junction of the drain region 12 and one end of the gate structure 11 . In some embodiments, another LDD region 17 is formed near the junction between the source region 13 and the other end of the gate structure 11 . The LDD region 17 can reduce the number of carriers at the junction, thus reducing the hot carrier effect of the semiconductor device structure 1 . In some embodiments, LDD region 17 is adjacent to gate structure 11 and formed using a different dopant material having the same conductivity type as drain region 12 and source region 13 .

In some embodiments, halo region 18 is a doped region formed beside drain region 12 and source region 13 . In some embodiments, halo region 18 is formed deeper in substrate 10 than LDD region 17 . The halo region 18 is formed to increase the threshold voltage of the semiconductor device structure 1 . The halo region 18 can reduce the short channel effect of the semiconductor element structure 1 . In some embodiments, halo region 18 is formed using a dopant material of the same conductivity type as substrate 10 .

FIG. 2A is a cross-sectional view illustrating the semiconductor device structure of some embodiments of the present disclosure. Referring to FIG. 2A , the semiconductor device structure 2 may include a substrate 20 , gate structures 21 a and 21 b , a structure 23 , spacers 24 and 25 , and layers 28 and 29 . The substrate 20 may have a surface (or upper surface) 20s1 and a surface (or lower surface) 20s2. The surface 20s1 is opposed to the surface 20s2. In this disclosure, the surface 20s1 may also be called an active surface. In this disclosure, the surface 20s2 may also be referred to as a rear side surface.

Substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. In some embodiments, the substrate 20 includes a first conductivity type. In some embodiments, the first conductivity type is p-type. In some embodiments, the p-type dopant includes boron (B), other Group III elements, or any combination thereof. In some embodiments, the first conductivity type is n-type. In some embodiments, the n-type dopant includes arsenic (As), phosphorus (P), other Group V elements, or any combination thereof.

Gate structures 21a and 21b are formed on surface 20s1. Spacer 24 may include two portions 24a and 24b. In some embodiments, portion 24a of spacer 24 is formed on gate structure 21a. In some embodiments, portion 24b of spacer 24 is formed on gate structure 21b. The semiconductor component structure 2 includes spacers 25 . Spacer 25 includes portions 25 a and 25 b formed on portions 24 a and 24 b of spacer 24 . The spacer 25 includes portions 25c and 25d between the base 20 and the spacer 24 . In some embodiments, portion 25a of spacer 25 is formed on portion 24a of spacer 24 . In some embodiments, portion 25b of spacer 25 is formed on portion 24b of spacer 24 .

A well region 22 is formed in the substrate 20 . A well region 22 is formed below the surface 20s1. Well region 22 is formed between gate structures 21a and 21b. In some embodiments, the well region 22 includes a second conductivity type different from the first conductivity type of the substrate 20 . Structure 23 is formed in substrate 20 . In some embodiments, structure 23 is formed in well region 22 . In some embodiments, structure 23 is embedded within well region 22 .

In some embodiments, portion 24a of spacer 24 extends continuously from gate structure 21a to well region 22 . In some embodiments, portion 24b of spacer 24 extends continuously from gate structure 21b to well region 22 . In some embodiments, portions 25c and 25d of spacer 25 are encapsulated by substrate 20 and spacer 24 .

Well region 26 is formed in substrate 20 . In some embodiments, well region 26 is formed below surface 20s1. In some embodiments, well region 26 is embedded within substrate 20 . In some embodiments, well region 26 includes a second conductivity type different from the first conductivity type of substrate 20 . In some embodiments, portion 24 a of spacer 24 is in contact with well region 26 . In some embodiments, portion 24 a of spacer 24 extends continuously from gate structure 21 a to well region 26 of substrate 20 . In some embodiments, well region 26 is spaced apart from well region 22 .

A well region 27 is formed in the substrate 20 . In some embodiments, well region 27 is formed below surface 20s1. In some embodiments, well region 27 is embedded within substrate 20 . In some embodiments, well region 27 includes the second conductivity type, which is different from the first conductivity type of substrate 20 . In some embodiments, portion 24b of spacer 24 is in contact with well region 27 . In some embodiments, portion 24b of spacer 24 extends continuously from gate structure 21b to well region 27 of substrate 20 . In some embodiments, well region 27 is spaced apart from well region 22 .

Layer 28 is formed on spacer 25 . In some embodiments, structure 23 is in contact with layer 28 . In some embodiments, vertical surface 28s of layer 28 is free of structures 23 . In some embodiments, structure 23 is spaced apart from vertical surface 28s1 of layer 28 . In some embodiments, layer 28 includes a metal oxide. In some embodiments, layer 28 includes a metal nitride. In some embodiments, layer 28 includes metal suicide. In some embodiments, layer 28 includes titanium nitride. In some embodiments, the thickness of layer 28 can be adjusted as desired.

Layer 29 is formed on layer 28 . In some embodiments, layer 28 acts as a barrier layer to isolate layer 29 from substrate 20 and spacers 25 . Layer 29 includes a conductive contact 29c disposed between gate structures 21a and 21b. A conductive contact 29c may be disposed within the trench between gate structures 21a and 21b. Structure 23 is disposed below conductive contact 29c. In some embodiments, layer 28 covers three sidewalls of conductive contact 29c. Layer 28 is formed on the sidewalls of conductive contact 29c. In some embodiments, layer 29 includes a metallic material. In some embodiments, layer 29 includes tungsten.

FIG. 2B is an enlarged view of the dotted rectangle A shown in FIG. 2A. In some embodiments, the cross-section of structure 23 has an acute angle 23A. In some embodiments, structure 23 may be pyramid-shaped. In some embodiments, the structure 23 tapers toward the surface 20s2 of the substrate 20 . In some embodiments, vertical surface 28s1 of layer 28 is free of structures 23 . In some embodiments, structure 23 is spaced apart from vertical surface 28s1 of layer 28 .

In some embodiments, structure 23 includes a metal silicide. In some embodiments, structure 23 includes cobalt suicide. In some embodiments, cross-section 23C1 of structure 23 is closer to surface 20s1 than cross-section 23C2 of structure 23 . Section 23C1 of structure 23 has a length L1. Section 23C2 of structure 23 has a length L2. In some embodiments, length L2 is different from length L1. In some embodiments, length L1 is greater than length L2.

In some embodiments, layer 28 includes a base 28b embedded within substrate 20 . In some embodiments, structure 23 is in contact with bottom 28b of layer 28 . In some embodiments, bottom 29b of layer 29 is in contact with bottom 28b of layer 28 . Structure 23 tapers from bottom 28b of layer 28 . Structure 23 tapers from bottom 29b of conductive contact 29c.

3A, 3B, 3C, 3D, 3F, 3G, 3H, 3I and 3J illustrate various stages of fabrication of semiconductor device structures according to some embodiments of the present disclosure.

Referring to Figure 3A, a substrate 20 may be provided. The gate structure 21a may be formed on the surface 20s1 of the substrate 201 . The gate structure 21b may be formed on the surface 20s1 of the substrate 20 . Well region 22 may be formed in substrate 20 . In some embodiments, well region 22 may be formed between gate structures 21a and 21b. Spacers 24 may be formed on the gate structures 21a and 21b. A spacer 25 may be formed on the spacer. A well region 26 may be formed in substrate 20 . In some embodiments, the well region 26 may be formed under the surface 20s1 of the substrate 201 .

In some embodiments, a portion of spacer 24 is in contact with well region 26 . In some embodiments, a portion of spacer 24 is embedded in well region 26 . Well region 27 may be formed in substrate 20 . The well region 27 may be formed under the surface 20s1 of the substrate 201 . In some embodiments, a portion of spacer 24 is in contact with well region 27 . In some embodiments, a portion of spacer 24 is embedded in well region 27 . In some embodiments, the base 20 has a recess 2Or. The recess 20r is recessed below the surface 20s1. In some embodiments, a trench 29 t is formed between the gate structures 21 a and 21 b , the trench 29 t is bounded by the spacer 25 and the recess 20 r of the substrate 20 .

Referring to FIG. 3B , a layer 28 ′ may be formed on the spacer 25 . Layer 28' may be formed by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), flowable CVD (FCVD), spin coating, sputtering, or the like. The layer 28 ′ is also formed on the recess 20 r of the substrate 20 and the sidewalls of the trench 29 t. In some embodiments, layer 28' includes one of titanium, titanium nitride, tantalum, tantalum nitride, silicon oxide, silicon nitride, or similar materials. In some embodiments, layer 28' includes titanium nitride.

Referring to FIG. 3C, a portion of layer 28' is removed, while a portion of layer 28' formed on sidewall 29s of trench 29t remains. In some embodiments, layer 28' formed on spacer 25 is removed. In some embodiments, a portion of layer 28' formed on recess 2Or of substrate 20 is removed. This portion of layer 28' can be removed by, for example, etching techniques. In some embodiments, etching techniques include dry etching, wet etching, or similar techniques. In some embodiments, layer 28' acts to prevent formation of structure 23 shown in FIG. 2A on sidewall 29s of trench 29t.

Referring to FIG. 3D , a layer 30 is formed on the spacer 25 and the recess 20r of the substrate 20 . In some embodiments, layer 30 is formed at the bottom of trench 29t. In some embodiments, layer 30 may be formed by, for example, physical vapor deposition (PVD). Layer 28' formed by CVD is deposited at a different concentration than layer 30 formed by PVD. The crystalline density of layer 28' formed by CVD is different from that of layer 30 formed by PVD. In some embodiments, layer 30 includes one of titanium, titanium nitride, tantalum, tantalum nitride, silicon oxide, silicon nitride, or similar materials. In some embodiments, layer 30 includes titanium nitride.

Referring to FIG. 3F , layer 32 is formed on layer 30 . Layer 32 is in contact with layer 30 . A portion of layer 32 is formed within trench 29t. A portion of layer 32 fills trench 29t. In some embodiments, layer 32 includes a metallic material. In some embodiments, layer 32 includes cobalt. In some embodiments, layer 32 is formed by plasma enhanced atomic layer deposition (ALD).

Referring to FIG. 3G, a thermal process is performed on the structure shown in FIG. 3F. In some embodiments, layer 30 acts as a diffusion barrier layer for forming structure 23 in substrate 20 . In some embodiments, layer 30 functions as a silicide phase change layer. During this thermal process, the material of layer 32 interacts with the material of substrate 20 , and structure 23 is gradually formed from layer 30 to well region 22 .

Structure 23 is in contact with layer 30 . In some embodiments, structures 23 are not on vertical surfaces 28's of layer 28'. In some embodiments, structure 23 is not in contact with layer 28'. In some embodiments, structure 23 is not in contact with layer 32 . Structure 23 is formed in well region 22 . In some embodiments, structures 23 taper from surface 20s1.

Referring to Figure 3H, layer 32 is removed. Layer 32 is removed by, for example, etching techniques. In some embodiments, etching techniques include dry etching, wet etching, or the like. In some embodiments, a portion of layer 30 is retained on spacer 25 and recess 20 r of substrate 20 . In some embodiments, a portion of layer 28' is retained on sidewall 29s of trench 29t.

Referring to FIG. 3I, layer 28 may be formed on the structure shown in FIG. 3H. In some embodiments, layer 28 is formed over the remainder of layer 30 and the remainder of layer 28'. In some embodiments, layer 28 may be formed by chemical vapor deposition (CVD). In some embodiments, layer 28 includes one of titanium, titanium nitride, tantalum, tantalum nitride, silicon oxide, silicon nitride, or similar materials. In some embodiments, layer 28 includes titanium nitride. The thickness of layer 28 can be adjusted as desired. In some embodiments, the combined thickness of layers 28 and 28' may be in the range of about 1 to 5 nanometers (nm). In some embodiments, the total thickness 30 of layers 28 and 30 may be in the range of approximately 1 to 5 nanometers. In some embodiments, the combined thickness of layer 28 and layer 28' may be about 3 nanometers. In some embodiments, the combined thickness of layers 28 and 30 may be about 3 nanometers.

Referring to FIG. 3J , layer 29 may be formed on layer 28 . In some embodiments, layer 28 acts as a barrier layer to prevent penetration of layer 29 into substrate 20 . In some embodiments, layer 29 may be formed by chemical vapor deposition (CVD). Layer 29 is also formed within trench 29t. In some embodiments, layer 29 formed within trench 29t is conductive contact 29c. A conductive contact 29c is formed between gate structures 21a and 21b. In some embodiments, layer 29 includes a metallic material. In some embodiments, layer 29 includes tungsten.

3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I and 3J illustrate various stages of fabrication of semiconductor device structures according to some embodiments of the present disclosure.

The stages of Figures 3A, 3B, 3C, 3D, 3F, 3G, 3H, 3I and 3J are the same as previously described. Figure 3E is performed after the stage of Figure 3D. Referring to FIG. 3E , an amorphization implant (PAI) 31 is performed on layer 30 . After PAI, the structure of layer 30 is degraded. In some embodiments, layer 30 becomes amorphous. Thereafter, the stages of Figures 3F, 3G, 3H, 3I and 3J follow the stages of Figure 3E. In some embodiments, the stages of Figure 3E may be optional. By implementing the stage of FIG. 3E , the amorphous atoms of layer 32 can more easily migrate into substrate 20 to form structure 23 .

3A, 3B, 3C, 3D, 3F, 3G, 3K, 3L and 3M illustrate various stages of fabrication of semiconductor device structures according to some embodiments of the present disclosure.

The stages of Figures 3A, 3B, 3C, 3D, 3F and 3G are the same as previously described. Figures 3K, 3L and 3M follow the stage of Figure 3G.

Referring to FIG. 3K, layer 28', layer 30, and layer 32 may be completely removed, leaving spacer 25 and recess 20r of substrate 20 exposed. Layer 28', layer 30, and layer 32 are removed by, for example, etching techniques. In some embodiments, etching techniques include dry etching, wet etching, or the like.

Referring to FIG. 3L, layer 28 may be formed on the structure shown in FIG. 3K. In some embodiments, layer 28 may be formed on spacer 25 and recess 20 r of substrate 20 . In some embodiments, layer 28 is formed on sidewalls 29s of trench 29t. In some embodiments, layer 28 may be formed by chemical vapor deposition (CVD). In some embodiments, layer 28 includes one of titanium, titanium nitride, tantalum, tantalum nitride, silicon oxide, silicon nitride, or similar materials. In some embodiments, layer 28 includes titanium nitride. In some embodiments, the thickness of layer 28 can be adjusted as desired. In some embodiments, layer 28 may have a thickness in the range of about 1 to 5 nanometers. In some embodiments, layer 28 may be about 3 nanometers thick.

Referring to FIG. 3M , layer 29 may be formed on layer 28 . In some embodiments, layer 28 acts as a barrier layer to prevent penetration of layer 29 into substrate 20 . In some embodiments, layer 29 may be formed by chemical vapor deposition (CVD). Layer 29 is also formed within trench 29t. In some embodiments, layer 29 formed within trench 29t is conductive contact 29c. A conductive contact 29c is formed between gate structures 21a and 21b. In some embodiments, layer 29 includes a metallic material. In some embodiments, layer 29 includes tungsten.

3A, 3B, 3C, 3D, 3E, 3F, 3G, 3K, 3L, and 3M illustrate various fabrication stages of semiconductor device structures according to some embodiments of the present disclosure.

The stages of Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D, Fig. 3E, Fig. 3F, Fig. 3G are the same as previously described. Figure 3K, Figure 3L and Figure 3M are also the same as previously described. Figures 3K, 3L and 3M are performed after the stage of Figure 3G.

FIG. 4 is a flowchart illustrating a method 40 of fabricating a semiconductor device structure according to various aspects of the present disclosure.

The manufacturing method 40 starts with operation S41, wherein a substrate is provided. The base has a surface.

The manufacturing method 40 continues with operation S42, wherein a first gate structure is formed. The first gate structure is formed on the surface.

The manufacturing method 40 continues with operation S43, wherein a second gate structure is formed. The second gate structure is formed on the surface.

The manufacturing method 40 continues with operation S44, wherein a first well region is formed in the substrate. The first well region is formed between the first gate structure and the second gate structure.

The manufacturing method 40 continues with operation S45 , wherein a conductive contact is formed in a trench. The trench is formed between the first gate structure and the second gate structure.

The manufacturing method 40 continues with operation S46, wherein a first structure is formed in the first well region. The first structure tapers gradually from a bottom of the conductive contact.

The preparation method 40 is only an illustration, and is not intended to limit the present disclosure beyond the scope explicitly mentioned in the patent claims. Additional operations may be provided before, during, or after each operation of manufacturing method 40, and some of the operations described may be replaced, eliminated, or reorganized for other embodiments of the manufacturing method. In some embodiments, preparation method 40 may also include operations not depicted in FIG. 4 .

5A and 5B are flow charts illustrating methods of fabricating semiconductor device structures according to various aspects of the present disclosure.

Referring to FIG. 5A , the manufacturing method 50 begins with operation S51A, in which a substrate is provided. The base has a surface.

The manufacturing method 50 continues with operation S51B, wherein a first gate structure and a second gate structure are formed. The first and the second gate structures are formed on the surface of the substrate.

The fabrication method 50 continues with operation S51C, wherein a spacer is formed on the first and the second gate structures.

The fabrication method 50 continues with operation S51D, wherein a trench is formed between the first and the second gate structures. Operation S51D corresponds to the stage of FIG. 3A.

The manufacturing method 50 continues with operation S51E, wherein a first layer is formed on the substrate and the spacer. Operation S51E corresponds to the stage of FIG. 3B. In some embodiments, the first layer includes titanium nitride.

Manufacturing method 50 continues with operation S51F, wherein the portion of the first layer not formed on the sidewall of the trench is removed. Operation S51F corresponds to the stage of FIG. 3C.

Referring to FIG. 5B , operation S51G follows operation S51F. The manufacturing method 50 continues with operation S51G, wherein a second layer is formed on the substrate and the spacer. Operation S51G corresponds to the stage of FIG. 3D. In some embodiments, the second layer includes titanium nitride.

The manufacturing method 50 continues with operation S51H, wherein a third layer is formed on the second layer. Operation S51H corresponds to the stage of FIG. 3F. In some embodiments, the third layer includes cobalt.

The manufacturing method 50 continues with operation S51I, wherein a first structure is formed in the substrate. The first structure tapers from the surface of the substrate. Operation S51I corresponds to the stage of FIG. 3G.

The manufacturing method 50 continues with operation S51J, wherein the third layer, and portions of the first and second layers are removed. Operation S51J corresponds to the stage of FIG. 3H.

The manufacturing method 50 proceeds to operation S51K, wherein a fourth layer is formed on the remaining portions of the first and second layers. Operation S51K corresponds to the stage of FIG. 3I. In some embodiments, the fourth layer includes titanium nitride.

The manufacturing method 50 continues with operation S51L, wherein a fifth layer is formed on the fourth layer. Operation S51L corresponds to the stage of FIG. 3J . In some embodiments, the fifth layer includes tungsten.

The preparation method 50 is only an illustration, and is not intended to limit the content of the present disclosure beyond the scope explicitly mentioned in the patent claims. Additional operations may be provided before, during, or after each operation of manufacturing method 50, and some of the operations described may be replaced, eliminated, or reorganized for additional embodiments of the manufacturing method. In some embodiments, preparation method 50 may also include operations not depicted in FIGS. 5A and 5B .

6A and 6B are flowcharts illustrating methods of fabricating semiconductor device structures according to various aspects of the present disclosure.

Referring to FIG. 6A, the manufacturing method 60 begins with operation S61A, in which a substrate is provided. The base has a surface.

The manufacturing method 60 continues with operation S61B, wherein a first gate structure and a second gate structure are formed. The first and the second gate structures are formed on the surface of the substrate.

The fabrication method 60 continues with operation S61C, wherein a spacer is formed on the first and the second gate structures.

Fabrication method 60 continues with operation S61D, wherein a trench is formed between the first and second gate structures. Operation S61D corresponds to the stage of FIG. 3A.

The manufacturing method 60 continues with operation S61E, wherein a first layer is formed on the substrate and the spacer. Operation S61E corresponds to the stage of FIG. 3B. In some embodiments, the first layer includes titanium nitride.

Manufacturing method 60 continues with operation S61F, wherein the portion of the first layer not formed on the sidewall of the trench is removed. Operation S61F corresponds to the stage of FIG. 3C.

Referring to FIG. 6B , operation S61G follows operation S61F. The manufacturing method 60 continues with operation S61G, wherein a second layer is formed on the substrate and the spacer. Operation S61G corresponds to the stage of FIG. 3D. In some embodiments, the second layer includes titanium nitride.

Fabrication method 60 continues with operation S61H, wherein an amorphization implant is performed on the second layer. Operation S61H corresponds to the stage of FIG. 3E.

The manufacturing method 60 continues with operation S61I, wherein a third layer is formed on the second layer. Operation S61I corresponds to the stage of FIG. 3F. In some embodiments, the third layer includes cobalt.

The manufacturing method 60 continues with operation S61J, wherein a first structure is formed in the substrate. The first structure tapers from the surface of the substrate. Operation S61J corresponds to the stage of FIG. 3G.

Manufacturing method 60 continues with operation S61K, wherein the third layer, and portions of the first and second layers are removed. Operation S61K corresponds to the stage of FIG. 3H.

Manufacturing method 60 continues with operation S61L, wherein a fourth layer is formed on the remaining portions of the first and second layers. Operation S61L corresponds to the stage of FIG. 3I. In some embodiments, the fourth layer includes titanium nitride.

Manufacturing method 60 continues with operation S61M, wherein a fifth layer is formed on the fourth layer. Operation S61M corresponds to the stage of Fig. 3J. In some embodiments, the fifth layer includes tungsten.

The preparation method 60 is just an example, and is not intended to limit the content of the present disclosure beyond the scope explicitly stated in the patent claims. Additional operations may be provided before, during, or after each operation of manufacturing method 60, and some of the operations described may be replaced, eliminated, or reorganized for additional embodiments of the manufacturing method. In some embodiments, preparation method 60 may also include operations not depicted in FIGS. 6A and 6B .

7A and 7B are flowcharts illustrating methods of fabricating semiconductor device structures according to various aspects of the present disclosure.

Referring to FIG. 7A, the manufacturing method 70 begins with operation S71A, in which a substrate is provided. The base has a surface.

The manufacturing method 70 continues with operation S71B, wherein a first gate structure and a second gate structure are formed. The first and the second gate structures are formed on the surface of the substrate.

The fabrication method 70 continues with operation S71C, wherein a spacer is formed on the first and the second gate structures.

The fabrication method 70 continues with operation S71D, wherein a trench is formed between the first and the second gate structures. Operation S71D corresponds to the stage of FIG. 3A.

The manufacturing method 70 continues with operation S71E, wherein a first layer is formed on the substrate and the spacer. Operation S71E corresponds to the stage of FIG. 3B. In some embodiments, the first layer includes titanium nitride.

Manufacturing method 70 continues with operation S71F, wherein the portion of the first layer not formed on the sidewall of the trench is removed. Operation S71F corresponds to the stage of FIG. 3C.

Referring to FIG. 7B , operation S71G follows operation S71F. The manufacturing method 70 continues with operation S71G, wherein a second layer is formed on the substrate and the spacer. Operation S71G corresponds to the stage of FIG. 3D. In some embodiments, the second layer includes titanium nitride.

The manufacturing method 70 continues with operation S71H, wherein a third layer is formed on the second layer. Operation S71H corresponds to the stage of FIG. 3F. In some embodiments, the third layer includes cobalt.

The manufacturing method 70 continues with operation S71I, wherein a first structure is formed in the substrate. The first structure tapers from the surface of the substrate. Operation S71I corresponds to the stage of FIG. 3G.

The manufacturing method 70 continues with operation S71J, wherein the first, the second and the third layers are removed. Operation S71J corresponds to the stage of FIG. 3K.

The manufacturing method 70 continues with operation S71K, wherein a fourth layer is formed on the substrate and the spacer. Operation S71K corresponds to the stage of FIG. 3L. In some embodiments, the fourth layer includes titanium nitride.

Manufacturing method 70 continues with operation S71L, wherein a fifth layer is formed on the fourth layer. Operation S71L corresponds to the stage of FIG. 3M. In some embodiments, the fifth layer includes tungsten.

The preparation method 70 is only an example, and is not intended to limit the content of the present disclosure beyond the scope explicitly stated in the patent claims. Additional operations may be provided before, during, or after each operation of the manufacturing method 70, and some of the operations described may be replaced, eliminated, or reorganized for additional embodiments of the manufacturing method. In some embodiments, preparation method 70 may also include operations not depicted in FIGS. 7A and 7B .

8A and 8B are flowcharts illustrating methods of fabricating semiconductor device structures according to various aspects of the present disclosure.

Referring to FIG. 8A, the manufacturing method 80 begins with operation S81A, in which a substrate is provided. The base has a surface.

The fabrication method 80 continues with operation S81B, wherein a first gate structure and a second gate structure are formed on the substrate. The first and the second gate structures are formed on the surface.

The fabrication method 80 continues with operation S81C, wherein a spacer is formed on the first and the second gate structures.

The fabrication method 80 continues with operation S81D, wherein a trench is formed between the first and the second gate structures. Operation S81D corresponds to the stage of FIG. 3A.

The manufacturing method 80 continues with operation S81E, wherein a first layer is formed on the substrate and the spacer. Operation S81E corresponds to the stage of FIG. 3B. In some embodiments, the first layer includes titanium nitride.

Manufacturing method 80 continues with operation S81F, wherein the portion of the first layer not formed on the sidewall of the trench is removed. Operation S81F corresponds to the stage of FIG. 3C.

Referring to FIG. 8B , operation S81G follows operation S81F. The manufacturing method 80 continues with operation S81G, wherein a second layer is formed on the substrate and the spacer. Operation S81G corresponds to the stage of FIG. 3D. In some embodiments, the second layer includes titanium nitride.

Fabrication method 80 continues with operation S81H, wherein an amorphization implant is performed on the second layer. Operation S81H corresponds to the stage of FIG. 3E.

The manufacturing method 80 continues with operation S81I, wherein a third layer is formed on the second layer. Operation S81I corresponds to the stage of FIG. 3F. In some embodiments, the third layer includes cobalt.

The manufacturing method 80 continues with operation S81J, wherein a first structure is formed in the substrate. The first structure tapers from the surface of the substrate. Operation S81J corresponds to the stage of FIG. 3G.

The manufacturing method 80 continues with operation S81K, wherein the first, the second and the third layers are removed. Operation S81K corresponds to the stage of FIG. 3K.

The manufacturing method 80 continues with operation S81L, wherein a fourth layer is formed on the substrate and the spacer. Operation S81L corresponds to the stage of FIG. 3L. In some embodiments, the fourth layer includes titanium nitride.

The manufacturing method 80 continues with operation S81M, wherein a fifth layer is formed on the fourth layer. Operation S81M corresponds to the stage of FIG. 3M. In some embodiments, the fifth layer includes tungsten.

The preparation method 80 is merely an illustration, and is not intended to limit the present disclosure beyond what is expressly stated in the claims. Additional operations may be provided before, during, or after each operation of manufacturing method 80, and some of the operations described may be replaced, eliminated, or reorganized for additional embodiments of the manufacturing method. In some embodiments, preparation method 80 may also include operations not depicted in FIGS. 8A and 8B .

9A is a schematic top view illustrating the layout of the gate 101 ′ and the source/drain 102 ′ of the semiconductor device structure 1 ′ of some comparative embodiments of the present disclosure.

Referring to FIG. 9A, the contact region 103' is separated from the gate region 101' by a distance L'. When the size of the semiconductor element structure 1 is reduced, the distance L' needs to be reduced accordingly, because when the gate length of the semiconductor element structure 1 is reduced, the threshold voltage of the semiconductor element structure 1 becomes difficult to control, which may cause unexpected current leakage . In a conventional process, cobalt silicide is formed on the sidewalls of the contacts. The cobalt silicide may be oval. Cobalt silicide formed on the sidewall of the contact may cause current leakage. To prevent cobalt silicide from forming on the sidewalls of the contacts, a layer of silicon nitride is formed on the sidewalls of the contacts. Although the silicon nitride layer prevents cobalt silicide from forming on the sidewalls of the contact, it increases contact resistance. The method disclosed herein eliminates the silicon nitride layer. Cobalt silicide is pyramidal. Cobalt silicide allows reducing the length L' without causing current leakage and also reduces contact resistance.

FIG. 9B is a cross-sectional view illustrating semiconductor device structures of some comparative embodiments of the present disclosure along the dotted line BB′ shown in FIG. 9A .

Referring to FIG. 9B, the semiconductor device structure 1' may include a substrate 10', a gate structure 11', a conductive contact 19c', a drain region 12', a source region 13', a metal silicide structure 14', spacers 15' and 16 ', lightly doped drain (LDD) region 17' and halo region 18'. The substrate 10' may have a surface 10s'. A gate structure 11' is formed on the surface 10s'. A drain region 12' is formed below the surface 10s'. A source region 13' is formed below the surface 10s. A metal silicide structure 14' is formed below the surface 10s'. The metal silicide structure 14' has a curved/circular profile. In some embodiments, the metal suicide structure 14' is elliptical.

Referring to FIG. 9B, a portion 14a' of the metal silicide structure 14' is formed on the sidewall 19s1' of the conductive contact 19c', and a portion 14b' of the metal silicide structure 14' is formed on the sidewall 19s2' of the conductive contact 19c'. Since the actual distance between portion 14a', conductive contact 19c' and gate structure 11' is less than distance L', current leakage from conductive contact 19c' to gate structure 11' is increased. Consequently, the performance of the semiconductor element structure 1' may be adversely affected.

The current path 19p' from the drain region 12' to the source region 13' is indicated by a dotted line. When comparing the semiconductor device structure 1' shown in FIG. 9B with the semiconductor device structure 1 shown in FIG. 1B, the metal silicide structure (cobalt silicide) 14' shown in FIG. Structure (cobalt silicide) 14 is pyramidal. As mentioned above, cobalt silicide 14 ′ is more likely to cause leakage current than cobalt silicide 14 . When reducing the size of semiconductor devices, it is preferable to use cobalt silicide 14 instead of cobalt silicide 14'.

One aspect of the present disclosure provides a semiconductor device structure. The semiconductor element structure includes a base, a first gate structure, a second gate structure, a first well region and a first structure. The base has a first surface and a second surface opposite to the first surface. The first gate structure is disposed on the first surface. The second gate structure is disposed on the first surface. The first well region is located in the substrate and between the first gate structure and the second gate structure. The first structure is disposed in the first well region. The shape of the first structure has an acute angle.

Another aspect of the disclosure provides a semiconductor device structure. The semiconductor device structure includes a base, a first gate structure, a second gate structure, a conductive contact, a first well area and a first structure. The base has a surface. The first gate structure is disposed on the surface. The second gate structure is disposed on the surface. The conductive contact is located between the first gate structure and the second gate structure. The first well region is located in the substrate and between the first gate structure and the second gate structure. The first structure is embedded in the first well region and gradually narrows from a bottom of the conductive contact. The first structure includes cobalt silicide.

Another aspect of the disclosure provides a method for fabricating a semiconductor device structure. The preparation method includes: providing a substrate, the substrate has a surface; forming a first gate structure on the surface; forming a second gate structure on the surface; in the substrate and on the first gate forming a first well region between the structure and the second gate structure; forming a conductive contact in a trench between the first gate structure and the second gate structure; and forming a conductive contact in the first well region A first structure is formed, wherein the first structure tapers from a bottom of the conductive contact.

Embodiments of the disclosure disclose a semiconductor device structure with a metal silicide in a substrate. The aforementioned metal silicide does not exist on the trench sidewalls between the gate structures of the semiconductor device structure. The contact resistance in the structure of the semiconductor component is thus reduced. In addition, the semiconductor element structure includes a titanium nitride layer. The titanium nitride layer acts as a diffusion barrier layer for forming metal silicide. The thickness of the titanium nitride layer is adjustable to prevent metal silicide from forming on the trench sidewall between the gate structures of the semiconductor element structure and to prevent the contact resistance from increasing. In a comparative example, silicon oxide/silicon nitride is formed on trench sidewalls between gate structures of semiconductor device structures. Silicon oxide/silicon nitride has a higher contact resistance, thus increasing the contact resistance between the gate structure and the metal silicide. Compared with the comparative example, in the embodiment of the present disclosure, the thickness of titanium nitride can be adjusted to prevent metal silicide from forming on the sidewall of the trench between the gate structures of the semiconductor device structure and prevent the contact resistance from increasing, so The performance of the semiconductor element structure can be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and substitutions can be made hereto without departing from the spirit and scope of the present disclosure as defined by the disclosed claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the disclosure is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that they can use existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machinery, manufacture, material composition, means, methods, or steps are included in the scope of the patent disclosure of this disclosure.

1: Semiconductor element structure 1': Semiconductor device structure 2: Semiconductor element structure 10: Base 10s: surface 10s': surface 10': base 11:Gate structure 11': gate structure 12: Drain area 12': Drain area 13: Source area 13': source region 14: Metal silicide structure 14': metal silicide structure 14a': part 14b': part 15: spacer 15': spacer 16: spacer 16': spacer 17: Lightly doped drain (LDD) region 17': Lightly doped drain (LDD) region 18: halo area 18': halo area 19: Conductive contact 19c': Conductive contact 19p: current path 19p': current path 19s1: side wall 19s1': side wall 19s2: side wall 19s2': side wall 20: base 20r: concave part 20s1: Surface 20s2: Surface 21a:Gate structure 21b:Gate structure 22: Well area 23: Structure 23A: acute angle 23C1: Profile 23C2: Profile 24: spacer 24a: part 24b: part 25: spacer 25a: part 25b: part 25c: part 25d: part 26: well area 26a: part 26b: part 27: well area 28: layer 28b: bottom 28s1: Vertical surfaces 28': layers 28's: vertical surface 29: layers 29b: Bottom 29c: Conductive contact 29s: side wall 29t: Groove 30: layers 31: Amorphization Implantation 32: layer 40: Preparation method 50: Preparation method 60: Preparation method 70: Preparation method 80: Preparation method 101: gate area 101': Gate 102: source/drain region 102': source/drain 103: Contact area 103': contact area A: dotted rectangle A-A': dotted line BB': dotted line L1: Length L2: Length L': distance S41: Operation S42: Operation S43: Operation S44: Operation S45: Operation S46: Operation S51A: Operation S51B: Operation S51C: Operation S51D: Operation S51E: Operation S51F: Operation S51G: Operation S51H: Operation S51I: Operation S51J: Operation S51K: Operation S51L: Operation S61A: Operation S61B: Operation S61C: Operation S61D: Operation S61E: Operation S61F: Operation S61G: Operation S61H: Operation S61I: Operation S61J: Operation S61K: Operation S61L: Operation S61M: Operation S71A: Operation S71B: Operation S71C: Operation S71D: Operation S71E: Operation S71F: Operation S71G: Operation S71H: Operation S71I: Operation S71J: Operation S71K: Operation S71L: Operation S81A: Operation S81B: Operation S81C: Operation S81D: Operation S81E: Operation S81F: Operation S81G: Operation S81H: Operation S81I: Operation S81J: Operation S81K: Operation S81L: Operation S81M: Operation

The disclosure content of the present application can be understood more comprehensively when referring to the embodiments and the patent scope of the application for combined consideration of the drawings, and the same reference numerals in the drawings refer to the same components. FIG. 1A is a schematic top view illustrating the layout of gate and source/drain regions of a semiconductor device structure according to some embodiments of the present disclosure. FIG. 1B is a cross-sectional view illustrating the semiconductor device structure of some embodiments of the present disclosure along the dotted line AA′ shown in FIG. 1A . FIG. 2A is a cross-sectional view illustrating the semiconductor device structure of some embodiments of the present disclosure. FIG. 2B is an enlarged view illustrating the dashed rectangle A shown in FIG. 2A of some embodiments of the present disclosure. 3A, 3B, 3C, 3D, 3F, 3G, 3H, 3I and 3J illustrate various stages of fabrication of semiconductor device structures according to some embodiments of the present disclosure. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I and 3J illustrate various stages of fabrication of semiconductor device structures according to some embodiments of the present disclosure. 3A, 3B, 3C, 3D, 3F, 3G, 3K, 3L and 3M illustrate various stages of fabrication of semiconductor device structures according to some embodiments of the present disclosure. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3K, 3L, and 3M illustrate various fabrication stages of semiconductor device structures according to some embodiments of the present disclosure. FIG. 4 is a flowchart illustrating a method of fabricating a semiconductor device structure according to various aspects of the present disclosure. 5A and 5B are flow charts illustrating methods of fabricating semiconductor device structures according to various aspects of the present disclosure. 6A and 6B are flowcharts illustrating methods of fabricating semiconductor device structures according to various aspects of the present disclosure. 7A and 7B are flowcharts illustrating methods of fabricating semiconductor device structures according to various aspects of the present disclosure. 8A and 8B are flowcharts illustrating methods of fabricating semiconductor device structures according to various aspects of the present disclosure. 9A is a schematic top view illustrating the layout of the gate and source/drain regions of the semiconductor device structures of some comparative embodiments of the present disclosure. FIG. 9B is a cross-sectional view illustrating semiconductor device structures of some comparative embodiments of the present disclosure along the dotted line BB′ shown in FIG. 9A .

2: Semiconductor element structure

20: base

20s1: Surface

20s2: Surface

21a:Gate structure

21b:Gate structure

22: Well area

23: Structure

24: spacer

24a: part

24b: part

25: spacer

25a: part

25b: part

25c: part

25d: part

26: well area

27: well area

28: layer

28s1: Vertical surfaces

29: layers

29c: Conductive contact

A: dotted rectangle

Claims (12)

A method for preparing a semiconductor element structure, comprising: providing a substrate, the substrate has a surface; forming a first gate structure on the surface; forming a second gate structure on the surface; A first well region is formed between the first gate structure and the second gate structure; a conductive contact is formed in a trench between the first gate structure and the second gate structure; A first structure is formed in the first well region, wherein the first structure gradually shrinks from a bottom of the conductive contact; a first spacer is formed on the first gate structure and the second gate structure; forming a second spacer on the first spacer; forming a first layer on the second spacer by chemical vapor deposition (CVD); and removing the part of the first layer other than the trench sidewall. The manufacturing method as claimed in claim 1, further comprising forming a second layer on the substrate and the second spacer. The manufacturing method as claimed in claim 1, further comprising performing an implantation on the second layer. The preparation method as claimed in claim 1, further comprising forming a third layer on the second layer. The preparation method as claimed in claim 3 further includes forming a third layer on the second layer. The manufacturing method as claimed in claim 4, further comprising forming the first structure by a thermal process. The preparation method according to claim 6, further comprising removing the first layer, the second layer and the third layer. The manufacturing method as claimed in claim 7, further comprising forming a fourth layer on the substrate and the second spacer. The manufacturing method as claimed in claim 8, further comprising forming a fifth layer on the fourth layer. The preparation method as claimed in claim 7, wherein the first structure is not present on a vertical surface of the first layer. The preparation method as claimed in item 7, wherein the third layer is removed, and a part of the first layer and the second layer are retained. The preparation method as claimed in item 7, wherein the first layer, the second layer and the third layer are removed.

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