JP2011151318A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a leakage current and parasitic resistance by suppressing diffusion of metallic elements from a silicide layer while keeping interface resistance between the silicide layer and a silicon low. <P>SOLUTION: A semiconductor device 100 includes: a substrate 1 (semiconductor layer); a semiconductor electrode 10 which is formed contacting to the substrate 1 and has reverse conductive type to the substrate 1; the silicide layer 14 formed on the semiconductor electrode 10 while contacting to the semiconductor electrode 10; and a gettering layer 12 which is formed while separated from the junction between the substrate 1 and the semiconductor electrode 10 and from the silicide layer 14, respectively, inside the gettering layer 12, for gettering the metallic elements contained in the silicide layer 14. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a silicide layer.

  In recent years, with the development of information communication equipment and digital video equipment, the processing capability required for LSIs has become higher and the speed of MIS field effect transistors has been increased. This increase in speed has been promoted mainly by miniaturization and densification of the structure.

  In particular, LSIs for digital video equipment and game machines that must process a large amount of data at high speed cannot satisfy the processing capacity of cache memory with conventional embedded SRAM alone. The realizable DRAM has been mixed.

  In a mixed DRAM in which a DRAM is mixed with a logic operation transistor, the DRAM transistor is manufactured in the same manufacturing process as the logic operation transistor. However, the logic operation transistor and the DRAM transistor have different characteristics, for example, the DRAM transistor requires a very low leakage current, while the logic operation transistor does not cause a significant leakage current. Is needed. For this reason, the embedded DRAM has a problem in that it is difficult to reduce the leakage current as in a general-purpose DRAM manufactured exclusively for DRAM.

  For example, in a transistor for logic operation, a salicide process is performed in which a silicide layer is formed in a self-aligned manner on the source / drain electrodes of the transistor in order to reduce the connection resistance with the contact. Therefore, in the embedded DRAM, the salicide process is performed even for the DRAM transistor. However, when the silicide layer is formed, if there are dislocations or stacking faults in the source / drain electrodes, the metal elements constituting the silicide diffuse along the dislocations or stacking faults and react with surrounding silicon. It becomes easy. If a spike-shaped silicide occurs along dislocations, stacking faults, etc., and the silicide layer reaches the PN junction of the source / drain electrodes, it becomes a serious source of leakage.

  Japanese Patent Laid-Open No. 2005-268272 discloses a method in which a silicidation reaction suppression region is provided immediately below a silicide layer.

  In Patent Document 2 (Japanese Patent Laid-Open No. 2006-108703), a high concentration layer with many residual defects is provided in a source / drain region immediately below a silicide layer so as to disperse abnormal growth of the silicide and keep the abnormal growth at a shallow position. The configuration is described.

  Japanese Patent Laid-Open No. 11-214328 discloses a configuration in which a gettering region containing F is formed immediately below a silicide.

  Patent Document 4 (Japanese Patent Laid-Open No. 2005-259956) discloses a semiconductor substrate having an element isolation region, a diffusion region formed in the semiconductor substrate, a gate electrode formed on the semiconductor substrate, and the diffusion region. And an n-type MOSFET having an F-containing NiSi layer containing F atoms.

  In Patent Document 5 (Japanese Patent Laid-Open No. 2008-300831), an amorphous silicon layer is formed on a substrate, and the amorphous silicon layer is crystallized into a polycrystalline silicon layer using a crystallization-inducing metal. To form a metal layer pattern or a metal silicide layer pattern in contact with a certain region above or below the polycrystalline silicon layer corresponding to a region other than the channel region formed in the polycrystalline silicon layer, and heat treating the substrate. A polycrystal for gettering a crystallization-inducing metal existing in a region where a channel region is formed in the polycrystalline silicon layer to a region in the polycrystalline silicon layer corresponding to the region where the metal layer pattern or the metal silicide layer pattern is formed A method for manufacturing a silicon layer is described.

  The document includes the following description. In the region in the polycrystalline silicon layer corresponding to the region where the metal layer pattern or the metal silicide layer pattern is formed, the metal of the metal layer pattern is combined with the polycrystalline silicon layer to form a metal silicide or the metal silicide layer pattern. Metal silicide moves to the region. Therefore, when heat treatment is performed, the crystallization-inducing metal moves randomly and diffuses into a region in the polycrystalline silicon layer corresponding to the region where the metal layer pattern or the metal silicide layer pattern is formed, and exists in this region. Is thermodynamically stable. Thereby, the crystallization-inducing metal is gettered.

  Further, in this document, in order to increase the gettering effect, an n-type impurity or a p-type impurity is further implanted into a region in the semiconductor layer corresponding to a region where the metal layer pattern or the metal silicide layer pattern is formed, It is also described that a damage region is formed in this region using ions or plasma.

JP 2005-268272 A JP 2006-108703 A JP 11-214328 A JP 2005-259956 A JP 2008-300831 A

B. Colombeau et. Al., “Electrical Deactivation and Diffusion of Boron in Preamorphized Ultrashallow Junctions: Interstitial Transport and F co-implant Control”, IEDM 2004 Technical Digest, pages 971-974

  However, as described in Patent Document 3 and Patent Document 4, when impurities such as fluorine are added to getter the metal constituting the silicide, the activation rate of the dopant in the active region such as the source / drain region is The solid solubility limit can be lowered, and the interfacial resistance between silicide and silicon (also referred to as contact resistance or contact resistance) can be increased. For example, Non-Patent Document 1 describes that boron and fluorine form a complex to promote inactivation of boron.

  Further, depending on the impurities added to the gettering region, there is a possibility of affecting the quality of the silicide. For example, when oxygen is used as an impurity, the silicidation reaction is hindered by the presence of oxygen, which causes a problem that good silicide cannot be formed. Further, when a gettering region is formed using crystal defects, there arises a problem that silicide is formed in a spike shape only in a portion where the crystal defect exists, and silicide having a large film thickness variation is formed.

  In the technique described in Patent Document 5, the crystallization-inducing metal existing in the region where the channel region is formed is allowed to pass through the junction between the channel region and the source / drain region, thereby forming a metal layer pattern or a metal silicide layer pattern. The region is moved to a region in the polycrystalline silicon layer corresponding to the region where is formed. Therefore, the crystallization-inducing metal is unevenly distributed at the interface, which causes a problem that junction leakage is likely to occur.

According to the present invention,
A semiconductor layer;
A semiconductor electrode formed in contact with the semiconductor layer and having a conductivity type opposite to that of the semiconductor layer;
A silicide layer formed on and in contact with the semiconductor electrode;
Inside the semiconductor electrode, a gettering layer that is formed separately from the junction between the semiconductor layer and the semiconductor electrode and the silicide layer, and getters a metal element,
A semiconductor device is provided.

According to the present invention,
A method of manufacturing a semiconductor device including a silicide layer,
A step of forming a semiconductor electrode that is provided in contact with the semiconductor layer and includes a gettering layer for gettering a metal element at a position away from the junction with the semiconductor layer, and having a conductivity type opposite to that of the semiconductor layer;
After the step of forming the semiconductor electrode, a step of contacting the semiconductor electrode on the semiconductor electrode and forming a silicide layer at a position away from the gettering layer;
A method for manufacturing a semiconductor device is provided.

  According to this configuration, the silicide layer and the gettering layer are formed apart from each other. Therefore, when the silicide layer is formed, the presence of the gettering layer does not affect the silicide layer. Thereby, the silicide layer can be connected well, and the interface resistance between the silicide layer and the semiconductor electrode can be kept low.

  In addition, since the presence of the gettering layer does not affect the silicide layer, the formation conditions of the gettering layer can be selected without worrying about the quality of the silicide layer.

  Furthermore, since the gettering layer is separated from the junction between the semiconductor electrode and the semiconductor layer, junction leakage can be reduced.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between methods, apparatuses, and the like are also effective as an aspect of the present invention.

  According to the present invention, it is possible to suppress the diffusion of the metal element from the silicide layer and reduce the leakage current and the parasitic resistance while keeping the interface resistance between the silicide layer and silicon low.

It is sectional drawing which shows an example of a structure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is sectional drawing which shows an example of a structure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is a figure which shows the procedure for demonstrating the mechanism in which the crystal defect which functions as a gettering layer is formed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same constituent elements are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

(First embodiment)
FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to the present embodiment.
The semiconductor device 100 includes a substrate 1 (semiconductor layer), an element isolation insulating film 2 formed on the substrate 1, and an element formation region surrounded by the element isolation insulating film 2. The substrate 1 can be a semiconductor substrate such as a silicon substrate.

  In the element formation region of the semiconductor device 100, there is an MIS field effect transistor including the semiconductor electrode 10 functioning as a source / drain electrode and a gate constituted by the gate insulating film 3, the gate electrode 4, and the sidewall spacer 6. It is formed. The semiconductor electrode 10 is formed in contact with the substrate 1. Here, the semiconductor electrode 10 can be of a conductivity type opposite to that of the substrate 1.

  In this embodiment, the semiconductor device 100 includes a silicide layer 14 formed on the semiconductor electrode 10 so as to be in contact with the semiconductor electrode 10 and a junction (PN junction) between the substrate 1 and the semiconductor electrode 10 inside the semiconductor electrode 10. ) And the silicide layer 14, and a gettering layer 12 for gettering a metal element. The gettering layer 12 can getter the metal element contained in the silicide layer 14. In the present embodiment, the silicide layer 14 may be a silicide containing nickel such as nickel silicide. In the present embodiment, the semiconductor electrode 10 includes the source / drain extension region 5, the source / drain region 7 (first impurity diffusion region), the gettering layer 12, and the raised source / drain region 13 (second region). Impurity diffusion region). The raised source / drain region 13 can be configured to rise from the main surface of the substrate 1 (a portion raised from the main surface of the semiconductor layer). Here, the impurity diffusion region has a general meaning of a region where impurities are added to the semiconductor, and does not stick to adding impurities only by diffusion. For example, the semiconductor crystal is epitaxially grown while adding impurities.

  The semiconductor device 100 includes an insulating film 60 formed on the substrate 1 and covering the gate, and a contact 62 formed in the insulating film 60 and connected to the semiconductor electrode 10 through the silicide layer 14. Here, although the insulating film 60 is shown as a single layer, the insulating film 60 may have a laminated structure of a plurality of insulating films, and may include, for example, a liner insulating film. Although not shown here, in this embodiment, the semiconductor electrode 10 can be connected to a charge storage type storage device such as a storage node of a DRAM through a silicide layer 14. .

Next, a manufacturing procedure of the semiconductor device 100 in the present embodiment will be described. 2 and 3 are process cross-sectional views illustrating the manufacturing procedure of the semiconductor device according to the present embodiment.
First, the element isolation insulating film 2 is formed on the substrate 1. The element isolation insulating film 2 can be a field oxide film, for example. Subsequently, a gate insulating film 3 is formed on the substrate 1. Next, the gate electrode 4 is formed on the gate insulating film 3. Thereafter, impurities are doped on the surface of the substrate 1 by ion implantation using the gate electrode 4 and the gate insulating film 3 as a mask to form source / drain extension regions 5. Subsequently, an insulating film such as a silicon oxide film is deposited on the entire surface by a CVD (Chemical Vapor Deposition) method, and side walls are formed on the side walls of the gate insulating film 3 and the gate electrode 4 by anisotropic etching. A spacer 6 is formed. Thereby, the semiconductor device 100 having the configuration shown in FIG. 2A is obtained.

  Next, using the gate electrode 4 and the sidewall spacer 6 as a mask, impurities are doped on the surface of the substrate 1 by ion implantation and activated by heat treatment to form deep source / drain regions 7 (FIG. 2B).

  Thereafter, using the gate electrode 4 and the sidewall spacer 6 as a mask, the source / drain region 7 is partially etched by anisotropic etching to form a digging region 11 (FIG. 2C). . Here, the digging region 11 is formed so as not to reach the PN junction between the substrate 1 and the source / drain region 7. That is, the digging region 11 can be formed so that the substrate 1 is not exposed, and the source / drain region 7 is exposed at the bottom and side surfaces of the digging region 11.

  Subsequently, the surface of the source / drain region 7 exposed at the bottom of the dug region 11 is ion-implanted with a shallow impurity and subjected to heat treatment, and the gettering layer 12 functioning as a gettering site for the metal element constituting the silicide layer 14. Is formed (FIG. 3A). The gettering layer 12 is formed so as not to reach the PN junction between the substrate 1 and the source / drain region 7. At this time, heat treatment is performed so that the amorphous layer does not remain on the surface of the gettering layer 12. This facilitates selective growth of silicon in the subsequent backfilling process.

  In this embodiment mode, the impurity to be ion-implanted can be an element in which a region functioning as a gettering site for the metal element forming the silicide layer 14 is formed by ion-implanting the impurity into the semiconductor. . The impurity to be ion-implanted can be configured to include at least one of carbon, oxygen, nitrogen, fluorine, or a rare gas element, for example.

In the present embodiment, the impurity to be ion-implanted can be carbon, for example. Carbon forms several forms of Si—C clusters in silicon, and these Si—C clusters can induce strain fields to getter metal elements. Carbon can also be single carbon ions, but can also be cluster carbon ions instead of single carbon ions. As the cluster carbon ion, for example, C ₇ H ₇ , C ₁₄ H ₁₄ , C ₁₆ H _{10 and the} like can be used. By using cluster carbon, impurities can be implanted shallowly, and the gettering layer 12 can be easily formed so as not to reach the PN junction between the substrate 1 and the source / drain region 7.

  Subsequently, while doping impurities having the same conductivity type as the source / drain extension regions 5 and the source / drain regions 7, a crystal layer is formed on the digging region 11 by a selective growth method, and the raised source / drain regions 13 are formed. (FIG. 3B).

  Next, a metal layer is formed on the entire surface of the substrate 1, and the silicide layer 14 is formed by reacting the metal element of the metal layer with silicon at a portion where the metal layer is in contact with silicon by heat treatment. Thereafter, the unreacted metal layer is removed (FIG. 3C). Here, the metal layer can be a nickel layer. In this case, the silicide layer 14 can be nickel silicide. In the present embodiment, the silicide layer 14 is formed so as not to contact the gettering layer 12.

  Although not shown, when the gate electrode 4 is made of a silicon material, a silicide layer can be formed on the surface of the gate electrode 4 in the step of forming the silicide layer 14.

  Thereafter, an insulating film 60 is formed on the substrate 1 so as to cover the gate. Subsequently, after forming a contact hole reaching the silicide layer 14 on the semiconductor electrode 10 in the insulating film 60, the contact 62 is filled with a conductive material, thereby forming a contact 62. With the above procedure, the semiconductor device 100 having the configuration shown in FIG. 1 is obtained.

  In the present embodiment, the silicide layer 14 and the gettering layer 12 are formed apart from each other. Therefore, when the silicide layer 14 is formed, the presence of the gettering layer 12 does not affect the silicide layer 14. Thereby, the silicide layer 14 can be connected well, and the interface resistance between the silicide layer 14 and the semiconductor electrode 10 can be kept low.

  Further, since the presence of the gettering layer 12 does not affect the silicide layer 14, the formation conditions of the gettering layer 12 can be selected without worrying about the quality of the silicide layer 14.

  Furthermore, since the gettering layer 12 is formed when the silicide layer 14 is formed, diffusion of metal elements from the silicide layer 14 or the metal layer for forming the silicide layer 14 is suppressed, and leakage current and parasitic resistance are reduced. Can be small.

  Furthermore, since the gettering layer 12 is separated from the PN junction between the semiconductor electrode 10 and the substrate 1, junction leakage can be reduced.

  Further, in this embodiment, after the gettering layer 12 is formed on the source / drain region 7, the raised source / drain region 13 is formed on the gettering layer 12. Therefore, the distance between the silicide layer 14 and the gettering layer 12 can be raised by the source / drain region 13, the distance between the junction interface between the substrate 1 and the semiconductor electrode 10 and the gettering layer 12, and the semiconductor The margin of the distance between the interface between the electrode 10 and the silicide layer 14 and the gettering layer 12 can be increased, and the degree of manufacturing freedom can be increased.

(Second Embodiment)
FIG. 4 is a cross-sectional view showing an example of the configuration of the semiconductor device 100 in the present embodiment.
In the present embodiment, the configurations of the semiconductor electrode 10 and the gettering layer are different from those of the first embodiment. In the present embodiment, the second recrystallization region 24 including crystal defects is used as the gettering layer.

  In the present embodiment, the semiconductor electrode 10 includes a source / drain extension region 5, a source / drain region 7, a second recrystallization region 24, a first recrystallization region 23, and a raised source / drain region 25. Consists of. The raised source / drain region 25 can be raised from the main surface of the substrate 1.

  In the present embodiment, the silicide layer 26 can be the same as the silicide layer 14 described in the first embodiment.

Next, a manufacturing procedure of the semiconductor device 100 in the present embodiment will be described. 5 and 6 are process cross-sectional views illustrating the manufacturing procedure of the semiconductor device 100 according to the present embodiment.
The procedure shown in FIGS. 5A and 5B can be the same as the procedure described with reference to FIGS. 2A and 2B in the first embodiment. .

  Thereafter, using the gate electrode 4 and the side wall spacer 6 as a mask, an impurity 51 is ion-implanted into the source / drain region 7, and the first region 21, which is an amorphous region, is formed on the surface of the source / drain region 7 (impurity diffusion region). In addition, a second region 22 including atomic vacancies and interstitial atoms is formed under the first region 21 (FIG. 5C). Here, the first region 21 and the second region 22 are formed so as not to contact the PN junction between the substrate 1 and the source / drain region 7.

The impurity 51 can be the same element as that constituting the source / drain extension region 5 and the source / drain region 7. As such an element, the impurity 51 can be, for example, silicon. Further, the impurity 51 may be an element that becomes a dopant of the same conductivity type as the source / drain extension region 5 and the source / drain region 7. For example, when the source / drain extension regions 5 and the source / drain regions 7 are P-type semiconductors, the impurity 51 can be a single boron or a cluster of boron such as octadecaborane (B ₁₈ H ₂₂ ). When the source / drain extension region 5 and the source / drain region 7 are N-type semiconductors, the impurity 51 can be phosphorus, arsenic, or a cluster thereof (P ₄ or the like). By using cluster ions, the first region 21 which is an amorphized region and the second region 22 including atomic vacancies and interstitial atoms can be easily formed.

  As another example, the impurity 51 can be carbon, oxygen, nitrogen, fluorine, or a rare gas element. As described in the first embodiment, since these elements themselves act as gettering sites for the metal elements that form the silicide layers, the metal elements that form the silicide layers 26 can be effectively gettered.

  Thereafter, heat treatment is performed to convert the first region 21 into a first recrystallized region 23 containing no defects and the second region 22 into a second recrystallized region 24 containing crystal defects (see FIG. 6 (a)). The crystal defect functions as a gettering site for the metal element constituting the silicide layer 26. In the present embodiment, the second recrystallization region 24 functions as a gettering layer.

This procedure will be described with reference to FIG.
When the impurity 51 is implanted into the source / drain region 7 (FIG. 7A), the impurity 51 collides with the substrate 1 and silicon atoms constituting the substrate 1 are blown off by the impurity 51. The impurity 51 loses kinetic energy in the process of collision and is introduced into the first region 21 and the second region 22. A large number of silicon atoms on the outermost surface of the source / drain region 7 are blown off, and most of the silicon atoms are blown off, and the first region 21 is mutated into an amorphized region. Further, in the region below the first region 21, the impurity 51 collides with the substrate 1 to generate atomic vacancies 53 and interstitial silicon 52 (FIG. 7B).

  When heat treatment is performed in this state, in the second region 22 including the impurity 51 (interstitial atoms), the interstitial silicon 52, and the atomic vacancies 53, the impurity 51 or the interstitial silicon 52 is converted into the atomic vacancies 53 by the heat treatment. Fits in. Here, since the impurities 51 which are interstitial atoms are present in excess of the atomic vacancies 53, the defects 51 ({311} defects) and the defects 58 (EOR (End) (EOR (End)) are caused by the impurities 51 which could not fit in the atomic vacancies 53. -of-Range) defect) is generated (FIG. 7C). Therefore, the second region 22 is converted into the second recrystallization region 24 including crystal defects by heat treatment.

  On the other hand, in the first region 21 that is an amorphized region, rearrangement of atoms called solid layer growth occurs from the interface with the second region 22. Solid layer growth proceeds from the interface with the second region 22 toward the surface, and the first region 21 is finally converted into a first recrystallized region 23 that does not include crystal defects.

  Note that since the {311} defect and the EOR defect are in a metastable state, when the heat treatment is continued, the atoms are desorbed and these crystal defects disappear. The detached atoms diffuse toward the surface and constitute a new crystal surface. Therefore, when the heat treatment is continued, the second recrystallized region 24 including crystal defects is also converted into a recrystallized region not including crystal defects. In the present embodiment, the heat treatment can be performed in the range where the crystal defects in the second recrystallization region 24 exist.

  As such heat treatment conditions, for example, RTA (rapid thermal annealing) is performed at a temperature of about 700 ° C. to 900 ° C. for about 1 second, or MSA (millisecond annealing) is performed at a temperature of about 1000 ° C. to 1250 ° C. It can be about 1 millisecond.

  Returning to FIG. 6, a crystal layer is formed on the first recrystallized region 23 by selective growth while doping impurities having the same conductivity type as the source / drain extension region 5 and the source / drain region 7. Thus, raised source / drain regions 25 are formed (FIG. 6B). The raised source / drain region 25 can be formed so as to have a portion raised from the main surface of the substrate 1 even after the silicide layer 26 is formed later. In the present embodiment, in particular, when impurities other than those constituting the source / drain extension region 5 and the source / drain region 7 are used as the impurity 51, or the same conductivity as the source / drain extension region 5 and the source / drain region 7. When an element other than the type element is used, by forming the raised source / drain regions 25, the silicide layer 26 can be formed well and the interface resistance can be kept low. However, as the impurity 51, for example, the same element as the element constituting the source / drain extension region 5 or the source / drain region 7 or an element serving as a dopant of the same conductivity type as the source / drain extension region 5 and the source / drain region 7 is used. In such a case, the formation of the raised source / drain regions 25 can be omitted.

  Next, a metal layer is formed on the entire surface of the substrate 1, and the silicide layer 26 is formed by reacting the metal element of the metal layer with silicon at a portion where the metal layer is in contact with silicon by heat treatment. Thereafter, the unreacted metal layer is removed (FIG. 6C). Here, the metal layer can be a nickel layer. In this case, the silicide layer 26 can be nickel silicide. In the present embodiment, the silicide layer 26 is formed so as not to contact the second recrystallization region 24.

  Thereafter, an insulating film 60 is formed on the substrate 1 so as to cover the gate. Subsequently, after forming a contact hole reaching the silicide layer 14 on the semiconductor electrode 10 in the insulating film 60, the contact 62 is filled with a conductive material, thereby forming a contact 62. With the above procedure, the semiconductor device 100 having the configuration shown in FIG. 4 is obtained.

  In the present embodiment, the silicide layer 26 and the second recrystallized region 24 including crystal defects that function as a gettering layer are formed apart from each other. Therefore, also in the present embodiment, the same effect as in the first embodiment can be obtained. Further, since the second recrystallization region 24 is formed when the silicide layer 26 is formed, the diffusion of the metal element from the silicide layer 26 or the metal layer for forming the silicide layer 26 is suppressed, and the leakage current is reduced. In addition, parasitic resistance can be reduced.

  Furthermore, since the second recrystallization region 24 is separated from the PN junction between the semiconductor electrode 10 and the substrate 1, junction leakage can be reduced.

  Further, in the present embodiment, by forming the raised source / drain region 25, the distance between the junction interface between the substrate 1 and the semiconductor electrode 10 and the second recrystallization region 24, and the semiconductor electrode 10 and the silicide layer The margin of the distance between the interface with the second recrystallized region 24 and the second recrystallized region 24 can be increased, and the degree of manufacturing freedom can be increased.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Element isolation insulating film 3 Gate insulating film 4 Gate electrode 5 Source / drain extension region 6 Side wall spacer 7 Source / drain region 10 Semiconductor electrode 11 Excavation region 12 Gettering layer 13 Raised source / drain region 14 Silicide layer 21 First region 22 Second region 23 First recrystallization region 24 Second recrystallization region 25 Raised source / drain region 26 Silicide layer 51 Impurity 52 Interstitial silicon 53 Atomic vacancy 57 Defect 58 Defect 60 Insulating film 62 Contact 100 Semiconductor device

Claims (20)

A semiconductor layer;
A semiconductor electrode formed in contact with the semiconductor layer and having a conductivity type opposite to that of the semiconductor layer;
A silicide layer formed on and in contact with the semiconductor electrode;
Inside the semiconductor electrode, a gettering layer that is formed separately from the junction between the semiconductor layer and the semiconductor electrode and the silicide layer, and getters a metal element,
A semiconductor device including: The semiconductor device according to claim 1,
The semiconductor device, wherein the semiconductor electrode is connected to a contact through the silicide layer. The semiconductor device according to claim 1 or 2,
The semiconductor device, wherein the semiconductor electrode is a source / drain electrode of a field effect transistor. The semiconductor device according to claim 1,
The semiconductor device, wherein the semiconductor electrode is connected to a charge storage memory device through the silicide layer. The semiconductor device according to claim 1,
The semiconductor device, wherein the silicide layer is a silicide containing nickel. The semiconductor device according to claim 1,
The semiconductor device, wherein the semiconductor electrode has a portion raised from a main surface of the semiconductor layer. The semiconductor device according to claim 1,
The gettering layer is a semiconductor device containing at least one of carbon, oxygen, nitrogen, fluorine, or a rare gas element. The semiconductor device according to claim 1,
The gettering layer is a semiconductor device including crystal defects. A method of manufacturing a semiconductor device including a silicide layer,
A step of forming a semiconductor electrode that is provided in contact with the semiconductor layer and includes a gettering layer for gettering a metal element at a position away from the junction with the semiconductor layer, and having a conductivity type opposite to that of the semiconductor layer;
After the step of forming the semiconductor electrode, a step of contacting the semiconductor electrode on the semiconductor electrode and forming a silicide layer at a position away from the gettering layer;
A method of manufacturing a semiconductor device including: In the manufacturing method of the semiconductor device according to claim 9,
A method of manufacturing a semiconductor device, further comprising forming a contact connected to the semiconductor electrode through the silicide layer. In the manufacturing method of the semiconductor device according to claim 9 or 10,
The method for manufacturing a semiconductor device, wherein the silicide layer is a silicide containing nickel. In the manufacturing method of the semiconductor device according to claim 9,
The semiconductor electrode includes a first impurity diffusion region and a second impurity diffusion region having a conductivity type opposite to that of the semiconductor layer,
The step of forming the semiconductor electrode includes:
Removing an upper portion of the first impurity diffusion region so as not to penetrate into the semiconductor layer in a state where a part of the first impurity diffusion region is masked;
Forming the gettering layer on the first impurity diffusion region so as not to contact the junction between the semiconductor layer and the first impurity diffusion region;
Forming a crystal layer to be the second impurity diffusion region on the gettering layer;
Including
A method of manufacturing a semiconductor device, wherein, in the step of forming the silicide layer, the silicide layer is formed on the second impurity diffusion region so as not to contact the gettering layer. In the manufacturing method of the semiconductor device according to claim 12,
A method of manufacturing a semiconductor device, wherein, in the step of forming the crystal layer, the crystal layer is formed so that the crystal layer has a portion protruding from the main surface of the semiconductor layer even after the silicide layer is formed. In the manufacturing method of the semiconductor device according to claim 12 or 13,
The step of forming the gettering layer includes
A step of ion-implanting at least one of carbon, oxygen, nitrogen, fluorine, or a rare gas element;
Performing a heat treatment so that an amorphous region does not remain on the surface of the first impurity diffusion region;
A method of manufacturing a semiconductor device including: In the manufacturing method of the semiconductor device according to claim 9,
The semiconductor electrode includes an impurity diffusion region having a conductivity type opposite to that of the semiconductor layer,
The step of forming the semiconductor electrode includes:
Impurities are ion-implanted into the impurity diffusion region in a state where a part of the impurity diffusion region is masked to form a first region which is an amorphized region on the surface of the impurity diffusion region, and below the first region. Forming a second region containing atomic vacancies and interstitial atoms so as not to contact the junction of the semiconductor layer and the impurity diffusion region;
The heat treatment converts the first region into a first recrystallized region that does not include defects, and the second region serves as the second recrystallized region that includes crystal defects as the gettering layer. Converting, and
Including
A method of manufacturing a semiconductor device, wherein, in the step of forming the silicide layer, the silicide layer is formed so as not to contact the second recrystallization region. In the manufacturing method of the semiconductor device according to claim 15,
The step of forming the semiconductor electrode includes:
After the step of converting into the first recrystallized region and the second recrystallized region, and before the step of forming the silicide layer, it becomes a part of the semiconductor electrode on the impurity diffusion region Further comprising forming a crystal layer,
A method of manufacturing a semiconductor device, wherein the silicide layer is formed in contact with the crystal layer in the step of forming the silicide layer. In the manufacturing method of the semiconductor device according to claim 15 or 16,
The method of manufacturing a semiconductor device, wherein in the step of forming the first region and the second region, the impurity to be ion-implanted is the same element as that constituting the impurity diffusion region. In the manufacturing method of the semiconductor device according to claim 15 or 16,
In the step of forming the first region and the second region, the impurity to be ion-implanted is a method for manufacturing a semiconductor device, which is an element that becomes a dopant of the same conductivity type as the impurity diffusion region. In the manufacturing method of the semiconductor device according to claim 15 or 16,
The method for manufacturing a semiconductor device, wherein in the step of forming the first region and the second region, the impurity to be ion-implanted is at least one of carbon, oxygen, nitrogen, fluorine, or a rare gas element. In the manufacturing method of the semiconductor device in any one of Claims 15-19,
In the method of forming the first region and the second region, the impurity to be ion-implanted is a method for manufacturing a semiconductor device in which cluster ions are used.

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