TWI595607B - 封裝載板及封裝載板的製造方法 - Google Patents

封裝載板及封裝載板的製造方法 Download PDF

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TWI595607B
TWI595607B TW105120846A TW105120846A TWI595607B TW I595607 B TWI595607 B TW I595607B TW 105120846 A TW105120846 A TW 105120846A TW 105120846 A TW105120846 A TW 105120846A TW I595607 B TWI595607 B TW I595607B
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flexible substrate
package carrier
build
package
opening
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TW105120846A
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TW201801255A (zh
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林永清
劉珍君
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欣興電子股份有限公司
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Priority to US15/259,011 priority patent/US10103104B2/en
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
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Description

封裝載板及封裝載板的製造方法
本發明是有關於一種封裝載板、封裝載板的製造方法及晶片封裝結構，且特別是有關於一種具有晶片容置槽的封裝載板、此封裝載板的製造方法及具有此封裝載板的晶片封裝結構。
近年來，隨著電子產品的需求朝向高功能化、訊號傳輸高速化及電路元件高密度化，半導體相關產業也日漸發展。半導體積體電路(IC)產業包含積體電路製造及積體電路封裝。積體電路製造是將積體電路製作在晶圓上。積體電路封裝則可提供結構保護、電性傳遞及良好散熱給已製作有積體電路的晶片(即晶圓於切割後的一部分)。
現行系統級封裝(System in package，SiP)及疊層封裝(Package on Package，PoP)受限於封裝面積與疊層封裝之接墊間距(pad pitch)等限制，封裝體內之晶片配置空間無法有效提升。
本發明提供一種封裝載板，可增加晶片的配置空間。
本發明提供一種封裝載板的製造方法，其所製造出的封裝載板可增加晶片的配置空間。
本發明提供一種晶片封裝結構，其封裝載板可增加晶片的配置空間。
本發明的封裝載板包括一可撓性基板、一第一增層結構及一第二增層結構。可撓性基板具有相對的一第一表面及一第二表面，且具有連接於第一表面與第二表面之間的一第一開口。第一增層結構配置於第一表面且覆蓋第一開口。第二增層結構配置於第二表面且具有一第二開口，第一開口與第二開口相連接而共同構成一晶片容置槽。
在本發明的一實施例中，上述的封裝載板更包括一圖案化阻障層，其中圖案化阻障層配置於第一表面且延伸至晶片容置槽的一底面。
在本發明的一實施例中，上述的圖案化阻障層沿第一開口的內緣延伸。
在本發明的一實施例中，上述的第二開口的輪廓吻合於第一開口的輪廓。
在本發明的一實施例中，上述的封裝載板更包括一圖案化導電層，其中圖案化導電層配置於第一表面且延伸至晶片容置槽的一底面。
在本發明的一實施例中，上述的封裝載板與另一封裝載板共用可撓性基板，可撓性基板在兩封裝載板之間的區段適於彎折。
本發明的封裝載板的製造方法包括以下步驟。提供一可撓性基板，其中可撓性基板具有相對的一第一表面及一第二表面。形成一第一增層結構於第一表面。形成一第二增層結構於第二表面。裁切可撓性基板及第二增層結構，以使可撓性基板的一第一待移除區塊分離於可撓性基板的其他區塊，且使第二增層結構的一第二待移除區塊分離於第二增層結構的其他區塊，其中第一待移除區塊連接於第二待移除區塊。將第一待移除區塊分離於第一增層結構，以同時移除第一待移除區塊及第二待移除區塊而形成一晶片容置槽。
在本發明的一實施例中，上述的封裝載板的製造方法更包括：在形成第一增層結構於第一表面之前，形成一圖案化阻障層於第一表面，其中圖案化阻障層延伸至第一待移除區塊。
在本發明的一實施例中，上述的形成圖案化阻障層於第一表面的步驟包括：使圖案化阻障層沿第一待移除區塊的邊緣延伸。
在本發明的一實施例中，上述的裁切可撓性基板及第二增層結構的步驟包括：藉由雷射製程同時裁切可撓性基板及第二增層結構。
在本發明的一實施例中，上述的封裝載板的製造方法更包括：在形成第一增層結構於第一表面之前，形成一圖案化導電層於第一表面，其中圖案化導電層延伸至第一待移除區塊。
在本發明的一實施例中，上述的封裝載板的製造方法更包括使封裝載板與另一封裝載板共用可撓性基板，其中可撓性基板在兩封裝載板之間的區段適於彎折。
基於上述，本發明的封裝載板藉其可撓性基板的第一開口與第二增層結構的第二開口共同構成晶片容置槽，使晶片能夠埋設於晶片容置槽內，藉以增加晶片的配置空間。此外，由於封裝載板以可撓性基板作為心層，故在製造封裝載板的過程中，可利用可撓性基板的部分區塊作為離形層來移除部分可撓性基板及部分第二增層結構，從而形成所述晶片容置槽，使封裝載板的製程較為簡便。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1D是本發明一實施例的封裝載板的製造方法流程圖。首先，請參考圖1A，提供一可撓性基板110，可撓性基板110例如是聚亞醯胺(Polyimide，PI)軟板且具有相對的一第一表面110a及一第二表面110b。此外，更形成一圖案化阻障層112及一圖案化導電層114於可撓性基板110的第一表面110a，其中圖案化阻障層112及圖案化導電層114延伸至可撓性基板110的一第一待移除區塊R1，且圖案化阻障層112沿第一待移除區塊R1的邊緣延伸。圖案化阻障層112及圖案化導電層114例如是藉由對可撓性基板110上的一金屬層(如銅層)進行圖案化而同時被形成。
接著，請參考圖1B，形成一第一增層結構120於可撓性基板110的第一表面110a，並形成一第二增層結構130於可撓性基板110的第二表面110b。第一增層結構120例如包含介電層122、配置於介電層122的線路層124、連接線路層124的導電通孔126、配置於介電層122表面並覆蓋線路層124的防銲層128。第二增層結構130例如包含介電層132、配置於介電層132的線路層134、連接線路層134的導電通孔136、配置於介電層132表面並覆蓋線路層134的防銲層138。
請參考圖1C，裁切可撓性基板110及第二增層結構130，以使可撓性基板110的第一待移除區塊R1分離於可撓性基板110的其他區塊，且使第二增層結構130的第二待移除區塊R2分離於第二增層結構130的其他區塊，所述第一待移除區塊R1連接於所述第二待移除區塊R2。在本實施例中，例如是藉由雷射製程同時裁切可撓性基板110及第二增層結構130，其中延伸至第一待移除區塊R1的圖案化阻障層112可避免雷射非預期地裁切到第一增層結構120。
接著，將可撓性基板110的第一待移除區塊R1分離於第一增層結構120，以同時移除第一待移除區塊R1及第二待移除區塊R2而如圖1D所示形成一晶片容置槽C，從而完成封裝載板100之製作。詳細而言，在上述製程中，係藉可撓性基板110易於被剝離的特性，而使第一待移除區塊R1能夠作為離形層而順利地分離於第一增層結構120。
圖2是圖1D的封裝載板的俯視圖，圖1D所示剖面對應於圖2中的I-I線。為使圖式較為清楚，圖1D中的圖案化導電層114未在圖2示出。請參考圖1D及圖2，藉由上述製程所製作出的封裝載板100包括可撓性基板110、第一增層結構120及第二增層結構130。可撓性基板110具有相對的第一表面110a及第二表面110b，且具有連接於第一表面110a與第二表面110b之間的一第一開口110c，此第一開口110c係上述製程中移除第一待移除區塊R1所形成。第一增層結構120配置於可撓性基板110的第一表面110a且覆蓋第一開口110c。第二增層結構130配置於可撓性基板110的第二表面110b且具有一第二開口130a，此第二開口130a係上述製程中移除第二待移除區塊R2所形成，第二開口130a的輪廓例如吻合於第一開口110c的輪廓。可撓性基板110的第一開口110c與第二增層結構130的第二開口130a相連接而共同構成晶片容置槽C。封裝載板100更包括圖案化阻障層112及圖案化導電層114，圖案化阻障層112及圖案化導電層114配置於可撓性基板110的第一表面110a且延伸至晶片容置槽C的底面，且圖案化阻障層112沿第一開口110c的內緣延伸。
本實施例的封裝載板100如上述般藉其可撓性基板110的第一開口110c與第二增層結構130的第二開口130a共同構成晶片容置槽C，使晶片能夠埋設於晶片容置槽C內，藉以增加晶片的配置空間。此外，由於封裝載板100以可撓性基板110作為心層，故在製造封裝載板100的過程中，可利用可撓性基板110的部分區塊(即所述第一待移除區塊R1)作為離形層來移除部分可撓性基板110及部分第二增層結構130，從而形成所述晶片容置槽C，使封裝載板100的製程較為簡便。以下具體說明由所述封裝載板與晶片構成的晶片封裝結構。
圖3是本發明一實施例的晶片封裝結構的示意圖。在圖3的晶片封裝結構50中，第一封裝載板200、可撓性基板210、第一表面210a、第二表面210b、第一開口210c、圖案化阻障層212、圖案化導電層214、第一增層結構220、介電層222、線路層224、導電通孔226、防銲層228、第二增層結構230、介電層232、線路層234、導電通孔236、防銲層238、第二開口230a、晶片容置槽C’的配置與作用方式相同於圖1D的第一封裝載板100、可撓性基板110、第一表面110a、第二表面110b、第一開口110c、圖案化阻障層112、圖案化導電層114、第一增層結構120、介電層122、線路層124、導電通孔126、防銲層128、第二增層結構130、介電層132、線路層134、導電通孔136、防銲層138、第二開口130a、晶片容置槽C’的配置與作用方式，於此不再贅述。
晶片封裝結構50更包括一第一晶片52、一第二封裝載板54、一第二晶片56及一封裝膠體58。第一晶片52配置於晶片容置槽C’內，第二封裝載板54具有相對的一第三表面54a及一第四表面54b，第二封裝載54板藉由第三表面54a而疊設於第二增層結構230及第一晶片52，第二晶片56則配置於第四表面54b。第二封裝載板54例如包含介電層54c、配置於介電層54c的線路層54d、連接線路層54d的導電通孔54e、配置於介電層54c表面並覆蓋線路層54d的防銲層54f。第一晶片52及第二封裝載板54例如是藉由銲球(solder ball)52a而連接於第一封裝載板200，第二晶片56可藉由銲線56a而連接於線路層54d。封裝膠體58用以覆蓋第一晶片52、第二晶片56、至少部分第一封裝載板200及至少部分第二封裝載板54。所述第一晶片52及第二晶片54可為應用處理器(application processor，AP)晶片、記憶體晶片或其他適當種類的主動、被動元件，本發明不對其種類加以限制。
圖4是本發明另一實施例的晶片封裝結構的示意圖。圖4的晶片封裝結構60及晶片封裝結構70及其具體結構類似圖3的晶片封裝結構50，於此不再贅述。圖4所示實施例與前述實施例的不同處在於，晶片封裝結構60及其封裝載板與晶片封裝結構70及其封裝載板共用可撓性基板310，使晶片封裝結構60與晶片封裝結構70能夠透過可撓性基板310而彼此電性連接。此外，可撓性基板310在兩晶片封裝結構60、70之間的區段適於彎折，使兩晶片封裝結構60、70能夠因應不同配置環境而配置為具有不同相對位置。在其他實施例中，可撓性基板可被更多數量的晶片封裝結構共用，本發明不對此加以限制。
綜上所述，本發明的封裝載板藉其可撓性基板的第一開口與第二增層結構的第二開口共同構成晶片容置槽，使晶片能夠埋設於晶片容置槽內，藉以增加晶片的配置空間。此外，由於封裝載板以可撓性基板作為心層，故在製造封裝載板的過程中，可利用可撓性基板的部分區塊作為離形層來移除部分可撓性基板及部分第二增層結構，從而形成所述晶片容置槽，使封裝載板的製程較為簡便。另外，複數晶片封裝結構可共用單一可撓性基板，所述可撓性基板在兩晶片封裝結構之間的區段適於彎折，使複數晶片封裝結構能夠因應不同配置環境而配置為具有不同相對位置，以增加晶片封裝結構在配置上的自由性。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
50、60、70‧‧‧晶片封裝結構
52‧‧‧第一晶片
52a‧‧‧銲球
54‧‧‧第二封裝載板
54a‧‧‧第三表面
54b‧‧‧第四表面
54c、122、132、222、232‧‧‧介電層
54d、124、134、224、234‧‧‧線路層
54e、126、136、226、236‧‧‧導電通孔
54f、128、138、228、238‧‧‧防銲層
56‧‧‧第二晶片
56a‧‧‧銲線
58‧‧‧封裝膠體
100‧‧‧封裝載板
110、210、310‧‧‧可撓性基板
110a、210a‧‧‧第一表面
110b、210b‧‧‧第二表面
110c、210c‧‧‧第一開口
112、212‧‧‧圖案化阻障層
114、214‧‧‧圖案化導電層
120、220‧‧‧第一增層結構
130、230‧‧‧第二增層結構
130a、230a‧‧‧第二開口
200‧‧‧第一封裝載板
C、C’‧‧‧晶片容置槽
R1‧‧‧第一待移除區塊
R2‧‧‧第二待移除區塊
圖1A至圖1D是本發明一實施例的封裝載板的製造方法流程圖。 圖2是圖1D的封裝載板的俯視圖。 圖3是本發明一實施例的晶片封裝結構的示意圖。 圖4是本發明另一實施例的晶片封裝結構的示意圖。
100‧‧‧封裝載板
110‧‧‧可撓性基板
110a‧‧‧第一表面
110b‧‧‧第二表面
110c‧‧‧第一開口
112‧‧‧圖案化阻障層
114‧‧‧圖案化導電層
120‧‧‧第一增層結構
122、132‧‧‧介電層
124、134‧‧‧線路層
126、136‧‧‧導電通孔
128、138‧‧‧防銲層
130‧‧‧第二增層結構
130a‧‧‧第二開口
C‧‧‧晶片容置槽

Claims (10)

  1. 一種封裝載板，包括：一可撓性基板，具有相對的一第一表面及一第二表面，且具有連接於該第一表面與該第二表面之間的一第一開口；一第一增層結構，配置於該第一表面且覆蓋該第一開口；一第二增層結構，配置於該第二表面且具有一第二開口，其中該第一開口與該第二開口相連接而共同構成一晶片容置槽；以及一圖案化阻障層，配置於該第一表面且延伸至該晶片容置槽的一底面。
  2. 如申請專利範圍第1項所述的封裝載板，其中該圖案化阻障層沿該第一開口的內緣延伸。
  3. 如申請專利範圍第1項所述的封裝載板，其中該第二開口的輪廓吻合於該第一開口的輪廓。
  4. 如申請專利範圍第1項所述的封裝載板，更包括一圖案化導電層，其中該圖案化導電層配置於該第一表面且延伸至該晶片容置槽的該底面。
  5. 如申請專利範圍第1項所述的封裝載板，其中該封裝載板與另一該封裝載板共用該可撓性基板，該可撓性基板在該兩封裝載板之間的區段適於彎折。
  6. 一種封裝載板的製造方法，包括： 提供一可撓性基板，其中該可撓性基板具有相對的一第一表面及一第二表面；形成一第一增層結構於該第一表面；形成一第二增層結構於該第二表面；裁切該可撓性基板及該第二增層結構，以使該可撓性基板的一第一待移除區塊分離於該可撓性基板的其他區塊，且使該第二增層結構的一第二待移除區塊分離於該第二增層結構的其他區塊，其中該第一待移除區塊連接於該第二待移除區塊；將該第一待移除區塊分離於該第一增層結構，以同時移除該第一待移除區塊及該第二待移除區塊而形成一晶片容置槽；以及在形成該第一增層結構於該第一表面之前，形成一圖案化阻障層於該第一表面，其中該圖案化阻障層延伸至該第一待移除區塊。
  7. 如申請專利範圍第6項所述的封裝載板的製造方法，其中形成該圖案化阻障層於該第一表面的步驟包括：使該圖案化阻障層沿該第一待移除區塊的邊緣延伸。
  8. 如申請專利範圍第6項所述的封裝載板的製造方法，其中裁切該可撓性基板及該第二增層結構的步驟包括：藉由雷射製程同時裁切該可撓性基板及該第二增層結構。
  9. 如申請專利範圍第6項所述的封裝載板的製造方法，更包括： 在形成該第一增層結構於該第一表面之前，形成一圖案化導電層於該第一表面，其中該圖案化導電層延伸至該第一待移除區塊。
  10. 如申請專利範圍第6項所述的封裝載板的製造方法，更包括使該封裝載板與另一該封裝載板共用該可撓性基板，其中該可撓性基板在該兩封裝載板之間的區段適於彎折。
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