TWI594432B - Oxide semiconductor element, method for manufacturing oxide semiconductor element, display device and image sensor - Google Patents

Oxide semiconductor element, method for manufacturing oxide semiconductor element, display device and image sensor Download PDF

Info

Publication number
TWI594432B
TWI594432B TW102142372A TW102142372A TWI594432B TW I594432 B TWI594432 B TW I594432B TW 102142372 A TW102142372 A TW 102142372A TW 102142372 A TW102142372 A TW 102142372A TW I594432 B TWI594432 B TW I594432B
Authority
TW
Taiwan
Prior art keywords
layer
oxide semiconductor
electrode
metal
metal layer
Prior art date
Application number
TW102142372A
Other languages
Chinese (zh)
Other versions
TW201428974A (en
Inventor
望月文彦
五十田智丈
田中淳
鈴木真之
Original Assignee
富士軟片股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士軟片股份有限公司 filed Critical 富士軟片股份有限公司
Publication of TW201428974A publication Critical patent/TW201428974A/en
Application granted granted Critical
Publication of TWI594432B publication Critical patent/TWI594432B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

Description

氧化物半導體元件、氧化物半導體元件的製造方法、顯示裝置及影像感測器 Oxide semiconductor device, method of manufacturing oxide semiconductor device, display device, and image sensor

本發明是有關於氧化物半導體元件、氧化物半導體元件的製造方法、顯示裝置及影像感測器。 The present invention relates to an oxide semiconductor device, a method of manufacturing an oxide semiconductor device, a display device, and an image sensor.

近年來,將In-Ga-Zn-O系氧化物半導體薄膜用於氧化物半導體層(通道層(channel layer))的氧化物半導體元件、尤其是薄膜電晶體(Thin Film Transistor:TFT)的研究開發盛行。氧化物半導體薄膜可進行低溫成膜,且表現出較非晶矽(amorphous silicon)高的遷移率,此外對可見光為透明,因此可在塑膠板或薄膜等基板上形成可撓性薄膜電晶體。 In recent years, an In-Ga-Zn-O-based oxide semiconductor thin film has been used for an oxide semiconductor element (channel layer) of an oxide semiconductor element, particularly a thin film transistor (TFT). Development is prevalent. The oxide semiconductor thin film can be formed at a low temperature, exhibits a higher mobility than amorphous silicon, and is transparent to visible light, so that a flexible thin film transistor can be formed on a substrate such as a plastic plate or a film.

然而,在適於實用化而在液晶顯示器(Liquid Crystal Display,LCD)或有機電致發光(electroluminescence,EL)顯示器等的驅動電路上使用上述薄膜電晶體的情形時,薄膜電晶體驅動時的工作不穩定性(ΔVth:臨限值偏移)或光照射時的工作不穩定性成為問題。 However, when it is suitable for practical use and the above-mentioned thin film transistor is used on a driving circuit of a liquid crystal display (LCD) or an organic electroluminescence (EL) display, etc., the operation of the thin film transistor is driven. The instability (ΔVth: threshold shift) or the operational instability at the time of light irradiation becomes a problem.

薄膜電晶體驅動時的工作不穩定性起因於如下,即由於In-Ga-Zn-O系氧化物對水分或氧、污染等的耐受性低,因此若以In-Ga-Zn-O系氧化物為主體的氧化物半導體層露出於大氣中則該氧化物會隨著時間劣化。 The operational instability during driving of a thin film transistor is caused by the fact that the In-Ga-Zn-O-based oxide is low in resistance to moisture, oxygen, pollution, etc., so that the In-Ga-Zn-O system is used. When the oxide-based oxide semiconductor layer is exposed to the atmosphere, the oxide deteriorates with time.

又,光照射時的工作不穩定性起因於如下,即液晶顯示器的背光或有機電致發光的藍色發光層具有λ=450nm左右的發光峰值,發光光譜的底部延續至420nm,被該等光照射的In-Ga-Zn-O系等包含選自In、Zn、Ga及Sn中的至少1種的氧化物半導體層,通常相對於可見光短波長區域的光(波長400nm以上且450nm以下的光)而工作不穩定。 Further, the operational instability at the time of light irradiation is caused by the backlight of the liquid crystal display or the blue light-emitting layer of the organic electroluminescence having an emission peak of about λ = 450 nm, and the bottom of the emission spectrum is continued to 420 nm. The in-Ga-Zn-O system to be irradiated includes at least one oxide semiconductor layer selected from the group consisting of In, Zn, Ga, and Sn, and generally has light in a short-wavelength region with respect to visible light (light having a wavelength of 400 nm or more and 450 nm or less). ) and the work is unstable.

由此,日本專利第4982619號公報中揭示有如下內容,即在以In-Ga-Zn-O系氧化物為主體的氧化物半導體層的露出面上形成保護層來保護氧化物半導體層免受水分等侵害,藉此謀求改善薄膜電晶體驅動時的工作不穩定性。又,揭示有藉由在該保護膜形成時進行氧擴散控制,而謀求改善光照射時的工作不穩定性。 In the above-mentioned Japanese Patent No. 4982619, a protective layer is formed on the exposed surface of an oxide semiconductor layer mainly composed of an In—Ga—Zn—O-based oxide to protect the oxide semiconductor layer from the oxide semiconductor layer. Invasion of moisture or the like, thereby improving the operational instability during driving of the thin film transistor. Further, it has been revealed that the oxygen diffusion control at the time of formation of the protective film improves the operational instability at the time of light irradiation.

又,國際公開第2009/075281號中揭示有如下薄膜電晶體,其在保護以In-Ga-Zn-O系氧化物為主體的氧化物半導體層的保護層上設置有遮光膜,該遮光膜由在波長500nm以下的區域具有大的吸收或反射的樹脂材料或金屬材料構成。 Further, Japanese Laid-Open Patent Publication No. 2009/075281 discloses a thin film transistor in which a light shielding film is provided on a protective layer for protecting an oxide semiconductor layer mainly composed of an In—Ga—Zn—O based oxide. It is composed of a resin material or a metal material having a large absorption or reflection in a region having a wavelength of 500 nm or less.

然而,僅利用日本專利第4982619號公報的保護層無法相對於水分或氧、污染等充分保護氧化物半導體層。 However, the protective layer of Japanese Patent No. 4992619 cannot sufficiently protect the oxide semiconductor layer with respect to moisture, oxygen, contamination, or the like.

又,在國際公開第2009/075281號中僅在保護層上設置由樹脂材料構成的遮光膜,無法相對於水分或氧等充分保護氧化物半導體層。又,即便在保護層上僅設置由金屬材料構成的遮光膜,亦會因存在遮光膜而相應地花費多餘的製造成本。 In addition, in the international publication No. 2009/075281, only a light-shielding film made of a resin material is provided on the protective layer, and the oxide semiconductor layer cannot be sufficiently protected from moisture, oxygen, or the like. Further, even if only a light-shielding film made of a metal material is provided on the protective layer, an unnecessary manufacturing cost is required due to the presence of the light-shielding film.

本發明是鑒於上述情況而完成的,其目的在於提供一種確保光照射時的工作穩定性,並且抑制製造成本且提高氧化物半導體層的保護功能的氧化物半導體元件、氧化物半導體元件的製造方法、顯示裝置及影像感測器。 The present invention has been made in view of the above circumstances, and an object of the invention is to provide an oxide semiconductor device or a method for manufacturing an oxide semiconductor device which can ensure operational stability at the time of light irradiation, suppress manufacturing cost, and improve a protective function of an oxide semiconductor layer. , display device and image sensor.

本發明的上述課題藉由下述方法解決。 The above problems of the present invention are solved by the following methods.

<1>一種氧化物半導體元件,包括:電極,由金屬材料構成;氧化物半導體層,包含選自In、Zn、Ga及Sn中的至少1種;以及保護層,積層在上述氧化物半導體層上,且上述保護層包含無機絕緣層、及由與上述電極相同的金屬材料構成的金屬層。 <1> An oxide semiconductor device comprising: an electrode comprising: a metal material; an oxide semiconductor layer comprising at least one selected from the group consisting of In, Zn, Ga, and Sn; and a protective layer laminated on the oxide semiconductor layer Further, the protective layer includes an inorganic insulating layer and a metal layer made of the same metal material as the electrode.

<2>如<1>記載的氧化物半導體元件,其中上述金屬層的總厚度為50nm以上。 <2> The oxide semiconductor device according to <1>, wherein the total thickness of the metal layer is 50 nm or more.

<3>如<1>或<2>記載的氧化物半導體元件,其中上述電極為夾持上述保護層而分別積層在上述氧化物半導體層且可經由上述氧化物半導體層而相互導通的源極電極及汲極電極,在上述氧化物半導體層的配置上述保護層的側的相反側包含隔著閘極絕緣層而配置的閘極電極,上述金屬層的至少一部分由與上述源極電極及上述汲極電極相同的金屬材料構成,且配置在上述保護層的頂部。 The oxide semiconductor device according to the above aspect, wherein the electrode is a source in which the protective layer is sandwiched between the oxide semiconductor layers and can be electrically connected to each other via the oxide semiconductor layer. The electrode and the drain electrode include a gate electrode disposed via a gate insulating layer on a side opposite to a side of the oxide semiconductor layer on which the protective layer is disposed, and at least a portion of the metal layer is formed by the source electrode and the source electrode The drain electrode is made of the same metal material and is disposed on the top of the above protective layer.

<4>如上述<1>~上述<3>中任一項記載的氧化物半導體元件,其中上述金屬層為多層。 The oxide semiconductor device according to any one of the above aspects, wherein the metal layer is a plurality of layers.

<5>如上述<4>記載的氧化物半導體元件,其中上述為多層的金屬層包括:耗損金屬(sacrificial metal)層,配置在上述保護層的頂部;及反射金屬層,配置在上述無機絕緣層的內部,對波長400nm以上且450nm以下的光的反射率較上述耗損金屬層高。 The oxide semiconductor device according to the above <4>, wherein the plurality of metal layers include a sacrificial metal layer disposed on top of the protective layer, and a reflective metal layer disposed on the inorganic insulating layer The inside of the layer has a higher reflectance for light having a wavelength of 400 nm or more and 450 nm or less than the above-mentioned worn metal layer.

<6>如上述<3>記載的氧化物半導體元件,其中上述金屬層由與上述閘極電極相同的金屬材料構成。 The oxide semiconductor device according to the above <3>, wherein the metal layer is made of the same metal material as the gate electrode.

<7>如上述<1>~上述<6>中任一項記載的氧化物半導體元件,其中上述無機絕緣層包含上述金屬層的金屬材料。 The oxide semiconductor device according to any one of the above aspects, wherein the inorganic insulating layer contains a metal material of the metal layer.

<8>一種氧化物半導體元件的製造方法,包括:形成氧化物半導體層的步驟,上述氧化物半導體層包含選自In、Zn、Ga及Sn中的至少1種;形成電極的步驟,上述電極由金屬材料構成;以及形成保護層的步驟,上述保護層積層在上述氧化物半導體層上,且上述保護層包含無機絕緣層、及由與上述電極相同的金屬材料構成的金屬層。 <8> A method of producing an oxide semiconductor device, comprising: forming an oxide semiconductor layer, wherein the oxide semiconductor layer comprises at least one selected from the group consisting of In, Zn, Ga, and Sn; and the step of forming an electrode, the electrode And a step of forming a protective layer, wherein the protective layer is laminated on the oxide semiconductor layer, and the protective layer comprises an inorganic insulating layer and a metal layer made of the same metal material as the electrode.

<9>如<8>記載的氧化物半導體元件的製造方法,其中形成上述電極的步驟包括:在上述無機絕緣層及氧化物半導體層上形成金屬導電膜的步驟;以及將上述金屬導電膜圖案化而形成源極電極及汲極電極的步驟;並且在形成上述保護層的步驟中的形成上述金屬層的步驟中,在形成上述電極的步驟中,在將上 述金屬導電膜圖案化時形成上述源極電極及上述汲極電極,並且在上述無機絕緣層殘留上述金屬導電膜來形成上述金屬層。 The method for producing an oxide semiconductor device according to the above aspect, wherein the step of forming the electrode includes: forming a metal conductive film on the inorganic insulating layer and the oxide semiconductor layer; and patterning the metal conductive film a step of forming a source electrode and a drain electrode; and in the step of forming the metal layer in the step of forming the protective layer, in the step of forming the electrode, When the metal conductive film is patterned, the source electrode and the drain electrode are formed, and the metal conductive film remains in the inorganic insulating layer to form the metal layer.

<10>一種顯示裝置,包括如上述<1>~上述<7>中任一項記載的氧化物半導體元件。 The display device of any one of <1> to <7> above.

<11>一種影像感測器,包括如上述<1>~上述<7>中任一項記載的氧化物半導體元件。 The oxide semiconductor device according to any one of the above-mentioned <7>, wherein the oxide semiconductor device according to any one of the above <7>.

根據本發明,可確保光照射時的工作穩定性,並且抑制製造成本且提高氧化物半導體層的保護功能。 According to the present invention, it is possible to ensure the operational stability at the time of light irradiation, and to suppress the manufacturing cost and improve the protective function of the oxide semiconductor layer.

10、30、40‧‧‧薄膜電晶體 10, 30, 40‧‧‧ film transistor

10a‧‧‧驅動用薄膜電晶體 10a‧‧‧Drive film transistor

10b‧‧‧開關用薄膜電晶體 10b‧‧‧Transistor film transistor

12‧‧‧基板 12‧‧‧Substrate

14‧‧‧閘極電極 14‧‧‧ gate electrode

14A‧‧‧導電膜 14A‧‧‧Electrical film

16‧‧‧閘極絕緣層 16‧‧‧ gate insulation

16A、26A、34A、34B、210‧‧‧絕緣膜 16A, 26A, 34A, 34B, 210‧‧‧ insulating film

18‧‧‧氧化物半導體層 18‧‧‧Oxide semiconductor layer

18A‧‧‧氧化物半導體膜 18A‧‧‧Oxide semiconductor film

20‧‧‧源極電極 20‧‧‧Source electrode

20A、36C‧‧‧金屬導電膜 20A, 36C‧‧‧Metal conductive film

22‧‧‧汲極電極 22‧‧‧汲electrode

24、32、42‧‧‧保護層 24, 32, 42‧‧ ‧ protective layer

26、34、44‧‧‧無機絕緣層 26, 34, 44‧‧‧Inorganic insulation

28、36、46‧‧‧金屬層 28, 36, 46‧‧‧ metal layers

36A‧‧‧反射金屬層 36A‧‧‧reflective metal layer

36B‧‧‧耗損金屬層 36B‧‧‧Worn metal layer

100‧‧‧液晶顯示裝置 100‧‧‧Liquid crystal display device

102‧‧‧鈍化層 102‧‧‧ Passivation layer

104‧‧‧畫素下部電極 104‧‧‧ pixel lower electrode

106‧‧‧對向上部電極 106‧‧‧for the upper electrode

108‧‧‧液晶層 108‧‧‧Liquid layer

110‧‧‧紅綠藍彩色濾光片 110‧‧‧Red, Green and Blue Color Filters

112、220‧‧‧閘極配線 112, 220‧‧‧ gate wiring

112a、112b‧‧‧偏光板 112a, 112b‧‧‧ polarizing plate

114、222‧‧‧資料配線 114, 222‧‧‧ data wiring

116‧‧‧接觸孔 116‧‧‧Contact hole

118‧‧‧電容器 118‧‧‧ capacitor

200‧‧‧有機電致發光顯示裝置 200‧‧‧Organic electroluminescent display device

202‧‧‧基板絕緣層 202‧‧‧Substrate insulation

204‧‧‧彩色濾光片層 204‧‧‧Color filter layer

206‧‧‧畫素電極(陽極) 206‧‧‧ pixel electrodes (anode)

208‧‧‧連接電極 208‧‧‧Connecting electrode

212‧‧‧有機層 212‧‧‧Organic layer

214‧‧‧陰極 214‧‧‧ cathode

224‧‧‧驅動配線 224‧‧‧Drive wiring

226‧‧‧電容器 226‧‧‧ capacitor

圖1是表示本發明的實施方式的薄膜電晶體、即底部閘極構造且頂部接觸型的薄膜電晶體的一例的示意圖。 1 is a schematic view showing an example of a thin film transistor according to an embodiment of the present invention, that is, a bottom gate structure and a top contact type thin film transistor.

圖2是表示本發明的實施方式的薄膜電晶體、即底部閘極構造且頂部接觸型的薄膜電晶體的另一例的示意圖。 2 is a schematic view showing another example of a thin film transistor of the embodiment of the present invention, that is, a bottom gate structure and a top contact type thin film transistor.

圖3是表示本發明的實施方式的薄膜電晶體、即底部閘極構造且頂部接觸型的薄膜電晶體的又一例的示意圖。 3 is a schematic view showing still another example of a thin film transistor according to an embodiment of the present invention, that is, a bottom gate structure and a top contact type thin film transistor.

圖4(A)~圖4(F)是圖1所示的薄膜電晶體的一連串的製造步驟圖。 4(A) to 4(F) are diagrams showing a series of manufacturing steps of the thin film transistor shown in Fig. 1.

圖5(A)~圖5(C)是繼圖4(F)之後的薄膜電晶體的一連串的製造步驟圖。 5(A) to 5(C) are diagrams showing a series of manufacturing steps of the thin film transistor subsequent to FIG. 4(F).

圖6(A)~圖6(F)是圖2所示的薄膜電晶體的一連串的製 造步驟圖。 6(A) to 6(F) are a series of thin film transistors shown in FIG. Make a step map.

圖7(A)~圖7(E)是繼圖6(F)之後的薄膜電晶體的一連串的製造步驟圖。 7(A) to 7(E) are diagrams showing a series of manufacturing steps of the thin film transistor subsequent to FIG. 6(F).

圖8是本發明的光電裝置的一實施方式的液晶顯示裝置的一部分的概略剖面圖。 Fig. 8 is a schematic cross-sectional view showing a part of a liquid crystal display device according to an embodiment of the photovoltaic device of the present invention.

圖9是圖8所示的液晶顯示裝置的電氣佈線的概略構成圖。 Fig. 9 is a schematic configuration diagram of electrical wiring of the liquid crystal display device shown in Fig. 8;

圖10是本發明的光電裝置的一實施方式的主動矩陣方式的有機電致發光顯示裝置的一部分的概略剖面圖。 Fig. 10 is a schematic cross-sectional view showing a part of an active matrix type organic electroluminescence display device according to an embodiment of the photovoltaic device of the present invention.

圖11是圖10所示的有機電致發光顯示裝置的電氣佈線的概略構成圖。 Fig. 11 is a schematic configuration diagram of electrical wiring of the organic electroluminescence display device shown in Fig. 10;

圖12是以波長為橫軸、且以△Vth為縱軸來繪製實施例1、實施例2及比較例1的每個波長下的△Vth的計算結果的曲線圖。 Fig. 12 is a graph showing the calculation results of ΔVth at each wavelength of Example 1, Example 2, and Comparative Example 1 with the wavelength on the horizontal axis and ΔVth as the vertical axis.

以下,參照隨附圖式對本發明的實施方式的氧化物半導體元件及氧化物半導體元件的製造方法進行具體說明。再者,圖中,對同一或具有對應的功能的構件(構成要素)附上相同符號並適當省略說明。又,以下說明的情形中所使用的「上」及「下」的用語是方便起見而使用的用語,不應限制為方向。 Hereinafter, an oxide semiconductor device and a method of manufacturing an oxide semiconductor device according to embodiments of the present invention will be specifically described with reference to the accompanying drawings. In the drawings, members (components) having the same or corresponding functions are denoted by the same reference numerals, and their description will be appropriately omitted. In addition, the terms "upper" and "lower" used in the following description are terms used for convenience, and should not be limited to the direction.

1.氧化物半導體元件:薄膜電晶體的概略構成 1. Oxide semiconductor device: schematic structure of thin film transistor

本發明的實施方式的氧化物半導體元件為薄膜電晶體(TFT)或光電二極體(photo diode)等。以下,列舉薄膜電晶體作為氧化物半導體元件的一例來進行說明。 The oxide semiconductor device according to the embodiment of the present invention is a thin film transistor (TFT), a photo diode, or the like. Hereinafter, a thin film transistor will be described as an example of an oxide semiconductor device.

本實施方式的薄膜電晶體為主動(active)元件,至少包括閘極電極、閘極絕緣層、氧化物半導體層、源極電極及汲極電極,且具有如下功能,即對閘極電極施加電壓而控制流過氧化物半導體層的電流,從而切換(switching)源極電極與汲極電極間的電流。 The thin film transistor of the present embodiment is an active element including at least a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode, and a drain electrode, and has a function of applying a voltage to the gate electrode The current flowing through the peroxide semiconductor layer is controlled to switch the current between the source electrode and the drain electrode.

作為薄膜電晶體的元件構造,存在基於閘極電極的位置的所謂的逆交錯(inverse stagger)構造(亦稱作底部閘極型(bottom gate type))及交錯構造(亦稱作頂部閘極型(top gate type)),但本實施方式中使用逆交錯構造。 As an element structure of a thin film transistor, there is a so-called inverse stagger structure (also referred to as a bottom gate type) and a staggered structure (also referred to as a top gate type) based on the position of the gate electrode. (top gate type)), but an inverse staggered structure is used in the present embodiment.

又,基於氧化物半導體層與源極電極及汲極電極(適當稱作「源極-汲極電極」)的接觸部分,亦可為所謂的頂部接觸型(top contact type)、底部接觸型(bottom contact type)中的任一態樣。 Further, the contact portion between the oxide semiconductor layer and the source electrode and the drain electrode (referred to as "source-drain electrode" as appropriate) may be a so-called top contact type or bottom contact type ( Bottom contact type).

再者,頂部閘極型是指如下形態,即在將形成薄膜電晶體的基板設為最下層時,在閘極絕緣層的上側配置閘極電極,且在閘極絕緣層的下側形成氧化物半導體層,底部閘極型是指如下形態,即在閘極絕緣層的下側配置閘極電極,且在閘極絕緣層的上側形成有氧化物半導體層。又,底部接觸型是指如下形態,即源極-汲極電極較氧化物半導體層更早地形成而使氧化物半導體層的下表面接觸於源極-汲極電極,頂部接觸型是指如下形態,即氧化物半導體層較源極-汲極電極更早地形成而使氧化物半導體層的上表面接觸於源極-汲極電極。 In addition, the top gate type refers to a form in which a gate electrode is disposed on the upper side of the gate insulating layer and an oxidation is formed on the lower side of the gate insulating layer when the substrate on which the thin film transistor is formed is the lowermost layer. The material semiconductor layer and the bottom gate type are those in which a gate electrode is disposed on the lower side of the gate insulating layer and an oxide semiconductor layer is formed on the upper side of the gate insulating layer. Further, the bottom contact type refers to a form in which the source-drain electrode is formed earlier than the oxide semiconductor layer and the lower surface of the oxide semiconductor layer is in contact with the source-drain electrode, and the top contact type is as follows The morphology, that is, the oxide semiconductor layer is formed earlier than the source-drain electrode, and the upper surface of the oxide semiconductor layer is in contact with the source-drain electrode.

圖1是表示本發明的實施方式的薄膜電晶體、即底部閘 極構造且頂部接觸型的薄膜電晶體的一例的示意圖。 1 is a thin film transistor, that is, a bottom gate showing an embodiment of the present invention. A schematic view of an example of a thin-film transistor of a polar structure and a top contact type.

圖1所示的薄膜電晶體10包括:閘極電極14,形成在基板12的一主面上;閘極絕緣層16,覆蓋該閘極電極14;及氧化物半導體層18,配置在該閘極絕緣層16的配置閘極電極14的側的相反側。進而,薄膜電晶體10包括:源極電極20及汲極電極22,相互分離地配置在氧化物半導體層18的配置閘極絕緣層16的側的相反側;及保護層24,形成在從該等源極電極20與汲極電極22之間露出的氧化物半導體層18的表面上。 The thin film transistor 10 shown in FIG. 1 includes: a gate electrode 14 formed on one main surface of the substrate 12; a gate insulating layer 16 covering the gate electrode 14; and an oxide semiconductor layer 18 disposed on the gate The opposite side of the side of the gate electrode 14 is disposed of the pole insulating layer 16. Further, the thin film transistor 10 includes a source electrode 20 and a drain electrode 22 which are disposed apart from each other on the side opposite to the side where the gate insulating layer 16 of the oxide semiconductor layer 18 is disposed, and a protective layer 24 formed thereon. The surface of the oxide semiconductor layer 18 exposed between the source electrode 20 and the drain electrode 22 is formed.

而且,本例中保護層24包含:無機絕緣層26,與氧化物半導體層18鄰接;及金屬層28,不與源極電極20、汲極電極22接觸而與無機絕緣層26鄰接。 Further, in the present embodiment, the protective layer 24 includes an inorganic insulating layer 26 adjacent to the oxide semiconductor layer 18, and the metal layer 28 is not adjacent to the source electrode 20 and the drain electrode 22 and is adjacent to the inorganic insulating layer 26.

圖2是表示本發明的實施方式的薄膜電晶體、即底部閘極構造且頂部接觸型的薄膜電晶體的另一例的示意圖。 2 is a schematic view showing another example of a thin film transistor of the embodiment of the present invention, that is, a bottom gate structure and a top contact type thin film transistor.

圖2所示的薄膜電晶體30與薄膜電晶體10相同地包括基板12、閘極電極14、閘極絕緣層16、氧化物半導體層18、源極電極20、汲極電極22。進而,薄膜電晶體30具有構成與薄膜電晶體10的保護層24不同的保護層32。 The thin film transistor 30 shown in FIG. 2 includes a substrate 12, a gate electrode 14, a gate insulating layer 16, an oxide semiconductor layer 18, a source electrode 20, and a gate electrode 22, similarly to the thin film transistor 10. Further, the thin film transistor 30 has a protective layer 32 which is different from the protective layer 24 of the thin film transistor 10.

而且,本例中該保護層32包含與氧化物半導體層18鄰接的無機絕緣層34、及設為雙層構造的金屬層36。該金屬層36包括:反射金屬層36A,設置在無機絕緣層34內;及耗損金屬層36B,與反射金屬層36A對向且在外側(基板12方向的相反側)與無機絕緣層34鄰接。 Further, in the present example, the protective layer 32 includes an inorganic insulating layer 34 adjacent to the oxide semiconductor layer 18 and a metal layer 36 having a two-layer structure. The metal layer 36 includes a reflective metal layer 36A disposed in the inorganic insulating layer 34, and a worn metal layer 36B adjacent to the reflective metal layer 36A and adjacent to the inorganic insulating layer 34 on the outer side (opposite side in the direction of the substrate 12).

圖3是表示本發明的實施方式的薄膜電晶體、即底部閘極構造且頂部接觸型的薄膜電晶體的另一例的示意圖。 3 is a schematic view showing another example of a thin film transistor according to an embodiment of the present invention, that is, a bottom gate structure and a top contact type thin film transistor.

圖3所示的薄膜電晶體40與薄膜電晶體10相同地包括基板12、閘極電極14、閘極絕緣層16、氧化物半導體層18、源極電極20、汲極電極22。進而,薄膜電晶體40具有構成與薄膜電晶體10的保護層24不同的保護層42。 The thin film transistor 40 shown in FIG. 3 includes a substrate 12, a gate electrode 14, a gate insulating layer 16, an oxide semiconductor layer 18, a source electrode 20, and a drain electrode 22, similarly to the thin film transistor 10. Further, the thin film transistor 40 has a protective layer 42 which is different from the protective layer 24 of the thin film transistor 10.

而且,本例中該保護層42包括與氧化物半導體層18鄰接的無機絕緣層44、及設置在無機絕緣層44內的金屬層46。 Further, in this example, the protective layer 42 includes an inorganic insulating layer 44 adjacent to the oxide semiconductor layer 18, and a metal layer 46 disposed in the inorganic insulating layer 44.

再者,本實施方式的薄膜電晶體除上述以外,亦可採用各種構成,例如亦可為在基板12上設置絕緣層,或者使氧化物半導體層18為多層,或者在氧化物半導體層18與源極電極20、汲極電極22之間設置接觸層的構成。 Further, the thin film transistor of the present embodiment may have various configurations in addition to the above, and for example, an insulating layer may be provided on the substrate 12, or the oxide semiconductor layer 18 may be a plurality of layers, or the oxide semiconductor layer 18 may be A configuration in which a contact layer is provided between the source electrode 20 and the drain electrode 22.

以下,對薄膜電晶體10、薄膜電晶體30、薄膜電晶體40的各構成要素進行詳述。 Hereinafter, each constituent element of the thin film transistor 10, the thin film transistor 30, and the thin film transistor 40 will be described in detail.

<薄膜電晶體的詳細構成> <Detailed Structure of Thin Film Transistor>

-基板- -Substrate -

關於基板12的形狀、構造、大小等,以存在可形成膜的主面為前提而無特別限制,可根據目的而適當選擇。基板12的構造可為單層構造,亦可為積層構造。 The shape, structure, size, and the like of the substrate 12 are not particularly limited as long as the main surface on which the film can be formed, and may be appropriately selected depending on the purpose. The structure of the substrate 12 may be a single layer structure or a laminate structure.

作為基板12的材質並無特別限定,例如可使用玻璃、釔安定氧化鋯(yttrium-stabilized zirconia,YSZ)等無機基板、樹脂基板或其複合材料等。其中自輕量方面、具有可撓性的方面而 言,較佳為樹脂基板或其複合材料。具體而言,可使用聚對苯二甲酸丁二酯、聚對苯二甲酸乙二酯、聚萘二甲酸乙二酯、聚萘二甲酸丁二酯、聚苯乙烯、聚碳酸酯、聚碸、聚醚碸、聚芳酯、碳酸烯丙基二甘醇酯、聚醯胺、聚醯亞胺、聚醯胺醯亞胺、聚醚醯亞胺、聚苯并唑、聚苯硫醚、聚環烯烴、降冰片烯樹脂、聚氯化三氟化乙烯等氟樹脂、液晶聚合物、丙烯酸樹脂、環氧樹脂、矽酮樹脂、離聚物樹脂、氰酸鹽樹脂、交聯富馬酸二酯、環狀聚烯烴、芳香族醚、馬來醯亞胺烯烴、纖維素、環硫化物化合物等合成樹脂基板、與氧化矽粒子的複合塑膠材料、與金屬奈米粒子、無機氧化物奈米粒子、無機氮化物奈米粒子等的複合塑膠材料、與碳纖維、碳奈米管的複合塑膠材料、與玻璃鱗片、玻璃纖維、玻璃珠的複合塑膠材料、與黏土礦物或具有雲母派生結晶構造的粒子的複合塑膠材料、在薄的玻璃與上述單獨有機材料之間具有至少1次接合界面的積層塑膠材料、藉由將無機層與有機層交替積層而具有至少1次以上接合界面的具有阻隔性能的複合材料、不鏽鋼基板或將不鏽鋼與異種金屬積層而成的金屬多層基板、鋁基板或藉由對表面實施氧化處理(例如陽極氧化處理)而使表面的絕緣性提高的具有氧化皮膜的鋁基板等。又,較佳為樹脂基板,其耐熱性、尺寸穩定性、耐溶劑性、電氣絕緣性、加工性、低透氣性、或低吸濕性等優異。上述樹脂基板較佳為具有用以防止水分或氧透過的氣體阻隔層、或用以提高樹脂基板的平坦性或與下部電極的密接性的底塗層等。此處,在將底塗層形成在樹脂基板 的單面的情形時,因內部殘留應力而導致樹脂基板產生翹曲,因此較佳為對兩面實施塗佈、或者控制為低應力的膜質、或藉由積層而利用壓縮/拉伸應力來控制。又,底塗層為提高阻隔性,較佳為用於後述的閘極絕緣層16等的材料。 The material of the substrate 12 is not particularly limited, and for example, an inorganic substrate such as glass or yttrium-stabilized zirconia (YSZ), a resin substrate, or a composite material thereof can be used. Which is lightweight and flexible. In other words, a resin substrate or a composite material thereof is preferred. Specifically, polybutylene terephthalate, polyethylene terephthalate, polyethylene naphthalate, polybutylene naphthalate, polystyrene, polycarbonate, polyfluorene can be used. , polyether oxime, polyarylate, allyl diglycol carbonate, polyamine, polyimine, polyamidimide, polyether phthalimide, polybenzoxazole, polyphenylene sulfide, Polycycloolefin, norbornene resin, fluororesin such as polychlorotrifluoroethylene, liquid crystal polymer, acrylic resin, epoxy resin, fluorenone resin, ionomer resin, cyanate resin, cross-linked fumaric acid Synthetic resin substrate such as diester, cyclic polyolefin, aromatic ether, maleimide olefin, cellulose, episulfide compound, composite plastic material with cerium oxide particles, metal nanoparticle, inorganic oxide Composite plastic materials such as rice particles, inorganic nitride nanoparticles, composite plastic materials with carbon fibers and carbon nanotubes, composite plastic materials with glass flakes, glass fibers, glass beads, clay minerals or mica-derived crystal structures Composite plastic material for particles, in thin a laminated plastic material having at least one joint interface between the glass and the above-mentioned individual organic material, a composite material having barrier properties having at least one joint interface by alternately laminating the inorganic layer and the organic layer, a stainless steel substrate or a stainless steel A metal multilayer substrate in which a dissimilar metal layer is laminated, an aluminum substrate, or an aluminum substrate having an oxide film which is improved in insulation properties by surface oxidation treatment (for example, anodization treatment). Further, the resin substrate is preferably excellent in heat resistance, dimensional stability, solvent resistance, electrical insulating properties, workability, low gas permeability, or low moisture absorption. The resin substrate preferably has a gas barrier layer for preventing moisture or oxygen from permeating, or an undercoat layer for improving the flatness of the resin substrate or the adhesion to the lower electrode. Here, the undercoat layer is formed on the resin substrate In the case of a single surface, the resin substrate is warped due to internal residual stress. Therefore, it is preferable to apply the coating on both surfaces or to control the film quality with low stress, or to control by compression/tensile stress by lamination. . Further, the undercoat layer is preferably a material for use in a gate insulating layer 16 to be described later, etc., in order to improve barrier properties.

-閘極電極- -Gate electrode -

閘極電極14形成在基板12的一主面上。 The gate electrode 14 is formed on one main surface of the substrate 12.

構成閘極電極14的導電膜較佳為使用具有高導電性的導電膜,例如可使用Al、Mo、Cr、Ta、Ti、Au、Ag等金屬膜、或Al-Nd、Ag合金、氧化錫、氧化鋅、氧化銦、氧化銦錫(ITO)、氧化銦鋅(IZO)等金屬氧化物導電膜等。其中,如後述般,因使金屬層的材料為與閘極電極14相同的材料,因此較佳為使用金屬膜。 The conductive film constituting the gate electrode 14 is preferably a conductive film having high conductivity. For example, a metal film such as Al, Mo, Cr, Ta, Ti, Au, Ag, or Al-Nd, Ag alloy, or tin oxide can be used. A metal oxide conductive film such as zinc oxide, indium oxide, indium tin oxide (ITO) or indium zinc oxide (IZO). Here, as described later, since the material of the metal layer is the same material as that of the gate electrode 14, it is preferable to use a metal film.

-閘極絕緣層- - Gate insulation -

閘極絕緣層16以覆蓋閘極電極14的方式,積層在基板12的相反側的閘極電極14的表面上、及基板12的露出面上。 The gate insulating layer 16 is laminated on the surface of the gate electrode 14 on the opposite side of the substrate 12 and on the exposed surface of the substrate 12 so as to cover the gate electrode 14.

構成閘極絕緣層16的絕緣膜較佳為具有高的絕緣性的絕緣膜,例如設為SiO2、SiNx(x為氮非化學計量)、SiON、Al2O3、Y2O3、Ta2O5、HfO2等的絕緣膜、或包含至少兩種以上該等化合物的絕緣膜。 The insulating film constituting the gate insulating layer 16 is preferably an insulating film having high insulating properties, and is, for example, SiO 2 , SiN x (x is nitrogen non-stoichiometric), SiON, Al 2 O 3 , Y 2 O 3 , An insulating film of Ta 2 O 5 or HfO 2 or an insulating film containing at least two or more of these compounds.

-氧化物半導體層- -Oxide semiconductor layer -

氧化物半導體層18積層在閘極電極14的相反側的閘極絕緣層16的表面上。 The oxide semiconductor layer 18 is laminated on the surface of the gate insulating layer 16 on the opposite side of the gate electrode 14.

氧化物半導體層18只要以包含選自In、Zn、Ga及Sn中的至少1種的氧化物半導體為主體即可,此外亦可含有雜質等。此處,「主體」表示構成氧化物半導體層18的構成成分中含量最多的成分。 The oxide semiconductor layer 18 may be mainly composed of an oxide semiconductor containing at least one selected from the group consisting of In, Zn, Ga, and Sn, and may contain impurities or the like. Here, the "main body" indicates the component having the largest content among the constituent components constituting the oxide semiconductor layer 18.

氧化物半導體亦可為非晶質或結晶質中的任一種,但較佳為使用非晶質氧化物半導體。若由氧化物半導體構成半導體膜,則電荷的遷移率遠遠高於非晶質矽的半導體膜,從而可用低電壓驅動。又,若使用氧化物半導體,則通常可形成透光性較矽高的半導體膜。又,氧化物半導體、尤其是非晶質氧化物半導體可在低溫(例如室溫)均勻地成膜,因此在使用如塑膠般的具有可撓性的樹脂基板時特別有利。 The oxide semiconductor may be either amorphous or crystalline, but an amorphous oxide semiconductor is preferably used. When the semiconductor film is composed of an oxide semiconductor, the mobility of charges is much higher than that of the amorphous germanium semiconductor film, and thus can be driven with a low voltage. Further, when an oxide semiconductor is used, a semiconductor film having a relatively high light transmittance can be usually formed. Further, since an oxide semiconductor, particularly an amorphous oxide semiconductor, can be uniformly formed at a low temperature (for example, room temperature), it is particularly advantageous when a flexible resin substrate such as plastic is used.

作為氧化物半導體的構成材料,只要包含選自In、Zn、Ga及Sn中的至少1種,則並無特別限定,但較佳為包含In、Ga及Zn中的至少1種的氧化物(例如In-O系)。尤其較佳為包含In、Ga及Zn中的至少2種的氧化物(例如In-Zn-O系、In-Ga-O系、Ga-Zn-O系),更佳為包含In、Ga及Zn的全部的氧化物。作為In-Ga-Zn-O系氧化物半導體,較佳為以結晶狀態下的組成為InGaO3(ZnO)m(m為小於6的自然數)表示的氧化物半導體,尤其,更佳為InGaZnO4。作為該組成的氧化物半導體的特徵,隨著導電度增加而表現出電子遷移率增加的傾向。其中,In-Ga-Zn-O系的組成比,嚴格來說不必為In:Ga:Zn=1:1:1。 The constituent material of the oxide semiconductor is not particularly limited as long as it contains at least one selected from the group consisting of In, Zn, Ga, and Sn, and is preferably an oxide containing at least one of In, Ga, and Zn ( For example, In-O system). In particular, it is preferable to contain at least two kinds of oxides of In, Ga, and Zn (for example, In-Zn-O-based, In-Ga-O-based, and Ga-Zn-O-based), and more preferably include In, Ga, and All oxides of Zn. As the In—Ga—Zn—O-based oxide semiconductor, an oxide semiconductor having a composition in a crystalline state of InGaO 3 (ZnO) m (m is a natural number less than 6) is preferable, and more preferably, InGaZnO is preferable. 4 . The characteristics of the oxide semiconductor having such a composition tend to increase the electron mobility as the conductivity increases. Among them, the composition ratio of the In-Ga-Zn-O system is not necessarily strictly In:Ga:Zn=1:1:1.

氧化物半導體層18的層構造亦可包含2層以上,氧化 物半導體層18包含低電阻層與高電阻層,較佳為低電阻層與閘極絕緣層16接觸,高電阻層與源極電極20及汲極電極22的至少一者電性接觸。 The layer structure of the oxide semiconductor layer 18 may also include two or more layers, and is oxidized. The semiconductor layer 18 includes a low resistance layer and a high resistance layer. Preferably, the low resistance layer is in contact with the gate insulating layer 16, and the high resistance layer is in electrical contact with at least one of the source electrode 20 and the drain electrode 22.

氧化物半導體層18的厚度並無特別限定,自確保載子遷移及抑制成本這兩者的觀點考慮,較佳為30nm以上且60nm以下。 The thickness of the oxide semiconductor layer 18 is not particularly limited, and is preferably 30 nm or more and 60 nm or less from the viewpoint of ensuring both carrier migration and cost reduction.

-源極-汲極電極- -Source-drain electrode -

源極電極20、汲極電極22相互隔開間隔而形成在閘極絕緣層16的相反側的氧化物半導體層18的表面上,可藉由閘極電極14的施加電壓而與氧化物半導體層18導通。 The source electrode 20 and the drain electrode 22 are formed on the surface of the oxide semiconductor layer 18 on the opposite side of the gate insulating layer 16 with a space therebetween, and the oxide semiconductor layer can be applied by the applied voltage of the gate electrode 14. 18 conduction.

構成源極電極20、汲極電極22的導電膜,使用具有高導電性的導電膜,例如可使用Al、Mo、Cr、Ta、Ti、Au、Ag等金屬膜、Al-Nd、Ag合金、氧化錫、氧化鋅、氧化銦、氧化銦錫(ITO)、氧化銦鋅(IZO)等金屬氧化物導電膜等而形成。其中,如後述般,因使金屬層的材料為與源極電極20、汲極電極22相同的材料,由此較佳為使用金屬膜。又,作為源極電極20、汲極電極22,可使該等導電膜為單層構造或2層以上的積層構造來使用。 The conductive film constituting the source electrode 20 and the drain electrode 22 is made of a conductive film having high conductivity. For example, a metal film such as Al, Mo, Cr, Ta, Ti, Au, Ag, or Al-Nd or Ag alloy can be used. It is formed by a metal oxide conductive film such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO) or indium zinc oxide (IZO). Here, as described later, since the material of the metal layer is the same material as that of the source electrode 20 and the gate electrode 22, it is preferable to use a metal film. Moreover, as the source electrode 20 and the drain electrode 22, these conductive films can be used in a single layer structure or a laminated structure of two or more layers.

若考慮成膜性、或利用蝕刻或舉離(lift off)法的圖案性、導電性等,則所成膜的導電膜的膜厚較佳為1nm以上且1000nm以下,更佳為50nm以上且500nm以下。 In consideration of film formability, patterning property by electroplating or lift off method, conductivity, and the like, the film thickness of the formed conductive film is preferably 1 nm or more and 1000 nm or less, and more preferably 50 nm or more. Below 500 nm.

-保護層- -The protective layer-

薄膜電晶體10、薄膜電晶體30、薄膜電晶體40的各保護層 24、保護層32、保護層42,積層在自源極電極20與汲極電極22之間露出的氧化物半導體層18上,保護氧化物半導體層18免受水或氧等的傷害。 Protective layers of the thin film transistor 10, the thin film transistor 30, and the thin film transistor 40 24. The protective layer 32 and the protective layer 42 are laminated on the oxide semiconductor layer 18 exposed between the source electrode 20 and the drain electrode 22 to protect the oxide semiconductor layer 18 from water, oxygen, or the like.

又,各保護層24、保護層32、保護層42包含無機絕緣層26、無機絕緣層34、無機絕緣層44、及金屬層28、金屬層36、金屬層46。 Further, each of the protective layer 24, the protective layer 32, and the protective layer 42 includes an inorganic insulating layer 26, an inorganic insulating layer 34, an inorganic insulating layer 44, and a metal layer 28, a metal layer 36, and a metal layer 46.

藉此,本實施方式的薄膜電晶體10、薄膜電晶體30、薄膜電晶體40中,即便自保護層24、保護層32、保護層42的外側(基板12的相反側)向氧化物半導體層18側入射波長400nm以上且450nm以下的光,由於存在金屬層28、金屬層36、金屬層46,因此亦會於此處反射,由此可抑制到達氧化物半導體層18的光量。由此,即便氧化物半導體層18包含選自In、Zn、Ga及Sn中的至少1種而不耐受波長400nm以上且450nm以下的光(即便引起薄膜電晶體的工作不穩定),亦可抑制到達氧化物半導體層18的光量,因此可確保薄膜電晶體10、薄膜電晶體30、薄膜電晶體40在光照射時的工作穩定性。 Thereby, in the thin film transistor 10, the thin film transistor 30, and the thin film transistor 40 of the present embodiment, the outer side of the protective layer 24, the protective layer 32, and the protective layer 42 (opposite side of the substrate 12) is directed to the oxide semiconductor layer. Since light having an incident wavelength of 400 nm or more and 450 nm or less on the 18 side is reflected by the metal layer 28, the metal layer 36, and the metal layer 46, the amount of light reaching the oxide semiconductor layer 18 can be suppressed. Therefore, even if the oxide semiconductor layer 18 contains at least one selected from the group consisting of In, Zn, Ga, and Sn and does not withstand light having a wavelength of 400 nm or more and 450 nm or less (even if the operation of the thin film transistor is unstable), The amount of light reaching the oxide semiconductor layer 18 is suppressed, so that the operational stability of the thin film transistor 10, the thin film transistor 30, and the thin film transistor 40 at the time of light irradiation can be ensured.

又,金屬層28、金屬層36、金屬層46的緻密性較作為通常的保護層而以單體來使用的無機絕緣層26、無機絕緣層34、無機絕緣層44高,因此水或氧等難以自保護層24、保護層32、保護層42的外側向氧化物半導體層18側透過,從而可提高對氧化物半導體層18的保護功能。 Further, the denseness of the metal layer 28, the metal layer 36, and the metal layer 46 is higher than that of the inorganic insulating layer 26, the inorganic insulating layer 34, and the inorganic insulating layer 44 which are used as a single protective layer as a normal protective layer, and thus water, oxygen, etc. It is difficult to transmit the outer side of the protective layer 24, the protective layer 32, and the protective layer 42 to the side of the oxide semiconductor layer 18, whereby the protective function to the oxide semiconductor layer 18 can be improved.

進而,與使用吸收光的吸收膜作為遮光層的情形相比,若使 用金屬層28、金屬層36、金屬層46,則可抑制由光照射而引起的熱的產生。 Further, compared with the case where an absorbing film that absorbs light is used as a light shielding layer, By using the metal layer 28, the metal layer 36, and the metal layer 46, generation of heat due to light irradiation can be suppressed.

進而又,由於金屬層28、金屬層36、金屬層46以外的保護層24、保護層32、保護層42的部分為無機絕緣層26、無機絕緣層34、無機絕緣層44,因此與水分易於透過的有機絕緣層的情形相比,金屬層28、金屬層36、金屬層46不易生銹。 Further, since the metal layer 28, the metal layer 36, the protective layer 24 other than the metal layer 46, the protective layer 32, and the portion of the protective layer 42 are the inorganic insulating layer 26, the inorganic insulating layer 34, and the inorganic insulating layer 44, it is easy to be separated from moisture. The metal layer 28, the metal layer 36, and the metal layer 46 are less likely to rust than in the case of the transmitted organic insulating layer.

無機絕緣層26、無機絕緣層34、無機絕緣層44的構成材料並無特別限定,可列舉SiO2、SiO、MgO、Al2O3、GeO、NiO、SrO、Y2O3、ZrO2、CeO2、Rb2O、Sc2O3、La2O3、Nd2O3、Sm2O3、Gd2O3、Dy2O3、Er2O3、Yb2O3、Ta2O3、Ta2O5、Nb2O5、HfO2、Ga2O3、TiO2等金屬氧化物、AlN、SiN、SiNxOy等金屬氮化物等無機材料。其中,較佳為成膜速度快的SiO2或Gd2O3等,更佳為Gd2O3。又,亦可使用藉由氧量調整、組成調整、或元素摻雜等而使電阻率變化等來與In-Ga-Zn-O系等氧化物半導體層18相同的材料。 The constituent material of the inorganic insulating layer 26, the inorganic insulating layer 34, and the inorganic insulating layer 44 is not particularly limited, and examples thereof include SiO 2 , SiO, MgO, Al 2 O 3 , GeO, NiO, SrO, Y 2 O 3 , and ZrO 2 . CeO 2 , Rb 2 O, Sc 2 O 3 , La 2 O 3 , Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , Dy 2 O 3 , Er 2 O 3 , Yb 2 O 3 , Ta 2 O 3 , an inorganic material such as a metal oxide such as Ta 2 O 5 , Nb 2 O 5 , HfO 2 , Ga 2 O 3 or TiO 2 or a metal nitride such as AlN, SiN or SiN x O y . Wherein, preferably SiO 2 film speed of Gd 2 O 3 or the like, more preferably Gd 2 O 3. Further, a material which is the same as the oxide semiconductor layer 18 such as the In—Ga—Zn—O-based material by changing the resistivity or the like by oxygen amount adjustment, composition adjustment, element doping or the like can be used.

又,自提高與氧化物半導體層18的密接性的觀點考慮,較佳為無機絕緣層26、無機絕緣層34、無機絕緣層44包含構成氧化物半導體層18的材料的至少一部分金屬。同樣地,無機絕緣層26、無機絕緣層34、無機絕緣層44,較佳為包含金屬層28、金屬層36、金屬層46的金屬材料。 Moreover, from the viewpoint of improving the adhesion to the oxide semiconductor layer 18, the inorganic insulating layer 26, the inorganic insulating layer 34, and the inorganic insulating layer 44 preferably contain at least a part of the metal constituting the oxide semiconductor layer 18. Similarly, the inorganic insulating layer 26, the inorganic insulating layer 34, and the inorganic insulating layer 44 are preferably metal materials including the metal layer 28, the metal layer 36, and the metal layer 46.

自確保保護功能及抑制成本這兩者的觀點考慮,無機絕緣層26、無機絕緣層34、無機絕緣層44的厚度較佳為1μm以上且1mm以下。進而佳為5μm以上且100μm以下,最佳為10μm 以上且50μm以下。 The thickness of the inorganic insulating layer 26, the inorganic insulating layer 34, and the inorganic insulating layer 44 is preferably 1 μm or more and 1 mm or less from the viewpoint of both the protective function and the cost. Further preferably, it is 5 μm or more and 100 μm or less, and most preferably 10 μm. Above and 50 μm or less.

又,如圖1及圖2所示般,無機絕緣層26、及包含反射金屬層36A的無機絕緣層34的厚度較佳為大於等於源極電極20、汲極電極22的厚度,以使積層在其上的金屬層28及耗損金屬層36B不與源極電極20、汲極電極22接觸,為防止由成膜誤差或圖案化誤差所引起的誤接觸,較佳為超過源極電極20、汲極電極22的厚度。 Further, as shown in FIGS. 1 and 2, the thickness of the inorganic insulating layer 26 and the inorganic insulating layer 34 including the reflective metal layer 36A is preferably equal to or greater than the thickness of the source electrode 20 and the drain electrode 22 to laminate The metal layer 28 and the worn metal layer 36B are not in contact with the source electrode 20 and the drain electrode 22, and are preferably over the source electrode 20 in order to prevent erroneous contact caused by film formation errors or patterning errors. The thickness of the drain electrode 22.

金屬層28、金屬層36、金屬層46不與源極電極20、汲極電極22接觸(為非導通),其構成材料在製造時可使用同一靶材(target)(同一材料),自可抑制製造成本的觀點考慮,較佳為與源極電極20、汲極電極22相同。或自相同的觀點考慮,金屬層28、金屬層36、金屬層46的構成材料較佳為與閘極電極14相同。進而,自進一步抑制製造成本的觀點考慮,金屬層28、金屬層36、金屬層46的構成材料較佳為與源極電極20、汲極電極22及閘極電極14相同。 The metal layer 28, the metal layer 36, and the metal layer 46 are not in contact with the source electrode 20 and the gate electrode 22 (non-conducting), and the constituent materials can be used in the same target (the same material). From the viewpoint of suppressing the manufacturing cost, it is preferably the same as the source electrode 20 and the drain electrode 22. The constituent materials of the metal layer 28, the metal layer 36, and the metal layer 46 are preferably the same as those of the gate electrode 14 from the same viewpoint. Further, from the viewpoint of further suppressing the manufacturing cost, the constituent materials of the metal layer 28, the metal layer 36, and the metal layer 46 are preferably the same as those of the source electrode 20, the gate electrode 22, and the gate electrode 14.

具體而言,構成材料可列舉Al、Cu、Ni、Mo、Cr、Ta、Ti、Au、Ag、Pt、Rh、Sn、Fe、Nb、Si、Mo-Nb等金屬材料。金屬層28、金屬層36、金屬層46的構成材料,較佳為上述中的對波長400nm以上且450nm以下的光的反射率為50%以上的Ag、Al、Rh、Mo。 Specifically, the constituent material may be a metal material such as Al, Cu, Ni, Mo, Cr, Ta, Ti, Au, Ag, Pt, Rh, Sn, Fe, Nb, Si, or Mo-Nb. The constituent material of the metal layer 28, the metal layer 36, and the metal layer 46 is preferably Ag, Al, Rh, or Mo having a reflectance of 50% or more for light having a wavelength of 400 nm or more and 450 nm or less.

本實施方式的金屬層較佳為如金屬層28、金屬層36般至少其一部分形成在保護層24、保護層32的頂部。其原因在於如 後述般,可同時進行金屬層28、金屬層36的形成與源極電極20、汲極電極22的形成,從而可簡化製造製程。 The metal layer of the present embodiment is preferably formed on at least a portion of the protective layer 24 and the protective layer 32, such as the metal layer 28 and the metal layer 36. The reason is such as As will be described later, the formation of the metal layer 28 and the metal layer 36 and the formation of the source electrode 20 and the drain electrode 22 can be simultaneously performed, thereby simplifying the manufacturing process.

又,本實施方式的金屬層並非如金屬層28、金屬層46般為單層,較佳為如金屬層36般為多層。其原因在於,若為多層,則可抑制位於內側的金屬層的劣化。再者,更佳為無機絕緣層夾在多層之間。 Further, the metal layer of the present embodiment is not a single layer like the metal layer 28 or the metal layer 46, and is preferably a multilayer such as the metal layer 36. This is because if it is a multilayer, deterioration of the metal layer located inside can be suppressed. Further, it is more preferable that the inorganic insulating layer is sandwiched between the plurality of layers.

具體而言,若列舉圖2所示的金屬層36為例進行說明,則耗損金屬層36B隔著無機絕緣層34而配置在反射金屬層36A的外側,因此接收來自外側的水或氧等。由此,位於內側的反射金屬層36A不接收水或氧等,從而可抑制反射金屬層36A的劣化(氫氧化等)。藉此,反射金屬層36A可維持金屬層36原本的功能即反射功能。 Specifically, when the metal layer 36 shown in FIG. 2 is taken as an example, the worn metal layer 36B is disposed outside the reflective metal layer 36A via the inorganic insulating layer 34, and thus receives water or oxygen from the outside. Thereby, the reflective metal layer 36A located inside does not receive water, oxygen, etc., and can suppress deterioration (hydrogenation etc.) of the reflective metal layer 36A. Thereby, the reflective metal layer 36A can maintain the original function of the metal layer 36, that is, the reflective function.

耗損金屬層36B接收水或氧,因此較佳為耐腐蝕性較反射金屬層36A高。另一方面,較佳為反射金屬層36A的反射率較耗損金屬層36B高。再者,反射金屬層36A因存在耗損金屬層36B而相應地使得考慮耐腐蝕性的必要性低,因此反射率高的材料的選擇範圍廣。 The worn metal layer 36B receives water or oxygen, and thus it is preferable that the corrosion resistance is higher than that of the reflective metal layer 36A. On the other hand, it is preferable that the reflective metal layer 36A has a higher reflectance than the worn metal layer 36B. Further, since the reflective metal layer 36A has a low necessity for considering the corrosion resistance due to the presence of the worn metal layer 36B, the material having a high reflectance has a wide selection range.

金屬層28、金屬層36、金屬層46的總厚度並無特別限定,但自抑制金屬層28、金屬層36、金屬層46的電容而避免發熱的觀點考慮,較佳為50nm以上。 The total thickness of the metal layer 28, the metal layer 36, and the metal layer 46 is not particularly limited, but is preferably 50 nm or more from the viewpoint of suppressing the capacitance of the metal layer 28, the metal layer 36, and the metal layer 46 from heat generation.

又,為了避免金屬層28或耗損金屬層36B與源極電極20、汲極電極22的電氣導通,而使無機絕緣層26的厚度厚於源極電 極20、汲極電極22的厚度來配置為不與源極電極20、汲極電極22接觸的高度。又,金屬層46或反射金屬層36A由無機絕緣層44、無機絕緣層34包圍,而不與源極電極20、汲極電極22接觸。 Moreover, in order to avoid electrical conduction between the metal layer 28 or the worn metal layer 36B and the source electrode 20 and the drain electrode 22, the thickness of the inorganic insulating layer 26 is thicker than that of the source electrode. The thickness of the pole 20 and the drain electrode 22 is set to a height that does not contact the source electrode 20 and the drain electrode 22. Further, the metal layer 46 or the reflective metal layer 36A is surrounded by the inorganic insulating layer 44 and the inorganic insulating layer 34, and is not in contact with the source electrode 20 and the drain electrode 22.

2.氧化物半導體元件的製造方法:薄膜電晶體的製造方法 2. Method for producing an oxide semiconductor device: a method for manufacturing a thin film transistor

其次,作為本實施方式的氧化物半導體元件的製造方法而列舉薄膜電晶體10的製造方法為一例來進行說明。 Next, a method of manufacturing the thin film transistor 10 will be described as an example of a method for producing an oxide semiconductor device according to the present embodiment.

(薄膜電晶體10的製造方法) (Method of Manufacturing Thin Film Transistor 10)

圖4(A)~圖4(F)及圖5(A)~圖5(C)是薄膜電晶體10的一連串的製造步驟圖。 4(A) to 4(F) and Figs. 5(A) to 5(C) are diagrams showing a series of manufacturing steps of the thin film transistor 10.

-閘極電極形成步驟- - Gate electrode formation step -

首先,進行閘極電極形成步驟。在該閘極電極形成步驟中,如圖4(A)所示般準備基板12。然後,如圖4(B)所示般,在所準備的基板12上形成導電膜14A。作為該導電膜14A的成膜方法,使用印刷方式、塗佈(coating)方式等濕式方式、真空蒸鍍法、濺鍍法、離子鍍敷(ion plating)法等物理方式、化學氣相沈積(Chemical Vapor Deposition,CVD)、電漿化學氣相沈積法等化學方式等中與所使用的材料相適合的方法。 First, a gate electrode forming step is performed. In the gate electrode forming step, the substrate 12 is prepared as shown in Fig. 4(A). Then, as shown in FIG. 4(B), a conductive film 14A is formed on the prepared substrate 12. As a film formation method of the conductive film 14A, a physical method such as a wet method such as a printing method or a coating method, a vacuum vapor deposition method, a sputtering method, or an ion plating method, or chemical vapor deposition is used. (Chemical Vapor Deposition, CVD), chemical methods such as plasma chemical vapor deposition, and the like, which are suitable for the materials used.

成膜後,如圖4(C)所示般,藉由光微影及蝕刻法或舉離法等將導電膜14A圖案化為規定的形狀,藉此自導電膜14A形成閘極電極14。此時,較佳為將閘極電極14及閘極配線同時圖案化。 After the film formation, as shown in FIG. 4(C), the conductive film 14A is patterned into a predetermined shape by photolithography, etching, lift-off, or the like, whereby the gate electrode 14 is formed from the conductive film 14A. At this time, it is preferable to simultaneously pattern the gate electrode 14 and the gate wiring.

-閘極絕緣層形成步驟、氧化物半導體層形成步驟及無機絕緣層形成步驟- - gate insulating layer forming step, oxide semiconductor layer forming step, and inorganic insulating layer forming step -

其次,進行閘極絕緣層形成步驟、氧化物半導體層形成步驟及無機絕緣層形成步驟。該等形成步驟亦可按閘極絕緣層形成步驟、氧化物半導體層形成步驟及無機絕緣層形成步驟的順序依序進行,但亦可同時進行,又亦可如以下般僅在成膜時依序進行,而圖案化按相反順序進行。 Next, a gate insulating layer forming step, an oxide semiconductor layer forming step, and an inorganic insulating layer forming step are performed. The forming step may be sequentially performed in the order of the gate insulating layer forming step, the oxide semiconductor layer forming step, and the inorganic insulating layer forming step, but may be performed simultaneously, or may be performed only at the time of film formation as follows The sequence proceeds, and the patterning proceeds in the reverse order.

該等形成步驟中,首先如圖4(D)所示般,在閘極電極14上及基板12上,依序形成絕緣膜16A、氧化物半導體膜18A及絕緣膜26A。 In the forming step, first, as shown in FIG. 4(D), the insulating film 16A, the oxide semiconductor film 18A, and the insulating film 26A are sequentially formed on the gate electrode 14 and the substrate 12.

作為該等成膜方法,使用印刷方式、塗佈方式等濕式方式、真空蒸鍍法、濺鍍法、離子鍍敷法等物理方式、化學氣相沈積、電漿化學氣相沈積法等化學方式等中與所使用的材料相適合的方法。該等中,自易於控制膜厚的觀點考慮,較佳為使用真空蒸鍍法、濺鍍法、離子鍍敷法、化學氣相沈積或電漿化學氣相沈積法等氣相成膜法。氣相成膜法中,更佳為濺鍍法、脈衝雷射沈積法(Pulsed Laser Deposition,PLD)法)。進而,自量產性的觀點考慮,更佳為濺鍍法。例如,可藉由射頻(radio frequency,RF)磁控濺鍍成膜法而控制真空度及氧流量來成膜。 As such a film forming method, a wet method such as a printing method or a coating method, a physical method such as a vacuum vapor deposition method, a sputtering method, or an ion plating method, or a chemical vapor deposition or a plasma chemical vapor deposition method is used. A method suitable for the materials used in the method and the like. Among these, from the viewpoint of easy control of the film thickness, a vapor phase film formation method such as a vacuum deposition method, a sputtering method, an ion plating method, a chemical vapor deposition method or a plasma chemical vapor deposition method is preferably used. In the vapor phase film formation method, a sputtering method or a Pulsed Laser Deposition (PLD) method is more preferable. Further, from the viewpoint of mass productivity, it is more preferably a sputtering method. For example, the film can be formed by a radio frequency (RF) magnetron sputtering film formation method to control the degree of vacuum and oxygen flow.

再者,在可連續地形成該些膜的方面而言,絕緣膜16A、氧化物半導體膜18A及絕緣膜26A的成膜方法較佳為相同。 Further, in the aspect in which the films can be formed continuously, the film formation methods of the insulating film 16A, the oxide semiconductor film 18A, and the insulating film 26A are preferably the same.

其次,如圖4(E)所示般,藉由光微影及蝕刻法或舉 離法等將絕緣膜26A圖案化為規定的形狀。藉此,自絕緣膜26A形成作為保護層24的一部分的無機絕緣層26。 Next, as shown in Fig. 4(E), by photolithography and etching or lifting The insulating film 26A is patterned into a predetermined shape by a separation method or the like. Thereby, the inorganic insulating layer 26 which is a part of the protective layer 24 is formed from the insulating film 26A.

其次,如圖4(F)所示般,藉由光微影及蝕刻法或舉離法等將氧化物半導體膜18A圖案化為規定的形狀。藉此,自氧化物半導體膜18A形成氧化物半導體層18。此處,氧化物半導體膜18A的與閘極電極14對向的通道部分被無機絕緣層26覆蓋,因此該無機絕緣層26發揮向通道部分的蝕刻終止層的作用。由此,可抑制通道部分因蝕刻而劣化。 Next, as shown in FIG. 4(F), the oxide semiconductor film 18A is patterned into a predetermined shape by photolithography, etching, lift-off, or the like. Thereby, the oxide semiconductor layer 18 is formed from the oxide semiconductor film 18A. Here, the channel portion of the oxide semiconductor film 18A opposed to the gate electrode 14 is covered by the inorganic insulating layer 26, and therefore the inorganic insulating layer 26 functions as an etch stop layer to the channel portion. Thereby, deterioration of the channel portion due to etching can be suppressed.

其次,如圖5(A)所示般,藉由光微影及蝕刻法或舉離法等將絕緣膜16A圖案化為規定的形狀。藉此,自絕緣膜16A形成閘極絕緣層16。此處,氧化物半導體膜18A的與閘極電極14對向的通道部分被無機絕緣層26覆蓋,因此該無機絕緣層26發揮向通道部分的蝕刻終止層的作用。由此,可抑制通道部分因蝕刻而劣化。 Next, as shown in FIG. 5(A), the insulating film 16A is patterned into a predetermined shape by photolithography, etching, lift-off, or the like. Thereby, the gate insulating layer 16 is formed from the insulating film 16A. Here, the channel portion of the oxide semiconductor film 18A opposed to the gate electrode 14 is covered by the inorganic insulating layer 26, and therefore the inorganic insulating layer 26 functions as an etch stop layer to the channel portion. Thereby, deterioration of the channel portion due to etching can be suppressed.

其次,如圖5(B)所示般,在無機絕緣層26上、氧化物半導體層18上及閘極絕緣層16上形成金屬導電膜20A。 Next, as shown in FIG. 5(B), a metal conductive film 20A is formed on the inorganic insulating layer 26, on the oxide semiconductor layer 18, and on the gate insulating layer 16.

作為其成膜方法,使用印刷方式、塗佈方式等濕式方式、真空蒸鍍法、濺鍍法、離子鍍敷法等物理方式、化學氣相沈積、電漿化學氣相沈積法等化學方式等中與所使用的材料相適合的方法。 As a film formation method, a chemical method such as a wet method such as a printing method or a coating method, a vacuum vapor deposition method, a sputtering method, or an ion plating method, or a chemical method such as chemical vapor deposition or plasma chemical vapor deposition is used. A method that is compatible with the materials used.

-源極-汲極電極形成步驟及金屬層形成步驟- - source-drain electrode forming step and metal layer forming step -

其次,如圖5(C)所示般,藉由光微影及蝕刻法或舉離法等 將金屬導電膜20A圖案化為規定的形狀,而自金屬導電膜20A形成源極電極20、汲極電極22。此處,作為保護層24的一部分的金屬層28亦可在其後形成,但自簡化製造製程的觀點考慮,較佳為在將金屬導電膜20A圖案化時,在源極電極20與汲極電極22之間,在無機絕緣層26的表面殘留金屬導電膜20A而形成金屬層28。 Next, as shown in FIG. 5(C), by photolithography and etching or lift-off method, etc. The metal conductive film 20A is patterned into a predetermined shape, and the source electrode 20 and the drain electrode 22 are formed from the metal conductive film 20A. Here, the metal layer 28 as a part of the protective layer 24 may be formed thereafter, but from the viewpoint of simplifying the manufacturing process, it is preferable to pattern the metal conductive film 20A at the source electrode 20 and the drain electrode. Between the electrodes 22, the metal conductive film 20A remains on the surface of the inorganic insulating layer 26 to form the metal layer 28.

藉由以上步驟而製作出圖1所示的薄膜電晶體10。 The thin film transistor 10 shown in Fig. 1 was produced by the above steps.

(薄膜電晶體30的製造方法) (Method of Manufacturing Thin Film Transistor 30)

其次,作為本實施方式的氧化物半導體元件的製造方法而列舉薄膜電晶體30的製造方法為一例來進行說明。 Next, a method of manufacturing the thin film transistor 30 will be described as an example of a method of manufacturing the oxide semiconductor device of the present embodiment.

圖6(A)~圖6(F)及圖7(A)~圖7(C)是薄膜電晶體30的一連串的製造步驟圖。 6(A) to 6(F) and Figs. 7(A) to 7(C) are diagrams showing a series of manufacturing steps of the thin film transistor 30.

-閘極電極形成步驟- - Gate electrode formation step -

首先,進行閘極電極形成步驟。該閘極電極形成步驟如圖6(A)~圖6(C)所示般與薄膜電晶體10的閘極電極形成步驟相同。 First, a gate electrode forming step is performed. This gate electrode forming step is the same as the gate electrode forming step of the thin film transistor 10 as shown in FIGS. 6(A) to 6(C).

-閘極絕緣層形成步驟、氧化物半導體層形成步驟、無機絕緣層形成步驟及金屬層形成步驟- - gate insulating layer forming step, oxide semiconductor layer forming step, inorganic insulating layer forming step, and metal layer forming step -

其次,進行閘極絕緣層形成步驟、氧化物半導體層形成步驟、無機絕緣層形成步驟及金屬層形成步驟。該等形成步驟亦可按閘極絕緣層形成步驟、氧化物半導體層形成步驟及無機絕緣層形成步驟的順序依序進行,但亦可同時進行,又亦可如以下般僅在成 膜時依序進行,而圖案化按相反順序進行。 Next, a gate insulating layer forming step, an oxide semiconductor layer forming step, an inorganic insulating layer forming step, and a metal layer forming step are performed. The forming step may be sequentially performed in the order of the gate insulating layer forming step, the oxide semiconductor layer forming step, and the inorganic insulating layer forming step, but may be performed simultaneously or may be performed as follows The film is carried out sequentially, and the patterning is carried out in the reverse order.

該等形成步驟中,首先,如圖6(D)所示般,在閘極電極14上及基板12上依序形成絕緣膜16A、氧化物半導體膜18A、絕緣膜34A、及金屬導電膜36C。成膜方法與薄膜電晶體10的各膜的成膜方法相同。 In the forming step, first, as shown in FIG. 6(D), the insulating film 16A, the oxide semiconductor film 18A, the insulating film 34A, and the metal conductive film 36C are sequentially formed on the gate electrode 14 and the substrate 12. . The film formation method is the same as the film formation method of each film of the thin film transistor 10.

其次,如圖6(E)所示般,藉由光微影及蝕刻法或舉離法等而將絕緣膜34A及金屬導電膜36C圖案化為規定的形狀。藉此,自絕緣膜34A形成無機絕緣層34的一部分,且自金屬導電膜36C形成反射金屬層36A。 Next, as shown in FIG. 6(E), the insulating film 34A and the metal conductive film 36C are patterned into a predetermined shape by photolithography, etching, lift-off, or the like. Thereby, a part of the inorganic insulating layer 34 is formed from the insulating film 34A, and the reflective metal layer 36A is formed from the metal conductive film 36C.

其次,如圖6(F)所示般,在氧化物半導體膜18A上及反射金屬層36A上形成絕緣膜34B。作為其成膜方法,使用印刷方式、塗佈方式等濕式方式、真空蒸鍍法、濺鍍法、離子鍍敷法等物理方式、化學氣相沈積、電漿化學氣相沈積法等化學方式等中與所使用的材料相適合的方法。 Next, as shown in FIG. 6(F), an insulating film 34B is formed on the oxide semiconductor film 18A and the reflective metal layer 36A. As a film formation method, a chemical method such as a wet method such as a printing method or a coating method, a vacuum vapor deposition method, a sputtering method, or an ion plating method, or a chemical method such as chemical vapor deposition or plasma chemical vapor deposition is used. A method that is compatible with the materials used.

其次,如圖7(A)所示般,藉由光微影及蝕刻法或舉離法等將絕緣膜34B圖案化為規定的形狀。藉此,自絕緣膜34B與之前形成的一部分無機絕緣層34形成作為保護層32的一部分的無機絕緣層34。在其形成時,反射金屬層36A由無機絕緣層34包圍。 Next, as shown in FIG. 7(A), the insulating film 34B is patterned into a predetermined shape by photolithography, etching, lift-off, or the like. Thereby, the inorganic insulating layer 34 as a part of the protective layer 32 is formed from the insulating film 34B and a part of the inorganic insulating layer 34 previously formed. The reflective metal layer 36A is surrounded by the inorganic insulating layer 34 at the time of its formation.

其次,如圖7(B)所示般,藉由光微影及蝕刻法或舉離法等將氧化物半導體膜18A圖案化為規定的形狀。藉此,自氧化物半導體膜18A形成氧化物半導體層18。此處,氧化物半導體 膜18A的與閘極電極14對向的通道部分被無機絕緣層34覆蓋,因此該無機絕緣層34發揮向通道部分的蝕刻終止層的作用。由此,可抑制通道部分因蝕刻而劣化。 Next, as shown in FIG. 7(B), the oxide semiconductor film 18A is patterned into a predetermined shape by photolithography, etching, lift-off or the like. Thereby, the oxide semiconductor layer 18 is formed from the oxide semiconductor film 18A. Here, the oxide semiconductor The channel portion of the film 18A opposed to the gate electrode 14 is covered by the inorganic insulating layer 34, and thus the inorganic insulating layer 34 functions as an etch stop layer to the channel portion. Thereby, deterioration of the channel portion due to etching can be suppressed.

其次,如圖7(C)所示般,藉由光微影及蝕刻法或舉離法等將絕緣膜16A圖案化為規定的形狀。藉此,自絕緣膜16A形成閘極絕緣層16。此處,氧化物半導體膜18A的與閘極電極14對向的通道部分被無機絕緣層34覆蓋,因此該無機絕緣層34發揮向通道部分的蝕刻終止層的作用。由此,可抑制通道部分因蝕刻而劣化。 Next, as shown in FIG. 7(C), the insulating film 16A is patterned into a predetermined shape by photolithography, etching, lift-off or the like. Thereby, the gate insulating layer 16 is formed from the insulating film 16A. Here, the channel portion of the oxide semiconductor film 18A opposed to the gate electrode 14 is covered by the inorganic insulating layer 34, and therefore the inorganic insulating layer 34 functions as an etch stop layer to the channel portion. Thereby, deterioration of the channel portion due to etching can be suppressed.

其次,如圖7(D)所示般,在無機絕緣層34上、氧化物半導體層18上及閘極絕緣層16上形成金屬導電膜20A。成膜方法與薄膜電晶體30的各膜的成膜方法相同。 Next, as shown in Fig. 7(D), a metal conductive film 20A is formed on the inorganic insulating layer 34, on the oxide semiconductor layer 18, and on the gate insulating layer 16. The film formation method is the same as the film formation method of each film of the thin film transistor 30.

-源極-汲極電極形成步驟及金屬層形成步驟- - source-drain electrode forming step and metal layer forming step -

其次,如圖7(E)所示般,藉由光微影及蝕刻法或舉離法等將金屬導電膜20A圖案化為規定的形狀,而自金屬導電膜20A形成源極電極20、汲極電極22。此處,作為保護層32的一部分的耗損金屬層36B亦可在其後形成,但自簡化製造製程的觀點考慮,較佳為在將金屬導電膜20A圖案化時,在源極電極20與汲極電極22之間,在無機絕緣層34上殘留金屬導電膜20A而形成耗損金屬層36B。 Next, as shown in FIG. 7(E), the metal conductive film 20A is patterned into a predetermined shape by photolithography, etching, lift-off, or the like, and the source electrode 20 and the germanium are formed from the metal conductive film 20A. Polar electrode 22. Here, the worn metal layer 36B which is a part of the protective layer 32 may be formed thereafter, but from the viewpoint of simplifying the manufacturing process, it is preferable to pattern the metal conductive film 20A at the source electrode 20 and the germanium electrode 20 Between the electrode electrodes 22, the metal conductive film 20A remains on the inorganic insulating layer 34 to form the worn metal layer 36B.

藉由以上步驟而製作圖2所示的薄膜電晶體30。 The thin film transistor 30 shown in Fig. 2 was produced by the above steps.

3.變形例 3. Modifications

再者,針對特定實施方式而詳細說明本發明,但本領域技術人員應當明白本發明並不限定於該實施方式,在本發明的範圍內可有其他各種實施方式。 Further, the present invention will be described in detail with reference to the specific embodiments, but those skilled in the art will understand that the invention is not limited to the embodiments, and various other embodiments are possible within the scope of the invention.

例如,亦可在氧化物半導體膜18A成膜後的任一步驟之間,進行將氧化物半導體膜18A(氧化物半導體層18)退火的步驟。藉由退火的熱處理溫度而使氧化物半導體膜18A中的氧擴散,從而可提高光照射時的工作穩定性。但是,在本實施方式的情形時,藉由金屬層28、金屬層36、金屬層46而抑制到達氧化物半導體膜18A的光量,因此可使退火的熱處理溫度低。藉此,獲得可撓性基板12時的材料的選擇範圍廣。 For example, the step of annealing the oxide semiconductor film 18A (the oxide semiconductor layer 18) may be performed between any of the steps after the formation of the oxide semiconductor film 18A. The oxygen in the oxide semiconductor film 18A is diffused by the heat treatment temperature of the annealing, whereby the operational stability at the time of light irradiation can be improved. However, in the case of the present embodiment, the amount of light reaching the oxide semiconductor film 18A is suppressed by the metal layer 28, the metal layer 36, and the metal layer 46, so that the heat treatment temperature for annealing can be made low. Thereby, a wide selection of materials when obtaining the flexible substrate 12 is obtained.

又,在薄膜電晶體10、薄膜電晶體30的製造方法中,使源極電極20、汲極電極22與金屬層28或耗損金屬層36B的構成材料為相同的金屬材料,但亦可使閘極電極14與金屬層28或耗損金屬層36B的構成材料為相同的金屬材料。 Further, in the method of manufacturing the thin film transistor 10 and the thin film transistor 30, the source electrode 20 and the drain electrode 22 are made of the same metal material as the metal layer 28 or the worn metal layer 36B, but the gate may be used. The electrode material of the electrode layer 14 and the metal layer 28 or the worn metal layer 36B is the same metal material.

4.應用 4. Application

並不限定於以上說明的本實施方式的薄膜電晶體10、薄膜電晶體30、薄膜電晶體40的用途,例如適於用於光電裝置(例如液晶顯示裝置、有機電致發光(Electro Luminescence)顯示裝置、無機電致發光顯示裝置等顯示裝置等)的驅動元件、尤其大面積裝置(device)的情形。 The use of the thin film transistor 10, the thin film transistor 30, and the thin film transistor 40 of the present embodiment described above is not limited to the use of, for example, a photovoltaic device (for example, a liquid crystal display device or an organic electroluminescence (Electro Luminescence) display. A driving element of a device, a display device such as an inorganic electroluminescence display device, or the like, in particular, a device of a large area.

進而本實施方式的薄膜電晶體10、薄膜電晶體30、薄膜電晶體40,尤其適於使用樹脂基板的可在低溫製程中製作的裝置,可 較佳地用作各種感測器、微機電系統(Micro Electro Mechanical System)等各種電子裝置的驅動元件(驅動電路)。 Further, the thin film transistor 10, the thin film transistor 30, and the thin film transistor 40 of the present embodiment are particularly suitable for a device which can be fabricated in a low temperature process using a resin substrate. It is preferably used as a driving element (drive circuit) of various electronic devices such as various sensors and micro electro mechanical systems.

5.光電裝置及感測器 5. Photoelectric device and sensor

本實施方式的光電裝置或感測器包括本實施方式的薄膜電晶體10而構成。 The photovoltaic device or the sensor of the present embodiment is configured by including the thin film transistor 10 of the present embodiment.

作為光電裝置的例子,存在顯示裝置(例如液晶顯示裝置、有機電致發光顯示裝置、無機電致發光顯示裝置等)。 As an example of the photovoltaic device, there are a display device (for example, a liquid crystal display device, an organic electroluminescence display device, an inorganic electroluminescence display device, etc.).

作為感測器的例子,較佳為電荷耦合裝置(Charge Coupled Device,CCD)或互補金屬氧化物半導體(Complementary Metal Oxide Semiconductor,CMOS)等影像感測器。 As an example of the sensor, an image sensor such as a Charge Coupled Device (CCD) or a Complementary Metal Oxide Semiconductor (CMOS) is preferable.

以下,作為包括本實施方式的薄膜電晶體10的光電裝置或感測器的代表例,對液晶顯示裝置、有機電致發光顯示裝置進行說明。 Hereinafter, a liquid crystal display device and an organic electroluminescence display device will be described as representative examples of the photovoltaic device or the sensor including the thin film transistor 10 of the present embodiment.

6.液晶顯示裝置 6. Liquid crystal display device

圖8中表示本發明的光電裝置的一實施方式的液晶顯示裝置的一部分的概略剖面圖,圖9表示該液晶顯示裝置的電氣佈線的概略構成圖。 8 is a schematic cross-sectional view showing a part of a liquid crystal display device according to an embodiment of the photovoltaic device of the present invention, and FIG. 9 is a schematic configuration view showing electrical wiring of the liquid crystal display device.

如圖8所示般,本實施方式的液晶顯示裝置100為如下構成,即包括:圖1所示的底部閘極構造且頂部接觸型的薄膜電晶體10;液晶層108,在薄膜電晶體10的由鈍化層(passivation layer)102保護的氧化物半導體層18上被畫素下部電極104及其對向上部電極106夾持;及紅綠藍(Red Green Blue,RGB)彩色 濾光片110,用以對應於各畫素而使各畫素發出不同色的光;且在薄膜電晶體10的基板12側及紅綠藍彩色濾光片110上分別具有偏光板112a、偏光板112b。 As shown in FIG. 8, the liquid crystal display device 100 of the present embodiment is configured to include a bottom gate structure and a top contact type thin film transistor 10 shown in FIG. 1, and a liquid crystal layer 108 in the thin film transistor 10. The oxide semiconductor layer 18 protected by the passivation layer 102 is sandwiched by the pixel lower electrode 104 and its upper electrode 106; and red green blue (RGB) color The filter 110 is configured to emit light of different colors corresponding to each pixel, and has a polarizing plate 112a and a polarizing light on the substrate 12 side of the thin film transistor 10 and the red, green and blue color filter 110, respectively. Board 112b.

又,如圖9所示般,本實施方式的液晶顯示裝置100包括相互平行的多個閘極配線112、及與該閘極配線112交叉的相互平行的資料配線114。此處閘極配線112與資料配線114電氣絕緣。在閘極配線112與資料配線114的交叉部附近具有薄膜電晶體10。 Further, as shown in FIG. 9, the liquid crystal display device 100 of the present embodiment includes a plurality of gate wirings 112 that are parallel to each other, and data wirings 114 that are parallel to each other and intersect with the gate wirings 112. Here, the gate wiring 112 is electrically insulated from the data wiring 114. The thin film transistor 10 is provided in the vicinity of the intersection of the gate wiring 112 and the data wiring 114.

薄膜電晶體10的閘極電極14連接於閘極配線112,薄膜電晶體10的源極電極20連接於資料配線114。又,薄膜電晶體10的汲極電極22經由設置於閘極絕緣層16的接觸孔116(在接觸孔116中埋入有導電體)而連接於畫素下部電極104。該畫素下部電極104與接地的對向上部電極106一同構成電容器118。 The gate electrode 14 of the thin film transistor 10 is connected to the gate wiring 112, and the source electrode 20 of the thin film transistor 10 is connected to the data wiring 114. Further, the gate electrode 22 of the thin film transistor 10 is connected to the pixel lower electrode 104 via a contact hole 116 provided in the gate insulating layer 16 (a conductor is buried in the contact hole 116). The pixel lower electrode 104 and the grounded pair upper electrode 106 constitute a capacitor 118.

該液晶顯示裝置100中,包含波長400nm以上且450nm以下的光的背光反射並從薄膜電晶體10的保護層24的外側向基板12側(薄膜電晶體形成側)照射。 In the liquid crystal display device 100, a backlight including light having a wavelength of 400 nm or more and 450 nm or less is reflected and irradiated from the outside of the protective layer 24 of the thin film transistor 10 to the substrate 12 side (the thin film transistor forming side).

本實施方式的薄膜電晶體10中,朝向氧化物半導體層18側的背光由金屬層28反射,因此可抑制到達氧化物半導體層18的光量。由此,即便氧化物半導體層18包含選自In、Zn、Ga及Sn中的至少1種而不耐受波長400nm以上且450nm以下的光,由於抑制到達氧化物半導體層18的光量,因此亦可確保薄膜電晶體10在光照射時的工作穩定性。因此,液晶顯示裝置100的可靠性 增大。 In the thin film transistor 10 of the present embodiment, the backlight toward the oxide semiconductor layer 18 side is reflected by the metal layer 28, so that the amount of light reaching the oxide semiconductor layer 18 can be suppressed. Therefore, even if the oxide semiconductor layer 18 contains at least one selected from the group consisting of In, Zn, Ga, and Sn and does not withstand light having a wavelength of 400 nm or more and 450 nm or less, since the amount of light reaching the oxide semiconductor layer 18 is suppressed, The operational stability of the thin film transistor 10 upon light irradiation can be ensured. Therefore, the reliability of the liquid crystal display device 100 Increase.

7.有機電致發光顯示裝置 7. Organic electroluminescent display device

圖10中表示本發明的光電裝置的一實施方式的主動矩陣方式的有機電致發光顯示裝置的一部分的概略剖面圖,圖11中表示電氣佈線的概略構成圖。 FIG. 10 is a schematic cross-sectional view showing a part of an active matrix type organic electroluminescence display device according to an embodiment of the photovoltaic device of the present invention, and FIG. 11 is a schematic configuration view showing electrical wiring.

有機電致發光顯示裝置的驅動方式中,有單純矩陣方式與主動矩陣方式這2種。單純矩陣方式具有可低成本製作的優點,但由於逐條選擇掃描線來使畫素發光,因此掃描線數與每條掃描線的發光時間成反比例。因此難以高精細化、大畫面化。主動矩陣方式因針對每個畫素形成電晶體或電容器而製造成本升高,但由於不存在如單純矩陣方式般不增大掃描線數的問題,因此適於高精細化、大畫面化。 Among the driving methods of the organic electroluminescence display device, there are two types of a simple matrix method and an active matrix method. The simple matrix method has the advantage of being inexpensive to manufacture, but since the pixels are selected one by one to cause the pixels to emit light, the number of scanning lines is inversely proportional to the lighting time of each scanning line. Therefore, it is difficult to achieve high definition and large screen. The active matrix method increases the manufacturing cost by forming a transistor or a capacitor for each pixel. However, since there is no problem that the number of scanning lines is not increased as in the simple matrix method, it is suitable for high definition and large screen.

本實施方式的主動矩陣方式的有機電致發光顯示裝置200中,圖1所示的底部閘極構造的薄膜電晶體10設置在基板12上。該基板12例如為可撓性支撐體、且為聚萘二甲酸乙二酯等塑膠薄膜,為了成為絕緣性而在表面具有基板絕緣層202。在該基板12上設置有已圖案化的彩色濾光片層204。在驅動薄膜電晶體部具有閘極電極14,進而閘極絕緣層16設置在閘極電極14上。在閘極絕緣層16的一部分開設有連接孔以進行電連接。在驅動薄膜電晶體部設置有氧化物半導體層18,並在該氧化物半導體層18上設置有源極電極20及汲極電極22。汲極電極22與有機電致發光元件的畫素電極(陽極)206為連續的一體,且利用同一材料、 同一步驟形成。開關薄膜電晶體的汲極電極22與驅動薄膜電晶體藉由連接電極208而利用連接孔電連接。進而,畫素電極部除形成有有機電致發光元件的部分以外整體上由絕緣膜210覆蓋。在畫素電極部上設置有包含發光層的有機層212及陰極214而形成有機電致發光元件部。 In the active matrix type organic electroluminescence display device 200 of the present embodiment, the thin film transistor 10 of the bottom gate structure shown in FIG. 1 is provided on the substrate 12. The substrate 12 is, for example, a flexible support and a plastic film such as polyethylene naphthalate, and has a substrate insulating layer 202 on the surface in order to provide insulation. A patterned color filter layer 204 is disposed on the substrate 12. The gate electrode 14 is provided on the driving thin film transistor portion, and the gate insulating layer 16 is further provided on the gate electrode 14. A connection hole is formed in a portion of the gate insulating layer 16 for electrical connection. An oxide semiconductor layer 18 is provided on the driving thin film transistor portion, and a source electrode 20 and a drain electrode 22 are provided on the oxide semiconductor layer 18. The gate electrode 22 and the pixel electrode (anode) 206 of the organic electroluminescent element are continuously integrated, and the same material is used. The same step is formed. The drain electrode 22 of the switching thin film transistor and the driving thin film transistor are electrically connected by a connection hole by connecting the electrode 208. Further, the pixel electrode portion is entirely covered with the insulating film 210 except for the portion where the organic electroluminescent element is formed. An organic electroluminescence element portion is formed by providing an organic layer 212 including a light-emitting layer and a cathode 214 on the pixel electrode portion.

又,如圖11所示般,本實施方式的有機電致發光顯示裝置200包括相互平行的多個閘極配線220、及與該閘極配線220交叉的相互平行的資料配線222及驅動配線224。此處,閘極配線220與資料配線222、驅動配線224電氣絕緣。開關用薄膜電晶體10b的閘極電極14連接於閘極配線220,開關用薄膜電晶體10b的源極電極20連接於資料配線222。又,開關用薄膜電晶體10b的汲極電極22連接於驅動用薄膜電晶體10a的閘極電極14,並且藉由使用電容器226而將驅動用薄膜電晶體10a保持於導通(on)狀態。驅動用薄膜電晶體10a的源極電極20連接於驅動配線224,且汲極電極22連接於有機層212。 Further, as shown in FIG. 11, the organic electroluminescence display device 200 of the present embodiment includes a plurality of gate wirings 220 that are parallel to each other, and mutually parallel data wirings 222 and driving wirings 224 that intersect the gate wirings 220. . Here, the gate wiring 220 is electrically insulated from the data wiring 222 and the driving wiring 224. The gate electrode 14 of the thin film transistor 10b for switching is connected to the gate wiring 220, and the source electrode 20 of the thin film transistor 10b for switching is connected to the data wiring 222. Further, the gate electrode 22 of the switching thin film transistor 10b is connected to the gate electrode 14 of the driving thin film transistor 10a, and the driving thin film transistor 10a is held in an on state by using the capacitor 226. The source electrode 20 of the driving thin film transistor 10a is connected to the driving wiring 224, and the drain electrode 22 is connected to the organic layer 212.

該有機電致發光顯示裝置200設為來自發光層的光從基板12側射出的底部發光型,包含400nm以上且450nm以下的波長光的光從薄膜電晶體10的保護層24的外側(基板12的相反側)的發光層向氧化物半導體層18側照射。 The organic electroluminescence display device 200 is a bottom emission type in which light from the light-emitting layer is emitted from the substrate 12 side, and light having wavelengths of 400 nm or more and 450 nm or less is emitted from the outside of the protective layer 24 of the thin film transistor 10 (substrate 12) The light-emitting layer on the opposite side of the light is irradiated toward the side of the oxide semiconductor layer 18.

本實施方式的薄膜電晶體10中,朝向氧化物半導體層18側的光由金屬層28反射,因此可抑制到達氧化物半導體層18的光量。由此,即便氧化物半導體層18包含選自In、Zn、Ga及Sn中 的至少1種而不耐受波長400nm以上且450nm以下的光,由於抑制到達氧化物半導體層18的光量,因此亦可確保薄膜電晶體10在光照射時的工作穩定性。因此,有機電致發光顯示裝置200的可靠性增大。 In the thin film transistor 10 of the present embodiment, the light toward the oxide semiconductor layer 18 side is reflected by the metal layer 28, so that the amount of light reaching the oxide semiconductor layer 18 can be suppressed. Thus, even the oxide semiconductor layer 18 is selected from the group consisting of In, Zn, Ga, and Sn. At least one of the light which does not withstand the wavelength of 400 nm or more and 450 nm or less can suppress the amount of light reaching the oxide semiconductor layer 18, and therefore can ensure the operational stability of the thin film transistor 10 at the time of light irradiation. Therefore, the reliability of the organic electroluminescence display device 200 is increased.

[實施例] [Examples]

以下對實施例進行說明,但本發明不受該等實施例任何限定。 The examples are described below, but the invention is not limited by the examples.

(實施例1) (Example 1)

實施例1中,製作與圖1所示的薄膜電晶體10為同類型的薄膜電晶體。 In the first embodiment, a thin film transistor of the same type as the thin film transistor 10 shown in Fig. 1 was produced.

具體而言,在實施例1的薄膜電晶體的製作中,首先準備液晶顯示器用玻璃基板,並將其加以清洗(超音波清洗:鹼性清洗液、沖洗(rinse)、乾燥臭氧處理)。其次利用直流(direct current,DC)濺鍍而形成約100nm的Mo-Nb膜來作為閘極電極用的導電膜。在成膜後,將導電膜圖案化而形成閘極電極。該圖案化按照如下順序進行,即利用旋塗塗佈正型光阻劑,並進行預烘烤(prebake)(90℃:熱板(hot plate)/1min)、曝光(約100mJ/cm2)、顯影、後烘烤(post bake)(120℃:熱板/2min)、蝕刻(市售蝕刻液:磷酸+硝酸+醋酸)、清洗、乾燥。 Specifically, in the production of the thin film transistor of Example 1, first, a glass substrate for a liquid crystal display is prepared and cleaned (ultrasonic cleaning: alkaline cleaning solution, rinse, drying) Ozone treatment). Next, a direct current (DC) sputtering was used to form a Mo-Nb film of about 100 nm as a conductive film for a gate electrode. After the film formation, the conductive film is patterned to form a gate electrode. The patterning is carried out in the following order, that is, the positive type photoresist is applied by spin coating, and prebake (90 ° C: hot plate / 1 min), exposure (about 100 mJ / cm 2 ) is performed. , development, post bake (120 ° C: hot plate / 2 min), etching (commercially available etching solution: phosphoric acid + nitric acid + acetic acid), washing, drying.

其次,形成SiO2膜作為閘極絕緣層用的絕緣膜,形成InGaZnO4(雖為結晶狀態下的組成表述,但實施例中為非晶質狀態)膜作為氧化物半導體層用的氧化物半導體膜,且形成SiO2膜 作為無機絕緣層用的絕緣膜。 Next, an SiO 2 film is formed as an insulating film for a gate insulating layer, and InGaZnO 4 (an amorphous state in the embodiment, but an amorphous state in the embodiment) is formed as an oxide semiconductor for an oxide semiconductor layer. A film is formed, and an SiO 2 film is formed as an insulating film for the inorganic insulating layer.

閘極絕緣層用的絕緣膜的成膜,藉由設置成膜溫度為350度且設置成膜環境氣體為SiH4與N2O的混合氣體的電漿化學氣相沈積而進行,使膜的厚度為約100nm。 The film formation of the insulating film for the gate insulating layer is performed by plasma chemical vapor deposition in which a film forming temperature is 350 degrees and a film atmosphere is a mixed gas of SiH 4 and N 2 O. The thickness is about 100 nm.

氧化物半導體層用的氧化物半導體膜的成膜,藉由設置成膜溫度為室溫且設置成膜環境氣體為Ar與O2的混合氣體的直流濺鍍而進行,使膜的厚度為約50nm。 The film formation of the oxide semiconductor film for the oxide semiconductor layer is performed by DC sputtering in which a film formation temperature is set to a room temperature and a film atmosphere is a mixed gas of Ar and O 2 so that the thickness of the film is about 50nm.

無機絕緣層用的絕緣膜的成膜,藉由設置成膜溫度為250度且設置成膜環境氣體為SiH4與N2O的混合氣體的電漿化學氣相沈積而進行,使膜的厚度為約100nm。 The film formation of the insulating film for the inorganic insulating layer is performed by plasma chemical vapor deposition in which a film forming temperature of 250 ° and a film atmosphere is a mixed gas of SiH 4 and N 2 O, and the film thickness is made. It is about 100 nm.

其次,利用光微影進行抗蝕劑圖案化,然後利用CHF3氣體環境的乾式蝕刻將無機絕緣層用的絕緣膜圖案化。繼而,利用O2電漿將抗蝕劑除去。藉此,自絕緣膜形成無機絕緣層。 Next, resist patterning is performed by photolithography, and then the insulating film for the inorganic insulating layer is patterned by dry etching in a CHF 3 gas atmosphere. The resist is then removed using O 2 plasma. Thereby, an inorganic insulating layer is formed from the insulating film.

其次,利用光微影進行抗蝕劑圖案化,然後利用使用氧化銦錫蝕刻劑(etchant)的濕式蝕刻將氧化物半導體層用的氧化物半導體膜圖案化。繼而,利用O2電漿將抗蝕劑除去。藉此,自氧化物半導體膜形成氧化物半導體層。 Next, resist patterning is performed by photolithography, and then the oxide semiconductor film for the oxide semiconductor layer is patterned by wet etching using an indium tin oxide etchant. The resist is then removed using O 2 plasma. Thereby, an oxide semiconductor layer is formed from the oxide semiconductor film.

其次,利用光微影進行抗蝕劑圖案化,然後利用CHF3氣體環境的乾式蝕刻將閘極絕緣層用的絕緣膜圖案化。繼而,利用O2電漿將抗蝕劑除去。藉此,自絕緣膜形成閘極絕緣層。 Next, resist patterning is performed by photolithography, and then the insulating film for the gate insulating layer is patterned by dry etching in a CHF 3 gas atmosphere. The resist is then removed using O 2 plasma. Thereby, a gate insulating layer is formed from the insulating film.

其次,利用直流濺鍍形成約100nm的Mo膜作為源極-汲極電極用的金屬導電膜。成膜後,將該金屬導電膜圖案化而形 成源極-汲極電極,並且形成金屬層。該圖案化按照以下順序進行,即利用旋塗塗佈正型光阻劑,並進行預烘烤(90℃:熱板/1min)、曝光(約100mJ/cm2)、顯影、後烘烤(120℃:熱板/2min)、蝕刻(市售蝕刻液:磷酸+硝酸+醋酸)、清洗、乾燥。 Next, a Mo film of about 100 nm was formed by DC sputtering as a metal conductive film for the source-drain electrode. After the film formation, the metal conductive film is patterned to form a source-drain electrode, and a metal layer is formed. The patterning is performed in the following order, that is, the positive type photoresist is applied by spin coating, and prebaking (90 ° C: hot plate / 1 min), exposure (about 100 mJ / cm 2 ), development, post-baking ( 120 ° C: hot plate / 2 min), etching (commercially available etching solution: phosphoric acid + nitric acid + acetic acid), washing, drying.

藉由以上步驟而製作出實施例1的薄膜電晶體。 The thin film transistor of Example 1 was produced by the above procedure.

(實施例2) (Example 2)

實施例2中,製作與圖2所示的薄膜電晶體30為同類型的薄膜電晶體。 In the second embodiment, a thin film transistor of the same type as the thin film transistor 30 shown in Fig. 2 was produced.

具體而言,利用與實施例1相同的方法形成閘極電極、閘極絕緣層、氧化物半導體層、無機絕緣層(的一部分)、源極-汲極電極、及金屬層(與源極-汲極電極同時形成的耗損金屬層)。 Specifically, the gate electrode, the gate insulating layer, the oxide semiconductor layer, the inorganic insulating layer (part of), the source-drain electrode, and the metal layer (with the source) are formed in the same manner as in the first embodiment. The drain metal electrode simultaneously forms a depleted metal layer).

其中,實施例2中,在無機絕緣膜圖案化之前,預先藉由直流濺鍍而在無機絕緣層上形成Mo膜作為金屬膜,在無機絕緣膜的圖案化中,金屬膜亦一同圖案化。藉此,形成無機絕緣層的一部分與金屬層(反射金屬層)。然後,在該金屬層上及氧化物半導體層上,進而形成絕緣膜(SiO2)並進行圖案化而形成無機絕緣層。源極-汲極電極及耗損金屬層的形成是在完全形成該無機絕緣層之後進行。 In the second embodiment, before the inorganic insulating film is patterned, a Mo film is formed as a metal film on the inorganic insulating layer by DC sputtering in advance, and the metal film is also patterned together in the patterning of the inorganic insulating film. Thereby, a part of the inorganic insulating layer and the metal layer (reflective metal layer) are formed. Then, an insulating film (SiO 2 ) is further formed on the metal layer and on the oxide semiconductor layer, and patterned to form an inorganic insulating layer. The formation of the source-drain electrodes and the worn metal layer is performed after the inorganic insulating layer is completely formed.

藉由以上步驟而製作出實施例2的薄膜電晶體。 The thin film transistor of Example 2 was produced by the above procedure.

(比較例1) (Comparative Example 1)

比較例1中,在形成源極-汲極電極時,除未形成耗損金屬層以外,利用與圖1所示的薄膜電晶體10相同的方法製作薄膜電晶 體。 In Comparative Example 1, when a source-drain electrode was formed, a thin film electric crystal was produced by the same method as the thin film transistor 10 shown in Fig. 1 except that a lossy metal layer was not formed. body.

(評估) (assessment)

對所製作的實施例1、實施例2及比較例1的薄膜電晶體的光照射時的工作穩定性(△Vth)進行評估。再者,薄膜電晶體的元件尺寸分別為通道長180μ、通道寬1mm。 The operational stability (ΔVth) at the time of light irradiation of the produced thin film transistors of Example 1, Example 2, and Comparative Example 1 was evaluated. Furthermore, the element dimensions of the thin film transistor are 180 μ channel length and 1 mm channel width, respectively.

各薄膜電晶體在黑暗環境下在大氣中放置1小時來排除薄膜電晶體保管環境下的室內光的影響。然後,在對閘極電極、源極-汲極電極間未施加電壓的狀態下從保護層側對各薄膜電晶體照射光(利用分光而使氙氣燈(xenon lamp)為10μW/cm2)。在照射時間為10分鐘後的時序對閘極電極、源極-汲極電極間施加電壓來測定Vg-Id特性(此時,持續照射光,測定波長在400nm~500nm之間且間隔20nm)。藉此,自預先未照射光時的Vg-Id特性計算出Vth,並自此計算出每個波長下的△Vth。 Each of the thin film transistors was placed in the atmosphere for 1 hour in a dark environment to eliminate the influence of room light in the storage environment of the thin film transistor. Then, each thin film transistor was irradiated with light from the protective layer side in a state where no voltage was applied between the gate electrode and the source-drain electrode (the xenon lamp was 10 μW/cm 2 by splitting). A voltage was applied between the gate electrode and the source-drain electrode at a timing of 10 minutes after the irradiation time to measure the Vg-Id characteristic (in this case, the light was continuously irradiated, and the measurement wavelength was between 400 nm and 500 nm and the interval was 20 nm). Thereby, Vth is calculated from the Vg-Id characteristic when the light is not irradiated in advance, and ΔVth at each wavelength is calculated therefrom.

再者,為了在每次測定中排除光照射時的影響,每次計測(例如500nm)結束時,在黑暗環境下放置至重現未照射光時的Vg-Id特性。又,在Vg-Id特性的測定中,使用半導體參數分析器(parameter analyzer)(安捷倫科技(Agilent Technologies)公司製造)。 Further, in order to eliminate the influence of light irradiation in each measurement, the Vg-Id characteristic was released in a dark environment until the unexposed light was reproduced, at the end of each measurement (for example, 500 nm). Further, in the measurement of the Vg-Id characteristics, a semiconductor parameter analyzer (manufactured by Agilent Technologies, Inc.) was used.

將每個波長下的△Vth的計算結果示於表1及圖12。 The calculation results of ΔVth at each wavelength are shown in Table 1 and FIG.

自表1及圖12所示的結果得知,在比較例1中,相對於照射波長400nm~450nm的光而|△Vth|超過1V,薄膜電晶體工作不穩定。尤其得知,相對於照射波長400nm~420nm的光而|△Vth|飛躍性地變大(變差),薄膜電晶體工作更不穩定。 As is apparent from the results shown in Table 1 and FIG. 12, in Comparative Example 1, the film transistor operation was unstable with respect to the light having an irradiation wavelength of 400 nm to 450 nm and |ΔVth| exceeding 1 V. In particular, it is known that |ΔVth| is greatly increased (deteriorated) with respect to light having an irradiation wavelength of 400 nm to 420 nm, and the operation of the thin film transistor is more unstable.

相對於此,得知在實施例1及實施例2中,即便照射波長400nm~450nm的任一波長的光,|△Vth|均低於1V,從而確保薄膜電晶體的工作穩定性。尤其得知,即便對於照射波長400nm~420nm的光,|△Vth|亦不飛躍性地變大,從而進一步確保薄膜電晶體的工作穩定性。 On the other hand, in Example 1 and Example 2, even if light of any wavelength of 400 nm to 450 nm was irradiated, |ΔVth| was less than 1 V, and the operational stability of the thin film transistor was ensured. In particular, even when light having a wavelength of 400 nm to 420 nm is irradiated, |ΔVth| is not drastically increased, and the operational stability of the thin film transistor is further ensured.

10‧‧‧薄膜電晶體 10‧‧‧film transistor

12‧‧‧基板 12‧‧‧Substrate

14‧‧‧閘極電極 14‧‧‧ gate electrode

16‧‧‧閘極絕緣層 16‧‧‧ gate insulation

18‧‧‧氧化物半導體層 18‧‧‧Oxide semiconductor layer

20‧‧‧源極電極 20‧‧‧Source electrode

22‧‧‧汲極電極 22‧‧‧汲electrode

24‧‧‧保護層 24‧‧‧Protective layer

26‧‧‧無機絕緣層 26‧‧‧Inorganic insulation

28‧‧‧金屬層 28‧‧‧metal layer

Claims (11)

一種氧化物半導體元件,其包括:電極,由金屬材料構成;氧化物半導體層,包含選自In、Zn、Ga及Sn中的至少1種;以及保護層,積層在上述氧化物半導體層上,且上述保護層包含無機絕緣層、及由與上述電極相同的金屬材料構成的金屬層;並且上述金屬層為多層;上述多層的金屬層包括:耗損金屬層,配置在上述保護層的頂部;以及反射金屬層,配置在上述無機絕緣層的內部,對波長400nm以上且450nm以下的光的反射率較上述耗損金屬層高。 An oxide semiconductor device comprising: an electrode composed of a metal material; an oxide semiconductor layer comprising at least one selected from the group consisting of In, Zn, Ga, and Sn; and a protective layer laminated on the oxide semiconductor layer And the protective layer comprises an inorganic insulating layer and a metal layer composed of the same metal material as the above electrode; and the metal layer is a plurality of layers; the plurality of metal layers comprise: a lossy metal layer disposed on top of the protective layer; The reflective metal layer is disposed inside the inorganic insulating layer, and has a higher reflectance for light having a wavelength of 400 nm or more and 450 nm or less than the worn metal layer. 如申請專利範圍第1項所述的氧化物半導體元件,其中上述金屬層的總厚度為50nm以上。 The oxide semiconductor device according to claim 1, wherein the total thickness of the metal layer is 50 nm or more. 如申請專利範圍第1項所述的氧化物半導體元件,其中上述電極為夾持上述保護層而分別積層在上述氧化物半導體層且可經由上述氧化物半導體層而相互導通的源極電極及汲極電極,在上述氧化物半導體層的配置上述保護層的一側的相反側包含隔著閘極絕緣層而配置的閘極電極,上述金屬層的至少一部分由與上述源極電極及上述汲極電極相同的金屬材料構成,且配置在上述保護層的頂部。 The oxide semiconductor device according to the first aspect of the invention, wherein the electrode is a source electrode and a germanium which are laminated on the oxide semiconductor layer and can be electrically connected to each other via the oxide semiconductor layer. a pole electrode including a gate electrode disposed via a gate insulating layer on a side opposite to a side of the oxide semiconductor layer on which the protective layer is disposed, wherein at least a portion of the metal layer is formed by the source electrode and the drain electrode The electrodes are made of the same metal material and are disposed on top of the above protective layer. 如申請專利範圍第2項所述的氧化物半導體元件,其中上 述電極為夾、持上述保護層而分別積層在上述氧化物半導體層且可經由上述氧化物半導體層而相互導通的源極電極及汲極電極,在上述氧化物半導體層的配置上述保護層的一側的相反側包含隔著閘極絕緣層而配置的閘極電極,上述金屬層的至少一部分由與上述源極電極及上述汲極電極相同的金屬材料構成,且配置在上述保護層的頂部。 An oxide semiconductor device according to claim 2, wherein The electrode is a source electrode and a drain electrode which are laminated on the oxide semiconductor layer and are electrically connected to each other via the oxide semiconductor layer, and the protective layer is disposed on the oxide semiconductor layer. The opposite side of the one side includes a gate electrode disposed via a gate insulating layer, and at least a portion of the metal layer is made of the same metal material as the source electrode and the gate electrode, and is disposed on top of the protective layer . 如申請專利範圍第3項所述的氧化物半導體元件,其中上述金屬層由與上述閘極電極相同的金屬材料構成。 The oxide semiconductor device according to claim 3, wherein the metal layer is made of the same metal material as the gate electrode. 如申請專利範圍第4項所述的氧化物半導體元件,其中上述金屬層由與上述閘極電極相同的金屬材料構成。 The oxide semiconductor device according to claim 4, wherein the metal layer is made of the same metal material as the gate electrode. 如申請專利範圍第1項所述的氧化物半導體元件,其中上述無機絕緣層包含上述金屬層的金屬材料。 The oxide semiconductor device according to claim 1, wherein the inorganic insulating layer comprises a metal material of the metal layer. 一種氧化物半導體元件的製造方法,包括:形成氧化物半導體層的步驟,上述氧化物半導體層包含選自In、Zn、Ga及Sn中的至少1種;形成電極的步驟,上述電極由金屬材料構成;以及形成保護層的步驟,上述保護層積層在上述氧化物半導體層上,且上述保護層包含無機絕緣層、及由與上述電極相同的金屬材料構成的金屬層。 A method of producing an oxide semiconductor device, comprising: forming an oxide semiconductor layer, wherein the oxide semiconductor layer comprises at least one selected from the group consisting of In, Zn, Ga, and Sn; and the step of forming an electrode, wherein the electrode is made of a metal material And a step of forming a protective layer, wherein the protective layer is laminated on the oxide semiconductor layer, and the protective layer comprises an inorganic insulating layer and a metal layer made of the same metal material as the electrode. 如申請專利範圍第8項所述的氧化物半導體元件的製造方法,其中形成上述電極的步驟包括:在上述無機絕緣層及上述氧化物半導體層上形成金屬導電膜的步驟;以及將上述金屬導電膜 圖案化而形成源極電極及汲極電極的步驟,並且在形成上述保護層的步驟中的形成上述金屬層的步驟中,在形成上述電極的步驟中,在將上述金屬導電膜圖案化時形成上述源極電極及上述汲極電極,並且在上述無機絕緣層殘留上述金屬導電膜來形成上述金屬層。 The method for producing an oxide semiconductor device according to claim 8, wherein the step of forming the electrode includes: forming a metal conductive film on the inorganic insulating layer and the oxide semiconductor layer; and conducting the metal conductive membrane a step of patterning to form a source electrode and a drain electrode, and in the step of forming the metal layer in the step of forming the protective layer, in the step of forming the electrode, forming the metal conductive film The source electrode and the drain electrode are formed of the metal conductive film in the inorganic insulating layer to form the metal layer. 一種顯示裝置,包括如申請專利範圍第1項至第7項中任一項所述的氧化物半導體元件。 A display device comprising the oxide semiconductor device according to any one of claims 1 to 7. 一種影像感測器,包括如申請專利範圍第1項至第7項中任一項所述的氧化物半導體元件。 An image sensor comprising the oxide semiconductor device according to any one of claims 1 to 7.
TW102142372A 2012-11-28 2013-11-21 Oxide semiconductor element, method for manufacturing oxide semiconductor element, display device and image sensor TWI594432B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012260201A JP6121149B2 (en) 2012-11-28 2012-11-28 Oxide semiconductor element, manufacturing method of oxide semiconductor element, display device, and image sensor

Publications (2)

Publication Number Publication Date
TW201428974A TW201428974A (en) 2014-07-16
TWI594432B true TWI594432B (en) 2017-08-01

Family

ID=50827697

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102142372A TWI594432B (en) 2012-11-28 2013-11-21 Oxide semiconductor element, method for manufacturing oxide semiconductor element, display device and image sensor

Country Status (4)

Country Link
JP (1) JP6121149B2 (en)
KR (1) KR101713461B1 (en)
TW (1) TWI594432B (en)
WO (1) WO2014084051A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI578544B (en) * 2014-12-02 2017-04-11 鴻海精密工業股份有限公司 Thin film transistor and display array substrate utilizing the thin film transistor
JP6878820B2 (en) * 2015-11-17 2021-06-02 株式会社リコー Field-effect transistor, display element, display device, system, and method of manufacturing field-effect transistor
JP6811096B2 (en) * 2017-01-12 2021-01-13 株式会社Joled Semiconductor devices, display devices and electronic devices
JP7153497B2 (en) * 2018-08-08 2022-10-14 株式会社ジャパンディスプレイ electronic circuit
CN112038288B (en) * 2020-11-04 2021-02-02 成都中电熊猫显示科技有限公司 Manufacturing method of array substrate and array substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201246389A (en) * 2009-12-04 2012-11-16 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0691105B2 (en) * 1985-02-15 1994-11-14 株式会社日立製作所 Method of manufacturing thin film transistor
JP2769617B2 (en) * 1987-08-26 1998-06-25 セイコーエプソン株式会社 Manufacturing method of liquid crystal display device
JPH04111322A (en) * 1990-08-30 1992-04-13 Stanley Electric Co Ltd Manufacture of thin film transistor
JPH05251705A (en) * 1992-03-04 1993-09-28 Fuji Xerox Co Ltd Thin-film transistor
JPH06326310A (en) * 1993-05-14 1994-11-25 Toshiba Corp Active matrix type display device
JPH06338489A (en) * 1993-05-28 1994-12-06 Fuji Xerox Co Ltd Method of manufacturing metal film
JP3163844B2 (en) * 1993-06-07 2001-05-08 日本電気株式会社 Method of manufacturing inverted staggered thin film field effect transistor
JPH08330591A (en) * 1995-05-30 1996-12-13 Nec Corp Thin film transistor
JP2009088179A (en) * 2007-09-28 2009-04-23 Bridgestone Corp Thin-film transistor and method of manufacturing the same
CN102047396B (en) * 2008-08-04 2013-01-09 松下电器产业株式会社 Flexible semiconductor device and method for manufacturing same
KR101516415B1 (en) * 2008-09-04 2015-05-04 삼성디스플레이 주식회사 Thin film transistor substrate, method of manufacturing the same, and display apparatus having the same
KR20110037220A (en) * 2009-10-06 2011-04-13 삼성모바일디스플레이주식회사 Thin film transistor, method of manufacturing the thin film transistor and organic light emitting display device having the thin film transistor
WO2011062043A1 (en) * 2009-11-20 2011-05-26 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
KR20110066370A (en) * 2009-12-11 2011-06-17 한국전자통신연구원 Oxide thin film transistor and method for manufacturing the same
CN104867984B (en) * 2009-12-28 2018-11-06 株式会社半导体能源研究所 The method for manufacturing semiconductor device
JP5743407B2 (en) * 2010-01-15 2015-07-01 キヤノン株式会社 Transistor driving method and display device including transistor driven by the method
US9960278B2 (en) * 2011-04-06 2018-05-01 Yuhei Sato Manufacturing method of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201246389A (en) * 2009-12-04 2012-11-16 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
WO2014084051A1 (en) 2014-06-05
JP6121149B2 (en) 2017-04-26
KR20150074135A (en) 2015-07-01
TW201428974A (en) 2014-07-16
KR101713461B1 (en) 2017-03-22
JP2014107453A (en) 2014-06-09

Similar Documents

Publication Publication Date Title
KR101891841B1 (en) Thin film transistor, method for manufacturing same, and image display device provided with thin film transistor
JP5052693B1 (en) Thin film transistor and manufacturing method thereof, display device, image sensor, X-ray sensor, and X-ray digital imaging device
TWI776206B (en) Light-emitting device
JP4982620B1 (en) Manufacturing method of field effect transistor, field effect transistor, display device, image sensor, and X-ray sensor
JP4864546B2 (en) Organic EL display device and manufacturing method thereof
EP3242341A1 (en) Array substrate and manufacturing method therefor, display panel and display device
JP5679933B2 (en) Thin film transistor and manufacturing method thereof, display device, image sensor, X-ray sensor, and X-ray digital imaging device
KR101528992B1 (en) Field effect transistor, display device, sensor, and method for producing field effect transistor
TWI594432B (en) Oxide semiconductor element, method for manufacturing oxide semiconductor element, display device and image sensor
US8421084B2 (en) Organic light emitting display and manufacturing method thereof
JP2011243745A (en) Method of manufacturing thin film transistor, thin film transistor, image sensor, x-ray sensor, and x-ray digital photographing device
JP5869110B2 (en) Thin film transistor, display device, image sensor and X-ray sensor
JP6260326B2 (en) Thin film transistor device and manufacturing method thereof
TWI509812B (en) Field effect transistor, display device and sensor
JP6041796B2 (en) Oxide semiconductor element, manufacturing method of oxide semiconductor element, display device, image sensor, and X-ray sensor
WO2014103323A1 (en) Thin film field effect transistor