TWI581308B - 圖案化基板之方法 - Google Patents

圖案化基板之方法 Download PDF

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TWI581308B
TWI581308B TW104142321A TW104142321A TWI581308B TW I581308 B TWI581308 B TW I581308B TW 104142321 A TW104142321 A TW 104142321A TW 104142321 A TW104142321 A TW 104142321A TW I581308 B TWI581308 B TW I581308B
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hard mask
layer
mask layer
substrate
forming
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TW201709274A (zh
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楊宗潾
陳華豐
陳桂順
謝旻諺
李勃學
傅士奇
龍元祥
蔡晏佐
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台灣積體電路製造股份有限公司
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Description

圖案化基板之方法
本發明係有關於使用微影技術製程形成積體電路之圖案或裝置，特別係有關於產生用於進階積體電路製程之島狀小型硬遮罩。
半導體積體電路(integrated circuit；IC)行業已經歷指數式增長。積體電路材料及設計中之技術進步已產生多個積體電路之世代，其中每一世代比前一世代具有更小且更複雜之電路。在積體電路進化之過程中，功能密度(亦即，每晶片面積之互連裝置之數目)已通常增加，而幾何尺寸(亦即，可使用製造工藝產生之最小元件(或接線))已減小。此按比例縮小製程通常藉由增加生產效率且降低相關成本來提供益處。此按比例縮小亦已增加處理及製造積體電路之複雜性，為了此等發展得以實現，積體電路的製程及製造需要類似的開發。
例如，在積體電路製造中，微影技術為用於將積體電路設計傳遞至半導體基板之經常使用的技術。典型的微影技術製程包括在基板之上形成硬遮罩層，圖案化此硬遮 罩層以形成硬遮罩，且以硬遮罩作為蝕刻遮罩蝕刻基板。圖案化硬遮罩層典型地包括在硬遮罩層之上塗覆抗蝕劑(或光阻劑)，將抗蝕劑暴露於諸如深紫外線(deep ultraviolet；DUV)或極紫外線(extreme ultraviolet；EUV)之輻射，且將抗蝕劑顯影且部分地剝離以在硬遮罩層之上留下圖案化抗蝕劑。然後，將圖案化抗蝕劑用於後續蝕刻硬遮罩層以形成硬遮罩。隨著裝置繼續小型化，常常需要生產島狀小型硬遮罩。
本發明之一實施例提供一種圖案化一基板之方法，方法包含以下步驟：在基板之上形成一硬遮罩層；在硬遮罩層之上形成一第一材料層；在第一材料層中形成一溝槽；以通過溝槽之一離子束處理硬遮罩層，其中硬遮罩層之一經處理部分之一蝕刻速率相對於一蝕刻製程降低，而硬遮罩層之一未處理部分之一蝕刻速率相對於蝕刻製程保持大體上不變；在處理硬遮罩層之步驟之後，移除第一材料層；以蝕刻製程移除硬遮罩層之未處理部分，從而在基板之上形成一硬遮罩；以及以硬遮罩作為一蝕刻遮罩蝕刻基板。
本發明之另一實施例提供一種圖案化一基板之方法，方法包含以下步驟：在基板之上形成一硬遮罩層，其中硬遮罩層包括非晶矽；在硬遮罩層之上形成一第一材料層；在第一材料層中形成一溝槽，溝槽暴露硬遮罩層之一第一部分；以一離子束處理第一部分，從而降低相對於一蝕刻 劑之第一部分之一蝕刻速率，而硬遮罩層之一未處理部分之一蝕刻速率相對於蝕刻劑保持大體上不變，其中離子束為以下各者中之一者：一硼(B)離子束及一氟化硼(BF2)離子束；在處理第一部分之後，移除第一材料層；以蝕刻劑移除硬遮罩層之未處理部分，從而在基板之上形成一硬遮罩；以及以硬遮罩作為一蝕刻遮罩蝕刻基板。
本發明之又一實施例提供一種圖案化一基板之方法，方法包含以下步驟：在基板之上形成一硬遮罩層，其中硬遮罩層包括非晶矽；在硬遮罩層之上形成一第一材料層；在第一材料層中形成一溝槽，溝槽暴露硬遮罩層之一第一部分；以一離子束處理第一部分，從而降低相對於一蝕刻劑之第一部分之一蝕刻速率，而硬遮罩層之一未處理部分之一蝕刻速率相對於蝕刻劑保持大體上不變，其中離子束為以下各者中之一者：一B離子束及一BF2離子束；且其中蝕刻劑包括以下兩者中之一者：氫氧化銨及氫氧化四甲銨；在處理第一部分之後，移除第一材料層；以蝕刻劑移除硬遮罩層之未處理部分，從而在基板之上形成一硬遮罩；以及用作為一蝕刻遮罩之硬遮罩蝕刻基板。
100‧‧‧方法
102、104、106、108、110、112、114、116、118、120、122‧‧‧操作
200‧‧‧裝置
202‧‧‧基板
202A‧‧‧部分
204‧‧‧硬遮罩層
204A‧‧‧經處理部分
204A'‧‧‧硬遮罩
204B‧‧‧未處理部分
206‧‧‧第一材料層
206'‧‧‧圖案化第一材料層
208‧‧‧中間層
210‧‧‧抗蝕劑層
210'‧‧‧抗蝕劑圖案
212‧‧‧溝槽/抗蝕劑溝槽
214‧‧‧溝槽
216‧‧‧離子束
搭配相對應的圖示閱讀下列詳細的敘述，可以更清晰地瞭解本揭示案。應該注意的是，根據在工業中的標準慣例，各種特徵不必按比例繪製。事實上，為了論述之清楚起見，可任意地增加或減小各種特徵之尺寸。
第1圖為用於實施本案之一或更多個實施例之在基板上形成目標圖案或裝置的方法之流程圖；以及第2A圖、第2B圖、第2C圖、第2D圖、第2E圖、第2F圖、第2G圖、第2H圖、第2I圖，及第2J圖為根據一實施例之形成根據第1圖之方法的目標裝置之剖視圖。
以下揭示內容提供用於實施所提供之標的之不同特徵的許多不同實施例，或實例。在下文中描述元件及佈置之特定實例以簡化本案。當然，此等特定實例僅為實例且不意欲作為限制。例如，在下文描述中之第一特徵位於或在第二特徵之上的結構可包括其中第一特徵及第二特徵直接接觸形成的實施例，且亦可包括其中額外特徵可形成在第一特徵與第二特徵之間，以使得第一特徵及第二特徵可不直接接觸之實施例。此外，本案可在各種實例中重複元件符號及/或字母。此重複係為了簡單且清晰之目的，且其本身不指定所論述之各種實施例及/或配置之間的關係。
此外，諸如「在……之下(beneath)」、「在……下(below)」、「下部(lower)」、「在……上(above)」、「上部(upper)」等等之空間相對術語可在本文中為便於描述而使用，以描述一元件或特徵的相對於如附圖中所示之另一元件或特徵之關係。空間相對術語意欲包含除附圖中所示之定向之外的在使用或操作中之裝置之不同定向。裝置可經 另外地定向(旋轉90度或以其他定向)且本文中使用之空間相對描述語言可同樣相應地解釋。
本案通常係關於使用微影技術製程形成積體電路(integrated circuit；IC)之圖案或裝置。更特定言之，本案係關於產生用於進階積體電路製程之島狀小型硬遮罩。
第1圖繪示根據本案之各種態樣的用於形成目標圖案或裝置之方法100之流程圖。可在方法100之前、期間及之後提供額外操作；對於本方法之額外實施例，可替換、消除，或移動一些所述之操作。方法100僅為實例，且不意欲限制本案超出申請專利範圍中所明確敘述之內容。方法100係結合第2A圖至第2J圖描述如下，此第2A圖至第2J圖繪示在製程之各個階段之裝置200的示意剖視圖。裝置200可為積體電路，或積體電路之一部分，此積體電路可包含靜態隨機存取記憶體(static random access memory；SRAM)及/或其他邏輯電路；被動元件，諸如電阻器、電容器，及電感器；及主動元件，諸如P型場效電晶體(p-type field effect transistors；PFET)、N型場效電晶體(n-type FET；NFET)、金屬氧化物半導體場效電晶體(metal-oxide semiconductor field effect transistors；MOSFET)、互補金屬氧化物半導體(complementary metal-oxide semiconductor；CMOS)電晶體、雙極電晶體、高壓電晶體、高頻電晶體、其他記憶體單元，及上述各者之組合。裝置200可包括三維裝置及多閘極裝置，諸如雙閘極場效電晶體、鰭式場效電晶體(FinFET)、三閘極場效電晶體、Ω場 效電晶體(omega FET)；及環繞閘極(gate-all-around；GAA)裝置，包括垂直環繞閘極裝置及水平環繞閘極裝置。
在操作102處，方法100(第1圖)提供如第2A圖中所示之基板202。參看第2A圖，在各種實施例中，基板202包括一或更多個材料層。在實施例中，基板202為半導體基板(例如，晶元)。在一實施例中，基板202包括結晶結構之矽。在替代實施例中，基板202包括其他元素半導體，諸如鍺；化合物半導體，諸如碳化矽、砷化鎵、砷化銦，或磷化銦；或合金半導體，諸如碳化矽鍺、磷化鎵砷，或磷化鎵銦。基板202可包括經拉緊/加壓用於效能增強之絕緣體上矽(silicon on insulator；SOI)基板，基板202包括磊晶區域，包括隔離區域，包括摻雜區域，包括一或更多個半導體裝置或半導體裝置之部分，包括導電及/或非導電層，及/或包括其他適當的特徵及層。例如，基板202可包括鰭狀場效電晶體(fin-like field effect transistor；FinFET)。
操作104處，方法100(第1圖)在基板202之上形成硬遮罩層204。參看第2B圖，在本實施例中，硬遮罩層204使用非晶矽(a-Si)。在替代實施例中，硬遮罩層204可使用氧化矽(SiO2)、氮化矽(SiN)、氮氧化矽(SiON)、碳氮化矽(SiCN)、碳化矽(SiC)、其他適當材料，或上述材料之組合。進一步，在本實施例中，硬遮罩層204使用非晶矽層，此層具有範圍自約10埃(Å)至約2000埃之厚度。硬遮罩層204可藉由化學氣相沉積(chemical vapor deposition；CVD)、低壓化學氣相沉積(low pressure chemical vapor deposition；LPCVD)、電漿增強化學氣相沉積(plasma enhanced chemical vapor deposition；PECVD)、物理氣相沉積(physical vapor deposition；PVD)、原子層沉積(atomic layer deposition；ALD)，或其他適當的沉積方法形成。例如，硬遮罩層204可使用化學製品藉由化學氣相沉積形成，此等化學製品包括六氯二矽烷(HCD或Si2Cl6)、二氯矽烷(DCS或SiH2Cl2)、雙(叔丁胺)矽烷(BTBAS或C8H22N2Si)及二矽烷(DS或Si2H6)。
在操作106處，方法100(第1圖)在硬遮罩層204之上形成第一材料層206。參看第2C圖，第一材料層206使用不同於硬遮罩層204之材料。在各種實施例中，第一材料層206及硬遮罩層204具有高蝕刻選擇性。第一材料層206可包含矽、氫、氧，及/或碳，諸如旋塗式玻璃(spin-on glass；SOG)。在實施例中，第一材料層206為三層光微影技術中之底層。第一材料層206可使用化學氣相沉積、物理氣相沉積、旋塗，或其他適當製程形成。
在操作108處，方法100(第1圖)在第一材料層之上形成抗蝕劑層210。參看第2D圖，在本實施例中，在形成抗蝕劑層210之前，方法100在第一材料層206上形成中間層208。中間層208可為抗反射塗層(anti-reflective coating；ARC)，此層包括聚合材料層或含矽材料層，諸如氧化矽、碳氧化矽，及電漿增強化學氣相沉積之氧化矽。在替代實施例中，中間層208包含碳、氫，及/或氧。中間層 208可藉由化學氣相沉積、物理氣相沉積、原子層沉積，或其他適當方法形成。抗蝕劑層210被形成在中間層208上。在替代實施例中，抗蝕劑層210可在無中間層208之情況下直接地形成在第一材料層206之上。在各種實施例中，抗蝕劑層210係藉由旋塗製程，繼之以軟烘烤製程形成。
抗蝕劑層210可為正性抗蝕劑或負性抗蝕劑。正性抗蝕劑通常在抗蝕劑顯影劑中不可溶，但是藉由暴露於輻射會變得可溶，此輻射諸如深紫外線(DUV)射線、極紫外線(EUV)射線、電子束(e-beam)、X射線，或其他適當的輻射。一示例性正性抗蝕劑材料為化學放大抗蝕劑(chemically amplified resist；CAR)，此抗蝕劑包含由酸不穩定基團(acid labile group；ALG)所保護之主鏈聚合物。負性抗蝕劑具有相反之行為-通常在抗蝕劑顯影劑中可溶，但是藉由暴露於輻射會變得不可溶，此輻射諸如深紫外線(DUV)射線、極紫外線(EUV)射線、電子束(e-beam)、X射線，或其他適當的輻射。示例性負性抗蝕劑為當照射時形成分子內及/或分子間交聯之聚合物，此聚合物諸如乙基(α-羥基)丙烯酸鹽(Ethyl(α-hydroxy)acrylate；EHMA)及甲基丙烯酸(methacryl methacryl；MAA)。
在操作110處，方法100(第1圖)將抗蝕劑層210圖案化，從而形成抗蝕劑圖案210'。參看第2E圖，在本實施例中，抗蝕劑圖案210'包括溝槽212，此溝槽亦稱為抗蝕劑溝槽212。為了進一步說明本實施例，抗蝕劑溝槽212 具有用於在硬遮罩層204中形成島狀小型硬遮罩之小的尺寸。
島狀硬遮罩(亦即，與硬遮罩特徵之其餘特徵隔離之硬遮罩特徵)常常用於積體電路製造中。例如，當形成靜態隨機存取記憶體單元之接觸層時，將線段切割遮罩用於界定最終特徵。線端切割遮罩為島狀遮罩。然而，因為半導體製程持續進行至較小節點，諸如22nm、10nm，或甚至更小之節點，所以形成用於光微影技術之島狀小型硬遮罩已成為相當大的挑戰。一個原因在於小型抗蝕劑圖案遭受抗蝕劑剝落問題。若抗蝕劑層210經圖案化以形成島狀小型抗蝕劑圖案，如在傳統光微影技術製程中一樣，則島狀小型抗蝕劑圖案不會非常好地附著於下層(例如，中間層208)，且可能在光微影技術製程期間輕易地脫落。此舉是不希望的。應對抗蝕劑剝落問題之一方法使用逆向圖案化方法。在逆向圖案化方法中，抗蝕劑首先經圖案化以具有小的抗蝕劑溝槽(諸如抗蝕劑溝槽212)。然後，抗蝕劑溝槽係藉由蝕刻硬遮罩層及此硬遮罩層與抗蝕劑之間的任何中間層來傳遞至硬遮罩層(諸如硬遮罩層204)，以形成硬遮罩溝槽。其次，硬遮罩溝槽係利用介電材料而過度填充，且執行化學機械平坦化(chemical mechanical planarization；CMP)製程以移除過多的介電材料。最終，藉由選擇性蝕刻製程移除硬遮罩層，留下作為島狀小型遮罩之介電材料。逆向圖案化方法解決了抗蝕劑剝落問題。然而，此方法具有其自身之缺點。首先，歸因於使用額外介電材料及相關聯沉積、化學 機械平坦化，及蝕刻製程，此方法會產生額外成本。其次，歸因於在基板之上的額外處理(例如，硬遮罩層蝕刻兩次)，此方法可能在製造裝置中產生更多缺陷。所提供之標的優於傳統島狀抗蝕劑圖案及逆向圖案化方法兩者，如將在下文中論述。
仍參看第2E圖，在實施例中，操作110(第1圖)使用光遮罩(或遮罩或標線)圖案化抗蝕劑層210。或者，操作110可使用諸如電子束直接寫入(electron beam direct writing；EBDW)之無遮罩圖案化技術。在實施例中，圖案化抗蝕劑層210包括將抗蝕劑層210暴露於輻射，後暴露烘烤，在抗蝕劑顯影劑中顯影抗蝕劑層210及硬烘烤，從而移除抗蝕劑層210之暴露部分(或在負性抗蝕劑之情況下為未暴露部分)，且在中間層208上留下作為抗蝕劑圖案210之此抗蝕劑層之未暴露部分。輻射可為深紫外線射線、極紫外線射線、電子束、X射線、離子束，或另一適當之輻射。在其中使用光遮罩以圖案化抗蝕劑層210之實施例中，光遮罩可為諸如透射遮罩或反射遮罩之不同類型，且光遮罩可以各種技術形成，諸如二元遮罩或相移遮罩(phase shift mask；PSM)。在一實例中，二元遮罩包括透明基板(例如，熔凝石英)，及不透明材料(例如，鉻))，此不透明材料塗覆於遮罩之不透明區域中。在另一實例中，相移遮罩包括經設置以具有適當相位差之各種特徵，以增強解析度及成像品質。在各種實施例中，抗蝕劑層210可經圖案化 以包括任何數目之溝槽圖案，且溝槽圖案可具有任何形狀及大小。
在操作112處，方法100(第1圖)將抗蝕劑溝槽212轉印至第一材料層206，從而形成圖案化第一材料層206'。在本實施例中，操作112包括通過抗蝕劑溝槽212蝕刻中間層208及第一材料層206。蝕刻製程可包括乾式(電漿)蝕刻、濕式蝕刻，及/或其他蝕刻方法。例如，乾式蝕刻製程可實施含氧氣體、含氟氣體(例如，CF4、SF6、CH2F2、CHF3及/或C2F6)、含氯氣體(例如，Cl2、CHCl3、CCl4及/或BCl3)、含溴氣體(例如，HBr及/或CHBR3)、含碘氣體、其他適當之氣體及/或電漿，及/或上述各者之組合。例如，濕式蝕刻製程可使用具有稀釋氫氟酸(diluted hydrofluoric acid；DHF)、氫氧化鉀(potassium hydroxide；KOH)溶液，氨水之蝕刻劑，或其他適當之濕式蝕刻劑。此一或多個蝕刻製程在第一材料層206中形成溝槽214。在已蝕刻第一材料層206之後，移除抗蝕劑圖案210'及中間層208。抗蝕劑圖案210'可例如藉由濕式蝕刻製程移除，此濕式蝕刻製程使用光阻劑剝離液、鹼性水溶液、胺溶劑混合物，或有機溶劑。中間層208可藉由乾式(電漿)蝕刻、濕式蝕刻，及/或其他蝕刻方法移除，此等方法經選擇性地調諧以移除中間層208，同時圖案化第一材料層206'保持大體上不變。
在本實施例中，第一材料層206及硬遮罩層204具有高蝕刻選擇性。換言之，當在蝕刻製程(例如，乾式蝕 刻製程)中蝕刻第一材料層206以形成溝槽214時，硬遮罩層204在蝕刻製程中保持大體上不變。作為操作112之結果，溝槽214經形成於第一材料層206中且暴露硬遮罩層204之一部分，如第2F圖中所示。
在操作114，方法100(第1圖)用離子束216處理硬遮罩層204。參看第2G圖，將離子束216朝向裝置200之頂表面導引。因為圖案化第一材料層206'部分地覆蓋硬遮罩層204，所以僅對應於溝槽214或藉由溝槽214暴露之硬遮罩層204之一部分係藉由離子束216處理。在本實施例中，硬遮罩層204之經處理部分經標記為204A，而硬遮罩層204之未處理部分經標記為204B。在本實施例中，離子束216相對於目標蝕刻劑降低經處理部分204A之蝕刻速率。特定言之，經處理部分204A相對於目標蝕刻劑比未處理部分204B獲得更低蝕刻速率(或較高蝕刻阻力)。在實施例中，硬遮罩層204包括非晶矽，離子束216包括B離子或BF2離子，且目標蝕刻劑包括氫氧化銨或氫氧化四甲銨。實驗已表明，在用B離子束或BF2離子束處理之後，在氫氧化銨或氫氧化四甲銨中之非晶矽之蝕刻速率顯著下降。在一實例中，蝕刻速率自約200Å/分鐘(Å/min)降低至約0Å/min。
在實施例中，離子束216係藉由離子注入機作為聚焦離子束產生。在實施例中，離子束216為B離子束或BF2離子束，且離子束216具備自約1.0kV至約50kV之離子能量及自約1×e13離子/cm2至約1×e16離子/cm2之離子劑 量。在替代實施例中，離子束216可包括以下離子物種中之一者：C、P、In、Ge、As、Si，及Yb。此外，離子束216可以一傾斜角及以一適當扭轉角朝向硬遮罩層204導引，此傾斜角之範圍自0度(垂直於裝置200之頂表面)至約45度(在法線之兩側)。在實施例中，硬遮罩層204之離子束處理可在自約-100攝氏度至約100攝氏度之間的溫度範圍內執行，且執行達約3秒至約600秒之時間。
除通過溝槽214之外，圖案化第一材料層206'有效地遮擋離子束216到達硬遮罩層204。在實施例中，圖案化第一材料層206'之蝕刻速率保持大體上不受離子束216之影響。此外，圖案化第一材料層206'及硬遮罩層204(包括經處理及未處理之部分)仍在蝕刻製程中具有足夠的蝕刻選擇性。
在實施例中，需要保持基板202大體上不受離子束216之影響。為了進一步說明此實施例，硬遮罩層204之厚度及離子束216之特性(諸如離子能量、離子劑量、光束傾斜角及扭轉角)經仔細設計，以便離子束216充分地處理硬遮罩層部分204A，但不(或不顯著地)穿透基板202。
在實施例中，在硬遮罩層204已經過離子束216處理之後，操作114進一步包括退火製程。例如，退火製程可包括微秒退火(microsecond annealing；μSSA)製程、微波退火(microwave annealing；MWA)製程、快速熱退火(rapid thermal annealing；RTA)製程，及/或其他適當 退火製程。退火製程可改善經處理部分204的臨界尺寸及輪廓，因此形成最終島狀小型硬遮罩。
在操作116處，方法100(第1圖)使用蝕刻製程移除圖案化第一材料層206'，此蝕刻製程可包括乾式(電漿)蝕刻、濕式蝕刻，及/或其他蝕刻方法。例如，乾式蝕刻製程可實施含氧氣體、含氟氣體、含氯氣體、含溴氣體、含碘氣體、其他適當氣體及/或電漿，及/或上述各者之組合。例如，濕式蝕刻製程可使用具有稀釋氫氟酸(diluted hydrofluoric acid；DHF)、氫氧化鉀(potassium hydroxide；KOH)溶液，氨水之蝕刻劑，或其他適當之濕式蝕刻劑。在本實施例中，蝕刻製程經調諧以選擇性地移除圖案化第一材料層206'，而包括經處理部分204A及未處理部分204B兩者之硬遮罩層204保持大體上不變，如第2H圖中所示。
在操作118處，方法100(第1圖)移除硬遮罩層204之未處理部分204B。蝕刻製程可包括乾式(電漿)蝕刻、濕式蝕刻，及/或其他蝕刻方法。在本實施例中，硬遮罩層204包括非晶矽且蝕刻製程使用氫氧化銨或氫氧化四甲銨作為蝕刻劑。歸因於操作114中之離子束處理，經處理部分204A及未處理部分204B在蝕刻製程中具有高的蝕刻選擇性。結果，未處理部分204B係藉由蝕刻製程移除，而經處理部分204A保持大體上不變且成為基板202之上的硬遮罩204A'。取決於經處理與未處理部分204A及204B之間的蝕刻選擇性，硬遮罩204A'可與經處理部分204A相同 或大體上相同。參看第2I圖，此圖中繪示其中硬遮罩204A’位於基板202之上的裝置200。在本實施例中，硬遮罩204A'為用於蝕刻基板202之島狀小型硬遮罩。與用於形成島狀小型硬遮罩之傳統方法相比，所提供之標的具有許多優點。首先，因為遮罩特徵係形成為抗蝕劑溝槽(例如，抗蝕劑溝槽212)，所以所提供之標的克服了抗蝕劑剝落問題。其次，所提供之標的直接地在硬遮罩層(例如，硬遮罩層204)中形成島狀小型硬遮罩，且不需要逆向材料及相關聯製程。因此，除其他益處之外，所提供之標的具有更多的成本效益。
在操作120處，方法100(第1圖)利用以硬遮罩204A'作為蝕刻遮罩蝕刻基板202。參看第2J圖，此圖中圖示具有經蝕刻之基板202之裝置200。硬遮罩204A'作為蝕刻遮罩且保護基板202之一部分202A免受蝕刻。在本實施例中，部分202A在基板202上形成島狀小型特徵。基板202可使用乾式蝕刻、濕式蝕刻、反應式離子刻蝕，及/或其他蝕刻方法蝕刻。在另一實施例中，硬遮罩204A'用作心軸切割製程中之切割遮罩。在心軸切割製程中，心軸遮罩界定第一暴露中之心軸圖案且切割遮罩界定第二暴露中之切割圖案(諸如硬遮罩204A')。例如，心軸圖案可為鰭式場效電晶體的鰭形，靜態隨機存取記憶體單元中之接觸線，等等。切割圖案界定待自心軸圖案或心軸圖案之衍生圖案中移除之區域。最終圖案包括心軸圖案加上衍生圖案，但不包括切割圖案。應注意，所提供之標的可用於形成任何類型之硬遮罩，但不限於島狀小型硬遮罩。就此而言，硬遮罩204A' 可為任何形狀及大小且可由方法100形成各種積體電路特徵，此等特徵諸如隔離特徵、源極及汲極特徵、閘極堆疊、觸點、通孔，及金屬互連。硬遮罩204A'可在基板202已被蝕刻之後，例如藉由乾式蝕刻、濕式蝕刻，或其他蝕刻方法移除。
在操作122處，方法100(第1圖)執行進一步步驟以完成裝置200之製造。例如，方法100可形成在基板202中或基板202上形成主動元件，諸如電晶體；形成高-k金屬閘極堆疊；形成多層互連結構；且以各種主動及被動元件形成邏輯電路及/或記憶體單元。
雖然不意欲為限制，但是本案提供製造積體電路之許多益處。例如，本案實施例可有利地用於形成島狀小型硬遮罩。與用於形成島狀小型硬遮罩之傳統方法相比，所提供之標的克服了抗蝕劑剝落問題，因為硬遮罩首先形成為抗蝕劑溝槽。此外，所提供之標的直接地在硬遮罩層中形成島狀小型硬遮罩，無需逆向材料填充及相關聯製程(諸如沉積、化學機械平坦化，及蝕刻)。結果，所提供之標的節省材料及處理成本且幫助減少最終積體電路裝置中之缺陷。所提供之標的可輕易地整合至現有的積體電路製造流程中且用於形成各種蝕刻遮罩，而不限於島狀小型硬遮罩。事實上，至此所論述之特定實施例僅為實例且不將本案之發明範圍限制超出申請專利範圍中明確敘述之內容。
在一示例性態樣中，本案針對圖案化基板之方法。此方法包括在基板之上形成硬遮罩層；在硬遮罩層之上 形成第一材料層；且在第一材料層中形成溝槽。此方法進一步包括以通過溝槽之離子束處理硬遮罩層，其中硬遮罩層之經處理部分之蝕刻速率相對於蝕刻製程降低，而硬遮罩層之未處理部分之蝕刻速率相對於蝕刻製程保持大體上不變。此方法進一步包括在處理硬遮罩層之後移除第一材料層。此方法進一步包括以此蝕刻製程移除硬遮罩層之未處理部分，從而在基板之上形成硬遮罩。此方法進一步包括以硬遮罩作為蝕刻遮罩蝕刻基板。
在另一示例性態樣中，本案針對圖案化基板之方法。此方法包括在基板之上形成硬遮罩層，其中此硬遮罩層包括非晶矽。此方法進一步包括在硬遮罩層之上形成第一材料層且在此第一材料層中形成溝槽，此溝槽暴露硬遮罩層之第一部分。此方法進一步包括用離子束處理第一部分，從而降低相對於蝕刻劑之第一部分之蝕刻速率，而硬遮罩層之未處理部分之蝕刻速率相對於蝕刻劑保持大體上不變。離子束為以下兩種離子束中之一者：B離子束及BF2離子束。此方法進一步包括在處理第一部分之後移除第一材料層。此方法進一步包括用蝕刻劑移除硬遮罩層之未處理部分，從而在基板之上形成硬遮罩，且用硬遮罩作為蝕刻遮罩蝕刻基板。
在又一示例性態樣中，本案針對圖案化基板之方法。此方法包括在基板之上形成硬遮罩層，其中硬遮罩層包括非晶矽；且在硬遮罩層之上形成第一材料層。此方法進一步包括在第一材料層中形成溝槽，此溝槽暴露硬遮罩層之第一部分。此方法進一步包括用離子束處理第一部分，從而 相對於蝕刻劑降低第一部分之蝕刻速率，而硬遮罩層之未處理部分之蝕刻速率相對於蝕刻劑保持大體上不變。離子束為以下兩種離子束中之一者：B離子束及BF2離子束。蝕刻劑包括以下兩種蝕刻劑中之一者：氫氧化銨及氫氧化四甲銨。此方法進一步包括在處理第一部分之後移除第一材料層。此方法進一步包括用蝕刻劑移除硬遮罩層之未處理部分，從而在基板之上形成硬遮罩；且用硬遮罩作為蝕刻遮罩蝕刻基板。
上文概括了若干實施例之特徵，以便一般技術者可較好地瞭解本案之態樣。一般技術者應瞭解，一般技術者可容易地使用本案作為用於設計或改變其他製程及結構之基礎，此等其他製程及結構用於進行本文引入之實施例之相同目的及/或達成本文引入之實施例之相同優點。一般技術者亦應認識到，此等同等構造不背離本案之精神及範疇；且應認識到，此等同等構造可在本文中進行各種變化、替換和變更，而不背離本案之精神及範疇。
100‧‧‧方法
102、104、106、108、110、112、114、116、118、120、122‧‧‧操作

Claims (10)

  1. 一種圖案化一基板之方法，該方法包含以下步驟：在該基板之上形成一硬遮罩層；在該硬遮罩層之上形成一第一材料層；在該第一材料層中形成一溝槽；以通過該溝槽之一離子束處理該硬遮罩層，其中該硬遮罩層之一經處理部分之一蝕刻速率相對於一蝕刻製程降低，而該硬遮罩層之一未處理部分之一蝕刻速率相對於該蝕刻製程保持大體上不變；在該處理該硬遮罩層之步驟之後，移除該第一材料層；以該蝕刻製程移除該硬遮罩層之該未處理部分，從而在該基板之上形成一硬遮罩；以及以該硬遮罩作為一蝕刻遮罩蝕刻該基板。
  2. 如請求項1所述之方法，其中該離子束為一B離子束或BF2離子束，該離子束具有自約1.0kV至約50kV之離子能量，及自約1×e13離子/cm2至約1×e16離子/cm2之離子劑量。
  3. 如請求項1所述之方法，其中該離子束為以下各者中之一者：B、BF2、C、P、In、Ge、As、Si，及Yb。
  4. 如請求項1所述之方法，其中該移除該第一材料層之步驟使用另一蝕刻製程，該蝕刻製程選擇性地移除該第一材料層，同時該硬遮罩層保持大體上不變。
  5. 如請求項1所述之方法，其中該形成該第一溝槽之步驟包括：在該第一材料層之上形成一抗蝕劑層；圖案化該抗蝕劑層以形成一抗蝕劑溝槽；以及將該抗蝕劑溝槽轉印至該第一材料層。
  6. 如請求項5所述之方法，其中該形成該第一溝槽之步驟進一步包括：在該形成該抗蝕劑層之前，在該第一材料層之上形成一抗反射塗層。
  7. 如請求項1所述之方法，其中該在該第一材料層中形成該溝槽之步驟包括另一蝕刻製程，該蝕刻製程選擇性地移除該第一材料層，同時該硬遮罩層保持大體上不變。
  8. 一種圖案化一基板之方法，該方法包含以下步驟：在該基板之上形成一硬遮罩層，其中該硬遮罩層包括非晶矽；在該硬遮罩層之上形成一第一材料層； 在該第一材料層中形成一溝槽，該溝槽暴露該硬遮罩層之一第一部分；以一離子束處理該第一部分，從而降低相對於一蝕刻劑之該第一部分之一蝕刻速率，而該硬遮罩層之一未處理部分之一蝕刻速率相對於該蝕刻劑保持大體上不變，其中該離子束為以下各者中之一者：一B離子束及一BF2離子束；在該處理該第一部分之後，移除該第一材料層；以該蝕刻劑移除該硬遮罩層之該未處理部分，從而在該基板之上形成一硬遮罩；以及以該硬遮罩作為一蝕刻遮罩蝕刻該基板。
  9. 如請求項8所述之方法，其中該移除該第一材料層之步驟及該在該第一材料層中形成該溝槽之步驟各自包括一蝕刻製程，該蝕刻製程選擇性地移除該第一材料層，而該硬遮罩層保持大體上不變。
  10. 一種圖案化一基板之方法，該方法包含以下步驟：在該基板之上形成一硬遮罩層，其中該硬遮罩層包括非晶矽；在該硬遮罩層之上形成一第一材料層；在該第一材料層中形成一溝槽，該溝槽暴露該硬遮罩層之一第一部分； 以一離子束處理該第一部分，從而降低相對於一蝕刻劑之該第一部分之一蝕刻速率，而該硬遮罩層之一未處理部分之一蝕刻速率相對於該蝕刻劑保持大體上不變，其中該離子束為以下各者中之一者：一B離子束及一BF2離子束；且其中該蝕刻劑包括以下兩者中之一者：氫氧化銨及氫氧化四甲銨；在該處理該第一部分之後，移除該第一材料層；以該蝕刻劑移除該硬遮罩層之該未處理部分，從而在該基板之上形成一硬遮罩；以及用作為一蝕刻遮罩之該硬遮罩蝕刻該基板。
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