TWI576961B - 用於高深寬比塡充的半導體重流處理 - Google Patents

用於高深寬比塡充的半導體重流處理 Download PDF

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Publication number
TWI576961B
TWI576961B TW102112724A TW102112724A TWI576961B TW I576961 B TWI576961 B TW I576961B TW 102112724 A TW102112724 A TW 102112724A TW 102112724 A TW102112724 A TW 102112724A TW I576961 B TWI576961 B TW I576961B
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TW
Taiwan
Prior art keywords
feature
conductive layer
layer
workpiece
seed
Prior art date
Application number
TW102112724A
Other languages
English (en)
Chinese (zh)
Other versions
TW201347090A (zh
Inventor
艾密許伊斯梅爾T
林凱羅柏特C
Original Assignee
應用材料股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/801,860 external-priority patent/US9245798B2/en
Application filed by 應用材料股份有限公司 filed Critical 應用材料股份有限公司
Publication of TW201347090A publication Critical patent/TW201347090A/zh
Application granted granted Critical
Publication of TWI576961B publication Critical patent/TWI576961B/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882Reflowing or applying of pressure to better fill the contact hole
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
TW102112724A 2012-04-26 2013-04-10 用於高深寬比塡充的半導體重流處理 TWI576961B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201261638856P 2012-04-26 2012-04-26
US13/801,860 US9245798B2 (en) 2012-04-26 2013-03-13 Semiconductor reflow processing for high aspect ratio fill

Publications (2)

Publication Number Publication Date
TW201347090A TW201347090A (zh) 2013-11-16
TWI576961B true TWI576961B (zh) 2017-04-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW102112724A TWI576961B (zh) 2012-04-26 2013-04-10 用於高深寬比塡充的半導體重流處理

Country Status (2)

Country Link
KR (1) KR20130121041A (ko)
TW (1) TWI576961B (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9758896B2 (en) * 2015-02-12 2017-09-12 Applied Materials, Inc. Forming cobalt interconnections on a substrate
US9711449B2 (en) * 2015-06-05 2017-07-18 Tokyo Electron Limited Ruthenium metal feature fill for interconnects
JP6723128B2 (ja) 2016-09-27 2020-07-15 東京エレクトロン株式会社 ニッケル配線の製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6368966B1 (en) * 1998-06-30 2002-04-09 Semitool, Inc. Metallization structures for microelectronic applications and process for forming the structures
US6998337B1 (en) * 2003-12-08 2006-02-14 Advanced Micro Devices, Inc. Thermal annealing for Cu seed layer enhancement
TW201145461A (en) * 2010-03-24 2011-12-16 Applied Materials Inc Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6368966B1 (en) * 1998-06-30 2002-04-09 Semitool, Inc. Metallization structures for microelectronic applications and process for forming the structures
US6998337B1 (en) * 2003-12-08 2006-02-14 Advanced Micro Devices, Inc. Thermal annealing for Cu seed layer enhancement
TW201145461A (en) * 2010-03-24 2011-12-16 Applied Materials Inc Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance

Also Published As

Publication number Publication date
TW201347090A (zh) 2013-11-16
KR20130121041A (ko) 2013-11-05

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MM4A Annulment or lapse of patent due to non-payment of fees