TWI551206B - Multilayer printed circuit board and method of manufacturing the same - Google Patents

Multilayer printed circuit board and method of manufacturing the same Download PDF

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Publication number
TWI551206B
TWI551206B TW103128287A TW103128287A TWI551206B TW I551206 B TWI551206 B TW I551206B TW 103128287 A TW103128287 A TW 103128287A TW 103128287 A TW103128287 A TW 103128287A TW I551206 B TWI551206 B TW I551206B
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Taiwan
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resin
resin films
circuit board
multilayer printed
printed circuit
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TW103128287A
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Chinese (zh)
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TW201521531A (en
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原田敏一
石川慶周
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電裝股份有限公司
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/4617Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • H05K1/025Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4697Manufacturing multilayer circuits having cavities, e.g. for mounting components

Description

多層印刷電路板及其製造方法 Multilayer printed circuit board and method of manufacturing same

本發明係關於多層印刷電路板及其製造方法。 The present invention relates to a multilayer printed circuit board and a method of fabricating the same.

傳統上關於具有導電圖案形成於二側上的多層印刷電路板的製造方法,有複數個樹脂膜疊層之方法,其中,導電圖案僅形成於其一側上(舉例而言,請參考日本專利申請公開號2003-86948)。 Conventionally, regarding a method of manufacturing a multilayer printed circuit board having conductive patterns formed on two sides, there is a method of laminating a plurality of resin films in which a conductive pattern is formed only on one side thereof (for example, refer to Japanese Patent Application Publication No. 2003-86948).

在此製造方法中,首先,製備均具有相同厚度的複數個樹脂膜。 In this manufacturing method, first, a plurality of resin films each having the same thickness are prepared.

接著,在複數個樹脂膜之中,二任意樹脂膜層疊,以致於未形成導電圖案的側會彼此相面對。 Next, among the plurality of resin films, two arbitrary resin films are laminated such that the sides on which the conductive patterns are not formed face each other.

然後,其它餘留的樹脂膜層疊,以致於形成導電圖案的側與未形成導電圖案的側彼此相面對。 Then, the remaining resin films are laminated such that the side where the conductive pattern is formed and the side where the conductive pattern is not formed face each other.

然後,藉由施壓加熱層疊的樹脂膜,製造多層電路板。 Then, the laminated resin film is heated by applying pressure to manufacture a multilayer circuit board.

根據本製造方法,由於僅有導電圖案形成於一側上的樹脂膜會被使用,所以,在樹脂膜的二側上形成導電圖案 的處理變得不必要,以致於相較於在一側上形成有導電圖案之樹脂膜與在二側上形成有導電圖案的樹脂膜都被一起使用的情形,多層印刷電路板的製程會簡化。 According to the manufacturing method, since only a resin film in which a conductive pattern is formed on one side is used, a conductive pattern is formed on both sides of the resin film. The processing becomes unnecessary, so that the process of the multilayer printed circuit board is simplified as compared with the case where the resin film having the conductive pattern formed on one side and the resin film having the conductive pattern formed on both sides are used together .

此外,當使用均具有不同厚度的樹脂膜時,這些具有各別厚度的樹脂膜必須被分別製造。但是,根據上述製造方法,由於僅有均具有單一厚度的多個樹脂膜會被製造,所以,多層印刷電路板的製程可以簡化。 Further, when resin films each having a different thickness are used, these resin films having respective thicknesses must be separately manufactured. However, according to the above manufacturing method, since only a plurality of resin films each having a single thickness are manufactured, the process of the multilayer printed circuit board can be simplified.

但是,由於均具有相同厚度的多個樹脂膜被層疊時,在以上述習知的製造方法製造後,在多層印刷電路板中產生下述問題。 However, since a plurality of resin films each having the same thickness are laminated, the following problems occur in the multilayer printed wiring board after being manufactured by the above-described conventional manufacturing method.

亦即,當考慮配置在相鄰樹脂膜的導電圖案之間的介電質的厚度時,單一樹脂膜的樹脂厚度等於其它樹脂膜層疊部份中的介電質的厚度。 That is, when considering the thickness of the dielectric disposed between the conductive patterns of the adjacent resin films, the resin thickness of the single resin film is equal to the thickness of the dielectric in the laminated portion of the other resin film.

另一方面,二樹脂膜的樹脂厚度等於二樹脂膜層疊的部份中的介電質之厚度。 On the other hand, the resin thickness of the two resin film is equal to the thickness of the dielectric in the portion where the two resin films are laminated.

因此,由於在上述二樹脂膜層疊的部份中與在其它樹脂膜層疊的部份中,介電質的厚度不同,所以,當在多層印刷電路板中形成高頻電路時,取得高頻訊號的傳輸線之阻抗的公式變得複雜。 Therefore, since the thickness of the dielectric is different in the portion where the two resin films are laminated and the portion laminated on the other resin film, high frequency signals are obtained when a high frequency circuit is formed in the multilayer printed circuit board. The formula of the impedance of the transmission line becomes complicated.

舉例而言,相較於使用其它樹脂膜層疊的部份之導電圖案的情形,當上述二樹脂膜層疊的部份之導電圖案作為傳輸線時,傳輸線與位於傳輸線外面的導電圖案之間的間隔將不同。 For example, in the case of a conductive pattern in which a portion of the other resin film is laminated, when a conductive pattern of a portion of the above-mentioned two resin film lamination is used as a transmission line, an interval between the transmission line and a conductive pattern located outside the transmission line will be different.

基於此理由,在傳輸線與傳輸線外側中的導電圖案之 間複數個的介電質厚度對於阻抗的影響會不同。 For this reason, the conductive pattern in the outer side of the transmission line and the transmission line The effect of the dielectric thickness on the impedance will vary.

因此,假使上述二樹脂膜相層疊的部份之導電圖案作為傳輸線時,用於計算傳輸線的阻抗之公式將變得複雜,以及,電路設計將非常複雜。 Therefore, if a conductive pattern of a portion in which the above two resin films are laminated is used as a transmission line, the formula for calculating the impedance of the transmission line becomes complicated, and the circuit design will be very complicated.

此外,當在多層印刷電路板的二側上之導電圖案被指派給接地線時、以及在多層印刷電路板內部的導電圖案作為高頻訊號的傳輸線時,當構成多層印刷電路板之樹脂膜的數目是奇數時,則在傳輸線與接地線之間的間隔在層疊方向上的一側與另一側上會不同。 Further, when the conductive pattern on the two sides of the multilayer printed circuit board is assigned to the ground line, and the conductive pattern inside the multilayer printed circuit board is used as the transmission line of the high-frequency signal, when forming the resin film of the multilayer printed circuit board When the number is an odd number, the interval between the transmission line and the ground line may be different on one side and the other side in the stacking direction.

亦即,傳輸線變成在多層印刷電路板的層疊方向上偏離中心。 That is, the transmission line becomes off-center in the stacking direction of the multilayer printed circuit board.

基於此理由,用於計算傳輸線的阻抗之公式變得複雜,且電路設計將變得非常複雜。 For this reason, the formula for calculating the impedance of the transmission line becomes complicated, and the circuit design becomes very complicated.

慮及上述揭示的問題而產生本發明,本發明之目的在於提供能夠使考慮阻抗的電路設計變得容易之多層印刷電路板,以及多層印刷電路板的製造方法。 The present invention has been made in view of the problems disclosed above, and an object of the present invention is to provide a multilayer printed circuit board capable of facilitating circuit design in consideration of impedance, and a method of manufacturing a multilayer printed circuit board.

在根據第一態樣的多層印刷電路板中,多層印刷電路板包含複數個樹脂膜及僅形成於各樹脂膜的一側上之導電圖案。 In the multilayer printed circuit board according to the first aspect, the multilayer printed circuit board includes a plurality of resin films and conductive patterns formed only on one side of each of the resin films.

在複數個樹脂膜中,二樹脂膜層疊以致於未形成導電圖案的側會彼此面對。 In the plurality of resin films, the two resin films are laminated such that the sides where the conductive patterns are not formed may face each other.

在複數個樹脂膜中先前所述二樹脂膜除外的其它樹脂 膜層疊,以致於形成有導電圖案的側與未形成導電圖案的側彼此面對。 Other resins excluding the previously described two resin films in a plurality of resin films The films are laminated such that the side where the conductive pattern is formed and the side where the conductive pattern is not formed face each other.

在其它樹脂膜層疊的部份中在層疊方向上導電圖案之間的所有間隔是相同的。 All the intervals between the conductive patterns in the lamination direction are the same in the portion where the other resin films are laminated.

在二樹脂膜層疊的部份中在層疊方向上導電圖案之間的間隔與在其它它樹脂膜層疊的部份中的間隔是相同的。 The interval between the conductive patterns in the lamination direction in the portion where the two resin films are laminated is the same as the interval in the portion in which the other resin film is laminated.

在根據第二態樣之多層印刷電路板的製造方法中,方法包含:製備處理,用於製備複數個樹脂膜,其中,導電圖案僅形成於各樹脂膜的一側上;層疊處理,用於層疊複數個樹脂膜;以及,施壓加熱處理,在加熱層疊複數個樹脂膜時施壓。 In the method of manufacturing a multilayer printed circuit board according to the second aspect, the method includes: a preparation process for preparing a plurality of resin films, wherein the conductive pattern is formed only on one side of each resin film; a lamination process for A plurality of resin films are laminated; and a pressure heat treatment is performed to apply pressure when a plurality of resin films are laminated by heating.

在複數個樹脂膜中,在層疊處理中,將二樹脂膜層疊,以致於未形成導電圖案的側彼此面對。 In the plurality of resin films, in the lamination process, the two resin films are laminated such that the sides where the conductive patterns are not formed face each other.

在層疊處理中,在複數個樹脂膜中先前所述二樹脂膜除外的其它樹脂膜層疊,以致於形成有導電圖案的側與未形成導電圖案的側彼此面對。 In the lamination process, other resin films excluding the previously described two resin films in the plurality of resin films are laminated such that the side where the conductive pattern is formed and the side where the conductive pattern is not formed face each other.

在製備處理中製備均具有相同的樹脂厚度之複數個樹脂膜以用於其它樹脂膜,以及,在製備處理中,製備具有的樹脂厚度總合與其它單一樹脂膜的厚度相同的二樹脂膜以用於這二樹脂膜。 A plurality of resin films each having the same resin thickness are prepared for use in other resin films in the preparation process, and, in the preparation process, a two-resin film having a resin thickness sum equal to that of the other single resin films is prepared. Used for these two resin films.

根據本發明,在上述二樹脂膜層疊的部份中以及其它樹脂膜層疊的部份中,形成於相鄰的樹脂膜中的導電圖案之間的介電質厚度製成相等的。 According to the invention, in the portion where the two resin films are laminated and the portion where the other resin films are laminated, the dielectric thickness between the conductive patterns formed in the adjacent resin films is made equal.

因此,當使用多層印刷電路板的導電圖案作為高頻訊 號的傳輸線時,容易計算高頻訊號線的阻抗,且能夠使電路設計容易。 Therefore, when using a conductive pattern of a multilayer printed circuit board as a high frequency signal When the transmission line of the number is used, it is easy to calculate the impedance of the high-frequency signal line, and the circuit design can be made easy.

舉例而言,即使在複數個樹脂膜中形成的任何導電圖案作為高頻訊號的傳輸線時,仍然能夠使要求阻抗控制的所有傳輸線中的傳輸線與位於傳輸線外側中的導電圖案之間的介電質厚度相等。 For example, even when any conductive pattern formed in a plurality of resin films is used as a transmission line of a high frequency signal, the dielectric between the transmission line in all transmission lines requiring impedance control and the conductive pattern located outside the transmission line can be made. The thickness is equal.

結果,在要求阻抗控制的所有傳輸線中,使介電質厚度對阻抗的影響相等。 As a result, the influence of the dielectric thickness on the impedance is made equal in all transmission lines requiring impedance control.

因此,容易計算阻抗。 Therefore, it is easy to calculate the impedance.

此外,當在多層印刷電路板的二側上的導電圖案被指派給接地線時,以及,多層印刷電路板內部中的導電圖案作為高頻訊號的傳輸線時,當構成多層印刷電路板的樹脂膜之數目是奇數時,傳輸線可以在層疊方向上位於中心。 Further, when the conductive pattern on the two sides of the multilayer printed circuit board is assigned to the ground line, and when the conductive pattern in the inside of the multilayer printed circuit board is used as the transmission line of the high-frequency signal, when the resin film constituting the multilayer printed circuit board When the number is an odd number, the transmission line can be centered in the stacking direction.

因此,容易計算阻抗。 Therefore, it is easy to calculate the impedance.

1‧‧‧多層印刷電路板 1‧‧‧Multilayer printed circuit board

2‧‧‧主動組件 2‧‧‧Active components

2a‧‧‧下電極 2a‧‧‧ lower electrode

10‧‧‧樹脂膜 10‧‧‧ resin film

10a‧‧‧側 10a‧‧‧ side

10b‧‧‧側 10b‧‧‧ side

11‧‧‧導電圖案 11‧‧‧ conductive pattern

12‧‧‧通路 12‧‧‧ pathway

13‧‧‧通路孔 13‧‧‧ access hole

14‧‧‧通孔 14‧‧‧through hole

15‧‧‧金屬粉末 15‧‧‧Metal powder

101‧‧‧最低樹脂膜 101‧‧‧Minyl resin film

102‧‧‧最低樹脂膜 102‧‧‧Minyl resin film

103‧‧‧樹脂膜 103‧‧‧ resin film

111‧‧‧傳輸線 111‧‧‧ transmission line

111a‧‧‧傳輸線 111a‧‧‧ transmission line

111b‧‧‧傳輸線 111b‧‧‧ transmission line

112‧‧‧接地線 112‧‧‧ Grounding wire

113‧‧‧接地線 113‧‧‧ Grounding wire

201‧‧‧多層印刷電路板 201‧‧‧Multilayer printed circuit board

J1‧‧‧多層印刷電路板 J1‧‧‧Multilayer printed circuit board

J201‧‧‧多層印刷電路板 J201‧‧‧Multilayer printed circuit board

在附圖中:圖1顯示第一實施例中的多層印刷電路板的剖面視圖;圖2顯示第一實施例中的多層印刷電路板的製造方法的說明圖;圖3顯示第一比較實施例中的多層印刷電路板的製造方法的說明圖;圖4顯示第一比較實施例中的多層印刷電路板的剖面 視圖;圖5顯示第二實施例中的多層印刷電路板的製造方法的說明圖;圖6顯示第二實施例中的多層印刷電路板的剖面視圖;圖7顯示第三實施例中的多層印刷電路板的剖面視圖;圖8顯示第三實施例中的多層印刷電路板的製造方法的說明圖;圖9顯示第四實施例中的多層印刷電路板的剖面視圖;圖10顯示第四實施例中的多層印刷電路板的製造方法的說明圖;圖11顯示第五實施例中的多層印刷電路板的剖面視圖;圖12顯示第五實施例中的多層印刷電路板的製造方法的說明圖;圖13顯示第二比較實施例中的多層印刷電路板的製造方法的說明圖;圖14顯示第二比較實施例中的多層印刷電路板的剖面視圖; In the drawings: FIG. 1 is a cross-sectional view showing a multilayer printed circuit board in a first embodiment; FIG. 2 is an explanatory view showing a manufacturing method of the multilayer printed circuit board in the first embodiment; and FIG. 3 is a first comparative example. Description of a method of manufacturing a multilayer printed circuit board; FIG. 4 shows a section of a multilayer printed circuit board in the first comparative embodiment Figure 5 is an explanatory view showing a manufacturing method of the multilayer printed circuit board in the second embodiment; Figure 6 is a sectional view showing the multilayer printed circuit board in the second embodiment; and Figure 7 is a multi-layer printing in the third embodiment. FIG. 8 is a cross-sectional view showing a method of manufacturing a multilayer printed circuit board in a third embodiment; FIG. 9 is a cross-sectional view showing a multilayer printed circuit board in a fourth embodiment; FIG. 11 is a cross-sectional view showing a multilayer printed circuit board in a fifth embodiment; and FIG. 12 is an explanatory view showing a method of manufacturing the multilayer printed circuit board in the fifth embodiment; Figure 13 is an explanatory view showing a method of manufacturing a multilayer printed circuit board in a second comparative embodiment; Figure 14 is a cross-sectional view showing a multilayer printed circuit board in a second comparative embodiment;

於下,將參考附圖,說明本發明的實施例。 Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

應瞭解,在第二實施例及後續的實施例中,與第一實施例中相同或類似的組件將被給予相同的代號,且不說明其結構及特點以免贅述。 It is to be understood that in the second embodiment and the subsequent embodiments, the same or similar components as those in the first embodiment will be given the same reference numerals, and the structure and features thereof will not be described.

[第一實施例] [First Embodiment]

如圖1所示,本實施例的多層印刷電路板1(於下,簡稱為電路板1)是組件併入的在二側上具有導電圖案11之電路板,而使用高頻訊號的主動組件2建於電路板1中。 As shown in FIG. 1, the multilayer printed circuit board 1 of the present embodiment (hereinafter, simply referred to as the circuit board 1) is a circuit board having a conductive pattern 11 on both sides of the assembly, and an active component using a high frequency signal. 2 is built in circuit board 1.

電路板1具有層疊複數個樹脂膜10的結構,其中,導電圖案11僅形成於各樹脂膜10的一側上。 The circuit board 1 has a structure in which a plurality of resin films 10 are laminated, wherein the conductive patterns 11 are formed only on one side of each of the resin films 10.

各樹脂膜10由熱塑樹脂製成且相互黏著。各導體圖案11由例如銅箔等金屬箔製成。在各樹脂膜10中形成通路12,作為層間連接構件。複數個層疊的導電圖案11藉由通路12相連接。藉由燒結的金屬粉末胚而形成各通路12。 Each of the resin films 10 is made of a thermoplastic resin and adheres to each other. Each of the conductor patterns 11 is made of a metal foil such as copper foil. A via 12 is formed in each of the resin films 10 as an interlayer connection member. A plurality of stacked conductive patterns 11 are connected by vias 12. Each passage 12 is formed by a sintered metal powder embryo.

在複數個樹脂膜10中,二最低的樹脂膜101、102層疊,以致於未形成導電圖案11的側10b會彼此面對。 In the plurality of resin films 10, the two lowest resin films 101, 102 are laminated such that the side 10b where the conductive patterns 11 are not formed may face each other.

此外,形成於二最低樹脂膜101、102中的通路12相接合。 Further, the vias 12 formed in the two lowest resin films 101, 102 are joined.

在複數個樹脂膜10中二最低的樹脂膜除外的其它樹脂膜103層疊,以致於形成有導電圖案11的側10a與未形成導電圖案11的側10b彼此面對。 The other resin films 103 excluding the two lowest resin films among the plurality of resin films 10 are laminated such that the side 10a on which the conductive patterns 11 are formed and the side 10b on which the conductive patterns 11 are not formed face each other.

使用高頻訊號的主動組件2插入於其它樹脂膜10具有的通孔14中。舉例而言,主動組件2是LSI(大型積體) 組件。在本說明書中使用的高頻訊號之頻帶是3kHz或更高的電訊號。 The active component 2 using the high frequency signal is inserted into the through hole 14 of the other resin film 10. For example, active component 2 is an LSI (large scale) Component. The frequency band of the high frequency signal used in this specification is a digital signal of 3 kHz or higher.

主動組件2的下電極2a與導電圖案11連接,以及與配置在電路板1內部的高頻訊號之傳輸線111電連接。 The lower electrode 2a of the active component 2 is connected to the conductive pattern 11 and to the transmission line 111 of the high frequency signal disposed inside the circuit board 1.

形成於多片樹脂膜10上的各導電圖案11構成高頻訊號的傳輸線11及接地線112、113。 Each of the conductive patterns 11 formed on the plurality of resin films 10 constitutes a transmission line 11 of high frequency signals and ground lines 112, 113.

在本實施例中,形成於二最低樹脂膜101、102上的導電圖案11中之一指定給要求阻抗控制的高頻訊號之傳輸線111b。 In the present embodiment, one of the conductive patterns 11 formed on the two lowest resin films 101, 102 is assigned to the transmission line 111b of the high frequency signal requiring impedance control.

此外,形成於其它樹脂膜10上的某些導電圖案11指定給要求阻抗控制的高頻訊號之傳輸線111a。 Further, some of the conductive patterns 11 formed on the other resin film 10 are assigned to the transmission line 111a of the high frequency signal requiring impedance control.

在各傳輸線111a、111b上方及下方的導電圖案11指定給接地線112、113。 The conductive patterns 11 above and below the respective transmission lines 111a, 111b are assigned to the ground lines 112, 113.

在任一傳輸線111a、111b中,在傳輸線111與位於傳輸線111的外部之導電圖案112、113之間的間隔相等。 In any of the transmission lines 111a, 111b, the interval between the transmission line 111 and the conductive patterns 112, 113 located outside the transmission line 111 is equal.

接著,使用圖2,說明本實施例的電路板1之製造方法。 Next, a method of manufacturing the circuit board 1 of the present embodiment will be described using FIG.

此外,圖2顯示在施壓加熱之前複數個樹脂膜10的設置次序。 Further, Fig. 2 shows the arrangement order of the plurality of resin films 10 before the pressure heating.

首先,執行用於製備複數個樹脂膜10的製備處理,其中,導電圖案11僅形成於各樹脂膜10的一側上。 First, a preparation process for preparing a plurality of resin films 10 in which the conductive patterns 11 are formed only on one side of each of the resin films 10 is performed.

此時,如圖2所示,製備均具有相同的樹脂厚度d3之複數個樹脂膜,以用於複數個樹脂膜10中二最低膜除 外的其它樹脂膜103。 At this time, as shown in FIG. 2, a plurality of resin films each having the same resin thickness d3 are prepared for use in the second lowest film removal of the plurality of resin films 10. The other resin film 103 is external.

另一方面,製備具有與其它單一樹脂膜103的樹脂厚度d3相同之樹脂厚度d1、d2的總合之二樹脂膜,以用於二最低樹脂膜101、102。 On the other hand, a two-resin film having a total resin thickness d1, d2 which is the same as the resin thickness d3 of the other single resin film 103 is prepared for use in the two lowest resin films 101, 102.

在本實施例中,二最低樹脂膜101、102的各樹脂厚度d1、d2設定為其它單一樹脂膜103的樹脂厚度d3之一半。 In the present embodiment, the respective resin thicknesses d1 and d2 of the two lowest resin films 101 and 102 are set to be one-half of the resin thickness d3 of the other single resin film 103.

舉例而言,在施壓加熱之前其它單一樹脂膜103的樹脂厚度d3設定於50μm(微米),以及,最低樹脂膜101、102的各樹脂厚度d1、d2均設定於25μm。 For example, the resin thickness d3 of the other single resin film 103 before the pressure heating is set to 50 μm (micrometer), and the respective resin thicknesses d1 and d2 of the lowest resin films 101 and 102 are set to 25 μm.

接著,在各樹脂膜10的一側上配置金屬箔,以及,藉由圖型化金屬箔以形成導電圖案11。 Next, a metal foil is placed on one side of each resin film 10, and a conductive pattern 11 is formed by patterning a metal foil.

然後,藉由雷射光加工,在各樹脂膜10中形成通路孔13。 Then, via holes 13 are formed in each of the resin films 10 by laser light processing.

此時,根據二最低樹脂膜101、102的厚度d1、d2、及其它樹脂膜103的厚度d3,調整雷射輸出。 At this time, the laser output is adjusted in accordance with the thicknesses d1 and d2 of the two lowest resin films 101 and 102 and the thickness d3 of the other resin film 103.

然後,以膏狀金屬粉末15填充通路孔13,用於通路形成。 Then, the via hole 13 is filled with the paste metal powder 15 for via formation.

此外,以雷射光加工,在某些其它樹脂膜103中,形成用於插入主動組件2的通孔14。 Further, in the laser light processing, in some other resin film 103, a through hole 14 for inserting the active component 2 is formed.

然後,執行用於層疊複數個樹脂膜10的層疊處理。 Then, a lamination process for laminating a plurality of resin films 10 is performed.

此時,如圖2所示,首先,將二最低樹脂膜101、102層疊,以致於未形成導電圖案11的側10b彼此面對。 At this time, as shown in FIG. 2, first, the two lowest resin films 101, 102 are laminated such that the sides 10b where the conductive patterns 11 are not formed face each other.

然後,在二最低膜除外的複數個樹脂膜10之中的其它樹脂膜103層疊,以致於形成有導電圖案11的側10a與未形成導電圖案11的側10b彼此面對。 Then, the other resin films 103 among the plurality of resin films 10 excluding the two lowest films are laminated such that the side 10a on which the conductive patterns 11 are formed and the side 10b on which the conductive patterns 11 are not formed face each other.

換言之,最低樹脂膜101除外的樹脂膜10與形成有導電圖案11之面上的側10a相層疊,以及,最低的樹脂膜101上下顛倒及層疊。 In other words, the resin film 10 except the lowest resin film 101 is laminated on the side 10a on the surface on which the conductive pattern 11 is formed, and the lowest resin film 101 is turned upside down and laminated.

此外,當層疊其它樹脂膜103時,主動組件2插入於通孔14中。 Further, when the other resin film 103 is laminated, the active component 2 is inserted in the through hole 14.

然後,執行施壓加熱處理,當加熱層疊的複數個樹脂膜10時加壓。 Then, a pressure applying heat treatment is performed to pressurize when the plurality of laminated resin films 10 are heated.

因此,當樹脂流入以填充主動組件2與樹脂膜10之間的間隙以及成為一體時,樹脂膜10相互黏著及成一體。 Therefore, when the resin flows in to fill the gap between the active component 2 and the resin film 10 and is integrated, the resin films 10 are adhered to each other and integrated.

此外,將金屬粉末15燒結以及在處理期間藉由熱而形成通路12。 Further, the metal powder 15 is sintered and the passage 12 is formed by heat during the treatment.

如此,製造圖1中所示的電路板1。 Thus, the circuit board 1 shown in Fig. 1 is fabricated.

此處,說明多層印刷電路板的製造方法及在第一比較實例製造後的多層印刷電路板。 Here, a method of manufacturing a multilayer printed wiring board and a multilayer printed wiring board after the first comparative example is manufactured will be described.

在第一比較實例中,如圖3中所示,二最低樹脂膜101、102的各別厚度d1、d2設定成同於其它樹脂膜10的厚度d3。亦即,製備之所有複數個樹脂膜10彼此相同。其它構造與本實施例的構造相同。 In the first comparative example, as shown in FIG. 3, the respective thicknesses d1, d2 of the two lowest resin films 101, 102 are set to be the same as the thickness d3 of the other resin film 10. That is, all of the plurality of resin films 10 prepared are identical to each other. Other configurations are the same as those of the present embodiment.

在此情形中,如圖4所示,在製造後的多層印刷電路板J1,在形成於二最低樹脂膜101、102的層疊部份上之 導電圖案11構成的傳輸線111b中、與在形成於其它樹脂膜103的層疊部份上之導電圖案11構成的傳輸線111a中,傳輸線111與位於其外側的導電圖案112、113之間的間隔不同。 In this case, as shown in FIG. 4, the multilayer printed circuit board J1 after fabrication is formed on the laminated portion of the two lowest resin films 101, 102. In the transmission line 111b composed of the conductive pattern 11 and the transmission line 111a composed of the conductive pattern 11 formed on the laminated portion of the other resin film 103, the interval between the transmission line 111 and the conductive patterns 112, 113 located outside thereof is different.

具體而言,在傳輸線111a中,在位於傳輸線111的外部之導電圖案11上方及下方的間隔都等於單一樹脂膜10的樹脂厚度T1。 Specifically, in the transmission line 111a, the interval above and below the conductive pattern 11 located outside the transmission line 111 is equal to the resin thickness T1 of the single resin film 10.

另一方面,在傳輸線111b中,在傳輸線111與位於其上方的導電圖案11之間的間隔等於其它訊號樹脂膜103的樹脂厚度T1。 On the other hand, in the transmission line 111b, the interval between the transmission line 111 and the conductive pattern 11 located above it is equal to the resin thickness T1 of the other signal resin film 103.

然後,在傳輸線111與位於其下方的導電圖案11之間的間隔等於二片樹脂膜10的樹脂厚度T2。 Then, the interval between the transmission line 111 and the conductive pattern 11 located thereunder is equal to the resin thickness T2 of the two resin films 10.

基於此理由,相較於其它樹脂膜103層疊的部份,在二最低樹脂膜101、102層疊的部份中,在傳輸線111b的層疊方向上位於二側的介電質的厚度不同,以及,在傳輸線111a的層疊方向上位於二側的介電質的厚度不同。 For this reason, in the portion where the two resin films 101 and 102 are laminated, the thickness of the dielectric on the two sides in the stacking direction of the transmission line 111b is different from that of the other resin film 103. The thickness of the dielectric located on both sides in the stacking direction of the transmission line 111a is different.

換言之,在其它樹脂膜103層疊之部份中,位於接地線112、113之間的傳輸線111係位於接地線112、113之間的中心。 In other words, in the portion where the other resin films 103 are laminated, the transmission line 111 located between the ground lines 112, 113 is located at the center between the ground lines 112, 113.

但是,在二最低樹脂膜101、102層疊之部份中,位於接地線112、113之間的傳輸線111設置成偏離接地線112、113之間的中心。 However, in the portion where the two lowest resin films 101, 102 are stacked, the transmission line 111 located between the ground lines 112, 113 is disposed away from the center between the ground lines 112, 113.

此處,假使在傳輸線的層疊方向上位於二側的介電質之厚度相同時,介電質厚度對於高頻訊號的傳輸線111之 阻抗具有的影響是相等的,以致於使用一般公式,即可計算傳輸線的阻抗。 Here, if the thicknesses of the dielectrics on the two sides in the stacking direction of the transmission line are the same, the dielectric thickness is for the transmission line 111 of the high-frequency signal. The impedance has the same effect, so that the impedance of the transmission line can be calculated using the general formula.

但是,由於在二最低樹脂膜101、102層疊的部份中,在傳輸線111b的層疊方向上位於二側中的介電質之厚度不同,所以,介電質厚度對於傳輸線111的阻抗之影響將不同。 However, since the thickness of the dielectric located in the two sides in the stacking direction of the transmission line 111b is different in the portion where the two lowest resin films 101, 102 are stacked, the influence of the dielectric thickness on the impedance of the transmission line 111 will be different.

基於此理由,對於形成於二最低樹脂膜101、102的層疊部份中的導電圖案11構成的傳輸線111b,用於計算阻抗的公式將變得複雜,且有效程度的範圍將窄化至給定的準確度。 For this reason, for the transmission line 111b formed of the conductive pattern 11 formed in the laminated portion of the two lowest resin films 101, 102, the formula for calculating the impedance will become complicated, and the range of the degree of effectiveness will be narrowed to a given Accuracy.

因此,在第一比較實施例的多層印刷電路板J1中,將產生用於計算傳輸線111的阻抗之公式變得複雜之問題,以及,電路設計將是非常複雜。 Therefore, in the multilayer printed circuit board J1 of the first comparative embodiment, the problem of generating a formula for calculating the impedance of the transmission line 111 becomes complicated, and the circuit design will be very complicated.

相反地,在本實施例的電路板1的製造方法中,首先,製備具有彼此相同的樹脂厚度d3之複數個樹脂膜,以用於二最低膜除外的複數個樹脂膜10之中的其它樹脂膜103。 In contrast, in the manufacturing method of the circuit board 1 of the present embodiment, first, a plurality of resin films having the same resin thickness d3 as each other are prepared for use in other resins among the plurality of resin films 10 excluding the two lowest films. Membrane 103.

然後,製備具有同於其它單一樹脂膜103的樹脂厚度d3之樹脂厚度d1、d2的總合之二樹脂膜,以用於二最低樹脂膜101、102。 Then, a total of two resin films having the resin thicknesses d1, d2 of the resin thickness d3 of the other single resin film 103 are prepared for use in the two lowest resin films 101, 102.

基於此理由,當觀看製造後的電路板1的剖面結構時,如圖1所示,在二最低樹脂膜101、102層疊的部份、以及其它樹脂膜103層疊的部份中,相鄰的樹脂膜10的導電圖案11的間隔T1和T2變成相等。 For this reason, when viewing the cross-sectional structure of the manufactured circuit board 1, as shown in FIG. 1, in the portion where the two lowest resin films 101, 102 are laminated, and the portion where the other resin film 103 is laminated, adjacent The intervals T1 and T2 of the conductive pattern 11 of the resin film 10 become equal.

換言之,配置在相鄰的樹脂膜10的導電圖案11之間的介電質之厚度T1和T2變成相等。 In other words, the thicknesses T1 and T2 of the dielectric disposed between the conductive patterns 11 of the adjacent resin films 10 become equal.

因此,根據本實施例,即使二最低樹脂膜101、102層疊的部份之導電圖案11與其它樹脂膜103層疊的部份之導電圖案11都作為高頻訊號的傳輸線111時,則傳輸線111與位於傳輸線111的外面之導電圖案11之間的間隔配置有高頻訊號的所有傳輸線111中之單片的其它樹脂膜10之樹脂厚度。 Therefore, according to the present embodiment, even if the portion of the conductive pattern 11 in which the two minimum resin films 101, 102 are laminated and the conductive pattern 11 in which the other resin film 103 is laminated serves as the transmission line 111 of the high-frequency signal, the transmission line 111 and The interval between the conductive patterns 11 located outside the transmission line 111 is disposed with the resin thickness of a single piece of the other resin film 10 among all the transmission lines 111 of the high-frequency signal.

結果,配置在傳輸線111與位於傳輸線111的外面之導電圖案11之間的介電質之厚度製成相等的,以及,使得所有傳輸線111中介電質厚度對阻抗具有的影響相等。 As a result, the thickness of the dielectric disposed between the transmission line 111 and the conductive pattern 11 located outside the transmission line 111 is made equal, and the dielectric thickness of all the transmission lines 111 has the same influence on the impedance.

因此,容易計算阻抗,且能夠使考慮阻抗的電路設計容易。 Therefore, it is easy to calculate the impedance, and it is possible to make the circuit design considering the impedance easy.

[第二實施例] [Second embodiment]

相對於第一實施例之最低樹脂膜101、102的厚度,本實施例改變二最低樹脂膜101、102的厚度。 The present embodiment changes the thickness of the two lowest resin films 101, 102 with respect to the thickness of the lowest resin films 101, 102 of the first embodiment.

在本實施例中,如圖5所示,在製造多層印刷電路板1的製備處理中,製備均具有不同樹脂厚度d1、d2且具有之樹脂厚度d1、d2的總合同於其它單一樹脂膜103的樹脂厚度d3之二樹脂膜,以用於二最低樹脂膜101、102。 In the present embodiment, as shown in FIG. 5, in the preparation process for manufacturing the multilayer printed circuit board 1, a total contract for preparing the resin thicknesses d1, d2 and having the resin thicknesses d1, d2 is obtained from the other single resin film 103. A resin film having a resin thickness d3 of two is used for the two lowest resin films 101, 102.

舉例而言,在施壓加熱之前的其它單一樹脂膜103之樹脂厚度d3設定於50μm(微米),以及,二最低樹脂膜 101、102之各樹脂厚度d1、d2分別設定於20μm及30μm。 For example, the resin thickness d3 of the other single resin film 103 before the pressure heating is set to 50 μm (micrometer), and the second minimum resin film The resin thicknesses d1 and d2 of 101 and 102 were set to 20 μm and 30 μm, respectively.

其餘與第一實施例相同。 The rest is the same as the first embodiment.

因而,也在本實施例中,如圖6所示,其它樹脂膜103的各樹脂厚度T1及二最低樹脂膜101、102的樹脂厚度之總合T2變成等於製造後的電路板1中的單一樹脂膜10的樹脂厚度T1。 Therefore, also in the present embodiment, as shown in Fig. 6, the total thickness T2 of each resin thickness T1 of the other resin film 103 and the resin thickness of the two lowest resin films 101, 102 becomes equal to a single one in the circuit board 1 after manufacture. The resin thickness of the resin film 10 is T1.

因此,本實施例也能取得與第一實施例相同的功效。 Therefore, the present embodiment can also achieve the same effects as the first embodiment.

[第三實施例] [Third embodiment]

相對於第一實施例之主動組件2,本實施例改變主動組件2的定位。 This embodiment changes the positioning of the active component 2 with respect to the active component 2 of the first embodiment.

亦即,如圖7所示,主動組件2安裝於本實施例的電路板1中的電路板之外表面上。 That is, as shown in Fig. 7, the active unit 2 is mounted on the outer surface of the circuit board in the circuit board 1 of the present embodiment.

其餘結構與第一實施例相同。 The rest of the structure is the same as that of the first embodiment.

如圖8所示,藉由改變第一實施例中所述的製造方法以將主動組件2定位於電路板的外表面上,而製造此電路板1。 As shown in FIG. 8, the circuit board 1 is manufactured by changing the manufacturing method described in the first embodiment to position the active component 2 on the outer surface of the circuit board.

具體而言,在製造電路板1之後,藉由銲接等等,將主動組件2的下電極2a連接至電路板的外表面之導電圖案11。 Specifically, after the circuit board 1 is manufactured, the lower electrode 2a of the active component 2 is attached to the conductive pattern 11 of the outer surface of the circuit board by soldering or the like.

在本實施例中,由於主動組件2的定位除外,電路板1的結構與第一實施例相同,所以,也能取得與第一實施例相同的功效。 In the present embodiment, since the positioning of the active unit 2 is excluded, the structure of the circuit board 1 is the same as that of the first embodiment, so that the same effects as those of the first embodiment can be obtained.

[第四實施例] [Fourth embodiment]

本實施例是第二及第三實施例的組合。 This embodiment is a combination of the second and third embodiments.

亦即,如圖9所示,主動組件2安裝於本實施例的電路板1中的電路板之外表面上。 That is, as shown in FIG. 9, the active unit 2 is mounted on the outer surface of the circuit board in the circuit board 1 of the present embodiment.

此外,如圖10所示,在製造多層印刷電路板1的製備處理中,製備均具有不同樹脂厚度d1、d2且具有之樹脂厚度d1、d2的總合同於其它單一樹脂膜103的樹脂厚度d3之二樹脂膜,以用於二最低樹脂膜101、102。 Further, as shown in FIG. 10, in the preparation process for manufacturing the multilayer printed circuit board 1, the resin thickness d3 which is contracted to the other single resin film 103, which has different resin thicknesses d1, d2 and which have the resin thicknesses d1, d2, is prepared. The resin film is used for the two lowest resin films 101 and 102.

基於此理由,在本實施例的電路板1中主動組件2的定位除外,電路板1的結構與第二實施例相同。 For this reason, except for the positioning of the active component 2 in the circuit board 1 of the present embodiment, the structure of the circuit board 1 is the same as that of the second embodiment.

因此,本實施例也能取得與第一實施例相同的功效。 Therefore, the present embodiment can also achieve the same effects as the first embodiment.

[第五實施例] [Fifth Embodiment]

如圖11所示,本實施例的多層印刷電路板201在其二側上具有導電圖案11,且作為用於傳送高頻訊號的電纜。 As shown in FIG. 11, the multilayer printed circuit board 201 of the present embodiment has a conductive pattern 11 on both sides thereof and serves as a cable for transmitting a high frequency signal.

此多層印刷電路板201具有類似於第一實施例的結構,其中,複數個樹脂膜10層疊,在樹脂膜10中,導電圖案11僅形成於一側上。 This multilayer printed circuit board 201 has a structure similar to that of the first embodiment in which a plurality of resin films 10 are laminated, and in the resin film 10, the conductive patterns 11 are formed only on one side.

形成於多層印刷電路板201的二側上之導電圖案11構成接地線112、113,以及,在多層印刷電路板201的層疊方向上位於中心的導電圖案11構成高頻訊號的傳輸線111。 The conductive patterns 11 formed on both sides of the multilayer printed circuit board 201 constitute ground lines 112, 113, and the conductive patterns 11 located at the center in the stacking direction of the multilayer printed circuit board 201 constitute a transmission line 111 of high frequency signals.

具體而言,在多層印刷電路板201中有五片樹脂膜10相層疊。 Specifically, five resin films 10 are laminated in the multilayer printed circuit board 201.

二最低樹脂膜101、102相層疊,以致於未形成導電圖案11的側10b彼此相面對。 The two lowest resin films 101, 102 are laminated such that the sides 10b where the conductive patterns 11 are not formed face each other.

二最低樹脂膜除外的其它樹脂膜103層疊,以致於形成有導電圖案11之側10a以及未形成導電圖案11之側10b彼此面對。 The other resin films 103 excluding the two lowest resin films are laminated such that the side 10a on which the conductive patterns 11 are formed and the side 10b on which the conductive patterns 11 are not formed face each other.

形成於始於底部之第三片的其它樹脂膜103上之導電圖案11中之一指定給高頻訊號的傳輸線111。 One of the conductive patterns 11 formed on the other resin film 103 of the third sheet starting from the bottom is assigned to the transmission line 111 of the high frequency signal.

此外,接地線112、113經由形成在各樹脂膜10中的通路12而電連接。 Further, the ground lines 112 and 113 are electrically connected via vias 12 formed in the respective resin films 10.

如圖12所示,以同於第一實施例之製造方法,製造具有此結構的多層印刷電路板201。 As shown in Fig. 12, a multilayer printed circuit board 201 having this structure was fabricated in the same manner as the manufacturing method of the first embodiment.

亦即,也在本實施例中,製備具有的樹脂厚度d1、d2的總合同於其它樹脂膜103的樹脂厚度d3之二樹脂膜,以用於二最低樹脂膜101、102。 That is, also in the present embodiment, a resin film having a resin thickness d1, d2 having a total resin thickness d3 of the other resin film 103 is prepared for use in the two lowest resin films 101, 102.

此時,二最低樹脂膜101、102的各樹脂厚度d1、d2可以設定為其它單一樹脂膜103的樹脂厚度d3的一半,或是可為不同的厚度。 At this time, the respective resin thicknesses d1 and d2 of the two lowest resin films 101 and 102 may be set to be half of the resin thickness d3 of the other single resin film 103, or may be different thicknesses.

此處,說明第二比較實例中之多層印刷電路板的製造方法以及製造後的多層印刷電路板。 Here, a method of manufacturing the multilayer printed circuit board in the second comparative example and a multilayer printed circuit board after the manufacture will be described.

在第二比較實例中,如圖13所示,二最低樹脂膜101、102的各別厚度d1、d2設定成與其它樹脂膜10的厚度d3相同。亦即,製備的所有複數個樹脂膜10是相同 的。其餘構造與本實施例相同。 In the second comparative example, as shown in FIG. 13, the respective thicknesses d1, d2 of the two lowest resin films 101, 102 are set to be the same as the thickness d3 of the other resin film 10. That is, all of the plurality of resin films 10 prepared are the same of. The rest of the configuration is the same as this embodiment.

在此情形中,如圖14所示,由於奇數片的樹脂膜10相層疊,所以,在製造後的多層印刷電路板J201中,在傳輸線111與位於傳輸線111外面的接地線112、113之間的間隔在層疊方向上的一側與另一側中是不同的。 In this case, as shown in FIG. 14, since the odd-numbered resin films 10 are stacked, in the multilayer printed circuit board J201 after fabrication, between the transmission line 111 and the ground lines 112, 113 located outside the transmission line 111. The interval is different in one side in the stacking direction from the other side.

亦即,高頻訊號的傳輸線111變成在多層印刷電路板J201的層疊方向上偏離中心。 That is, the transmission line 111 of the high-frequency signal becomes off-center in the stacking direction of the multilayer printed circuit board J201.

基於此理由,在多層印刷電路板J201中,對於傳輸線,用於計算阻抗的公式變得複雜,且操作參數的範圍將變窄。 For this reason, in the multilayer printed circuit board J201, the equation for calculating the impedance becomes complicated for the transmission line, and the range of the operation parameters will be narrowed.

因此,在第二比較實例的多層印刷電路板J201中,將產生用於計算傳輸線111的阻抗之公式變複雜之問題,且電路設計將非常複雜。 Therefore, in the multilayer printed circuit board J201 of the second comparative example, a problem that the equation for calculating the impedance of the transmission line 111 is complicated becomes complicated, and the circuit design will be very complicated.

相反地,本實施例與第一實施例的電路板201的製造方法製備均具有相同的樹脂厚度d3之複數個樹脂膜以用於其它樹脂膜103,以及,製造具有的樹脂厚度d1、d2的總合同於其它樹脂膜103的樹脂厚度d3之二樹脂膜,以用於二最低樹脂膜101、102。 On the contrary, the present embodiment and the manufacturing method of the circuit board 201 of the first embodiment are prepared by using a plurality of resin films each having the same resin thickness d3 for the other resin film 103, and manufacturing the resin thicknesses d1 and d2. The resin film of the resin film thickness d3 of the other resin film 103 is mainly contracted for the two lowest resin films 101 and 102.

基於此理由,當觀看製造後的電路板201之剖面結構時,如圖11所示,在二最低樹脂膜101、102層疊的部份中與在其它樹脂膜103層疊的部份中,相鄰樹脂膜10的導電圖案11之間隔T1和T2變成相等。 For this reason, when viewing the cross-sectional structure of the manufactured circuit board 201, as shown in FIG. 11, in the portion where the two lowest resin films 101, 102 are laminated and the portion laminated on the other resin film 103, adjacent The intervals T1 and T2 of the conductive patterns 11 of the resin film 10 become equal.

換言之,在相鄰樹脂膜10的導電圖案11之間的介電質之厚度T1和T2變成相等。 In other words, the thicknesses T1 and T2 of the dielectric between the conductive patterns 11 of the adjacent resin films 10 become equal.

因此,當考慮構成多層印刷電路板201之層疊的樹脂膜10的片數為奇數時,傳輸線111與位於傳輸線111的外面之接地線112、113的間隔可以製成相等的。 Therefore, when the number of sheets of the resin film 10 constituting the multilayer printed circuit board 201 is considered to be an odd number, the interval between the transmission line 111 and the ground lines 112, 113 located outside the transmission line 111 can be made equal.

亦即,高頻訊號的傳輸線111在多層印刷電路板J201的層疊方向上配置於中心。 In other words, the transmission line 111 of the high-frequency signal is disposed at the center in the stacking direction of the multilayer printed circuit board J201.

因此,容易計算阻抗,且能夠使考慮阻抗的電路設計容易。 Therefore, it is easy to calculate the impedance, and it is possible to make the circuit design considering the impedance easy.

[其它實施例] [Other Embodiments]

本發明不侷限於上述實施例,在不悖離本發明的範圍之下,可以適當地改變。 The present invention is not limited to the above embodiments, and may be appropriately changed without departing from the scope of the invention.

(1)在各上述實施例中,雖然二樹脂膜101、102配置在多層印刷電路板1、201的最低部份,但是,二樹脂膜101、102可以在配置最低部份以外的地方,例如,在多層印刷電路板1、201的中心。 (1) In the above embodiments, although the two resin films 101, 102 are disposed at the lowest portion of the multilayer printed circuit board 1, 201, the two resin films 101, 102 may be located outside the lowest portion of the configuration, for example, At the center of the multilayer printed circuit board 1, 201.

(2)雖然在第一至第四實施例中採用接地線112、113配置在傳輸線111的上方及下方的構造,但是,本發明不侷限於此構造。 (2) Although the grounding lines 112 and 113 are disposed above and below the transmission line 111 in the first to fourth embodiments, the present invention is not limited to this configuration.

當高頻訊號的傳輸線111由多層印刷電路板的表面上之導電圖案11構成時,接地線將僅在垂直方向上配置於一側上。 When the transmission line 111 of the high frequency signal is constituted by the conductive pattern 11 on the surface of the multilayer printed circuit board, the ground line will be disposed on only one side in the vertical direction.

(3)雖然在上述的實施例中所有複數個的樹脂膜10由熱塑樹脂製成,但是,所有複數個的樹脂膜10可由熱固樹脂製成。 (3) Although all of the plurality of resin films 10 are made of a thermoplastic resin in the above embodiment, all of the plurality of resin films 10 may be made of a thermosetting resin.

此外,熱塑樹脂製成的樹脂膜可與熱固樹脂製成的樹脂膜一起使用作為樹脂膜10。 Further, a resin film made of a thermoplastic resin can be used as the resin film 10 together with a resin film made of a thermosetting resin.

(4)各上述實施例不是相互無關的,且除了明確不當的情形外,可以適當地相結合。 (4) Each of the above embodiments is not mutually exclusive, and may be combined as appropriate in addition to the case of being unambiguous.

此外,在各上述實施例中,構成實施例的元件不一定是不可少的,但是,清楚說明元件是不可少的情形除外,或是清楚地說明元件是理論上不可少的情形除外。 Further, in each of the above embodiments, the elements constituting the embodiment are not necessarily indispensable, except that the case where the element is indispensable is clearly stated, or the case where the element is theoretically indispensable is clearly explained.

2‧‧‧主動組件 2‧‧‧Active components

2a‧‧‧下電極 2a‧‧‧ lower electrode

10‧‧‧樹脂膜 10‧‧‧ resin film

10a‧‧‧側 10a‧‧‧ side

10b‧‧‧側 10b‧‧‧ side

11‧‧‧導電圖案 11‧‧‧ conductive pattern

13‧‧‧通路孔 13‧‧‧ access hole

14‧‧‧通孔 14‧‧‧through hole

15‧‧‧金屬粉末 15‧‧‧Metal powder

101‧‧‧最低樹脂膜 101‧‧‧Minyl resin film

102‧‧‧最低樹脂膜 102‧‧‧Minyl resin film

103‧‧‧樹脂膜 103‧‧‧ resin film

d1、d2、d3‧‧‧樹脂厚度 D1, d2, d3‧‧‧ resin thickness

Claims (2)

一種多層印刷電路板,包括:複數個樹脂膜(10);以及導電圖案(11),僅形成於各該樹脂膜的一側上,且構成3kHz或更高的高頻訊號的傳輸線(111)及接地線(112,113);其中,在該複數個樹脂膜中,二個樹脂膜(101,102)層疊,令未形成該等導電圖案的側(10b)會彼此面對;在該複數個樹脂膜中該二個樹脂膜除外的其它樹脂膜(103)層疊,令形成有該等導電圖案的側(10a)與未形成該等導電圖案的側彼此面對;在該其它樹脂膜層疊的部份中,在層疊方向上該等導電圖案之間的所有間隔(T1)是相同的;以及在該二個樹脂膜層疊的部份中,在該層疊方向上該等導電圖案之間的間隔(T2)與在該其它樹脂膜層疊的該部份中的間隔(T1)相同。 A multilayer printed circuit board comprising: a plurality of resin films (10); and a conductive pattern (11) formed only on one side of each of the resin films and constituting a transmission line (111) of a high frequency signal of 3 kHz or higher And a grounding wire (112, 113); wherein, in the plurality of resin films, the two resin films (101, 102) are laminated such that sides (10b) not forming the conductive patterns face each other; The other resin films (103) except the two resin films in the resin film are laminated such that the side (10a) on which the conductive patterns are formed and the side on which the conductive patterns are not formed face each other; the other resin film is laminated In the portion, all the intervals (T1) between the conductive patterns are the same in the stacking direction; and in the portion where the two resin films are stacked, between the conductive patterns in the stacking direction The interval (T2) is the same as the interval (T1) in the portion in which the other resin film is laminated. 一種多層印刷電路板的製造方法,方法,包括:製備處理,用於製備複數個樹脂膜(10),其中,導電圖案(11)僅形成於各該樹脂膜的一側上,且構成3kHz或更高的高頻訊號的傳輸線(111)及接地線(112,113);層疊處理,用於層疊該複數個樹脂膜;以及施壓加熱處理,在加熱該層疊的複數個樹脂膜時施壓;其中,在該複數個樹脂膜中,在該層疊處理中,將二 個樹脂膜(101,102)層疊,令未形成該等導電圖案的側(10b)彼此面對;在該層疊處理中,在該複數個樹脂膜中該二個樹脂膜除外的其它樹脂膜(103)層疊,令形成有該等導電圖案的側(10a)與未形成該等導電圖案的側彼此面對;在該製備處理中,製備均具有該相同的樹脂厚度(d3)之複數個樹脂膜,以用於該等其它樹脂膜;以及在該製備處理中,製備具有的樹脂厚度(d1,d2)總合與該其它單一樹脂膜的樹脂厚度相同的二個樹脂膜,以用於該等二個樹脂膜。 A manufacturing method of a multilayer printed circuit board, comprising: a preparation process for preparing a plurality of resin films (10), wherein a conductive pattern (11) is formed only on one side of each of the resin films, and constitutes 3 kHz or a higher high frequency signal transmission line (111) and a ground line (112, 113); a lamination process for laminating the plurality of resin films; and a pressure heat treatment for applying pressure when heating the stacked plurality of resin films Wherein, in the plurality of resin films, in the lamination process, two The resin films (101, 102) are laminated such that sides (10b) where the conductive patterns are not formed face each other; in the lamination process, other resin films excluding the two resin films in the plurality of resin films ( 103) laminating such that sides (10a) on which the conductive patterns are formed and sides on which the conductive patterns are not formed face each other; in the preparation process, a plurality of resins each having the same resin thickness (d3) are prepared a film for use in the other resin films; and in the preparation process, preparing two resin films having a resin thickness (d1, d2) which is the same as a resin thickness of the other single resin film, for use in the preparation Wait for two resin films.
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016219452A (en) * 2015-05-14 2016-12-22 富士通株式会社 Multilayer substrate and manufacturing method for multilayer substrate
CN105472886B (en) * 2015-11-13 2018-08-28 惠州市金百泽电路科技有限公司 A kind of built-in active device PCB plate production method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023222A (en) * 2001-07-09 2003-01-24 Ibiden Co Ltd Printed circuit board
JP2004119507A (en) * 2002-09-24 2004-04-15 Denso Corp Circuit board structure

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2857237B2 (en) * 1990-08-10 1999-02-17 古河電気工業株式会社 Method for manufacturing multilayer circuit board
CN1224567A (en) * 1996-06-07 1999-07-28 旭化成工业株式会社 Resin-carrying metal foil for multilayered wiring board, process for mfg. same, multilayered wiring board, and electronic device
DE69629061T2 (en) * 1996-06-07 2004-05-13 Asahi Kasei Kabushiki Kaisha RESIN-CARRYING METAL FILM FOR MULTI-LAYER CIRCUIT BOARD, METHOD FOR THEIR PRODUCTION, MULTI-LAYER CIRCUIT BOARD, AND ELECTRONIC DEVICE
JP3407737B2 (en) 2000-12-14 2003-05-19 株式会社デンソー Multilayer substrate manufacturing method and multilayer substrate formed by the manufacturing method
JP3473601B2 (en) 2000-12-26 2003-12-08 株式会社デンソー Printed circuit board and method of manufacturing the same
JP3867523B2 (en) 2000-12-26 2007-01-10 株式会社デンソー Printed circuit board and manufacturing method thereof
JP3900862B2 (en) 2001-06-27 2007-04-04 株式会社デンソー Method for manufacturing printed circuit board
JP2003204209A (en) * 2002-01-07 2003-07-18 Kyocera Corp Wiring board for high frequency
JP3855774B2 (en) 2002-01-15 2006-12-13 株式会社デンソー Multilayer substrate manufacturing method
JP4045143B2 (en) * 2002-02-18 2008-02-13 テセラ・インターコネクト・マテリアルズ,インコーポレイテッド Manufacturing method of wiring film connecting member and manufacturing method of multilayer wiring board
JP3969192B2 (en) 2002-05-30 2007-09-05 株式会社デンソー Manufacturing method of multilayer wiring board
JP4029759B2 (en) * 2003-04-04 2008-01-09 株式会社デンソー Multilayer circuit board and manufacturing method thereof
KR20050112122A (en) * 2003-04-07 2005-11-29 이비덴 가부시키가이샤 Multilayer printed wiring board
JP2006073763A (en) * 2004-09-01 2006-03-16 Denso Corp Manufacturing method for multilayer board
JP2006093438A (en) * 2004-09-24 2006-04-06 Denso Corp Printed substrate and its production method
JP2006210533A (en) 2005-01-26 2006-08-10 Komatsu Lite Seisakusho:Kk Multilayer printed board and its manufacturing method
WO2006080073A1 (en) * 2005-01-27 2006-08-03 Matsushita Electric Industrial Co., Ltd. Multi-layer circuit substrate manufacturing method and multi-layer circuit substrate
JP4774920B2 (en) * 2005-10-31 2011-09-21 ソニー株式会社 Optical transceiver
JP4881445B2 (en) * 2007-12-05 2012-02-22 三菱樹脂株式会社 Multilayer wiring board having a cavity portion
JP4473935B1 (en) 2009-07-06 2010-06-02 新光電気工業株式会社 Multilayer wiring board
JP2011249745A (en) * 2010-04-28 2011-12-08 Denso Corp Multilayer substrate
WO2012124421A1 (en) * 2011-03-14 2012-09-20 株式会社村田製作所 Flexible multilayer substrate
CN103650651B (en) * 2011-07-05 2016-08-17 株式会社村田制作所 flexible multilayer substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023222A (en) * 2001-07-09 2003-01-24 Ibiden Co Ltd Printed circuit board
JP2004119507A (en) * 2002-09-24 2004-04-15 Denso Corp Circuit board structure

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