JP2020072103A - Wiring board - Google Patents

Abstract

To provide a wiring board in which a semiconductor device can normally function.SOLUTION: A wiring board comprises: a laminate 2 in which three or more layers of insulating layers 6 including a first insulating layer 6a that is the first layer from the top and a second insulating layer 6b that is the second layer are stacked with each other; wiring areas 8 that are located between a top face and an under surface of the laminate 2 and between the insulating layers 6; electrodes 3 that are located in the wiring area 8 of the top face of the first insulating layer 6a along an outer peripheral edge of the wiring area 8; wiring conductors 4 that are located in the wiring area 8; and via holes 7 that electrically connect the upper and lower wiring conductors 4 of the insulating layer 6. The electrodes 3 are electrically connected to the wiring conductor 4 on the top face of the second insulating layer 6b with the via holes 7 located immediately below the electrodes 3, of the via holes 7, and the wiring area 8 located on at least one of the plurality of insulating layers 6 that is a layer lower than the second insulating layer 6b is located to be within the wiring area 8 located on the first insulating layer 6a in plain perspective.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a wiring board.

  2. Description of the Related Art In recent years, some laminated wiring boards used for medical inspection devices and the like are equipped with a semiconductor element that images an X-ray transmitted through an inspection object that has received radiation such as X-rays. The laminated wiring board has a structure in which insulating layers and wiring conductors are alternately laminated. Such a wiring board and a semiconductor element have the same shape in plan view, and the semiconductor element may be mounted on the wiring board so as to overlap each other.

JP, 2014-150087, A

  In an inspection apparatus, the above-described semiconductor elements may be arranged vertically and horizontally without a gap, and may be arranged so that radiation does not leak from between adjacent semiconductor elements. However, the wiring conductor may be exposed from between the insulating layers that are laminated on the wiring board. In such a case, when wiring boards having the same size as the semiconductor element are arranged vertically and horizontally without any gap, exposed wiring conductors may be short-circuited and the semiconductor element may not function properly. is there.

  The wiring board according to the present disclosure includes a laminated body in which three or more insulating layers including a first insulating layer that is the first layer from the top and a second insulating layer that is the second layer are laminated together, and an upper surface and a lower surface of the laminated body. And a wiring region located between the insulating layers, an electrode located along the outer peripheral edge of the wiring region in the wiring region on the upper surface of the first insulating layer, and a wiring located in the wiring region A conductor and a plurality of via holes that are located in a plurality of insulating layers and electrically connect wiring conductors located above and below the insulating layer, and the electrodes are a plurality of via holes. Is electrically connected to a wiring conductor located on the upper surface of the second insulating layer by a via hole located directly below the electrode, and is located in at least one of lower layers than the second insulating layer among the plurality of insulating layers. The wiring area that is being insulated is the first insulation when seen through a plane. And it is characterized in that it is positioned to fit with and wiring region positioned.

  According to the present disclosure, it is possible to provide a wiring board that allows a semiconductor element to function normally.

FIG. 1 is a schematic cross-sectional view showing an exemplary embodiment of a wiring board according to the present disclosure. FIG. 2 is a schematic cross-sectional view showing a state in which the wiring boards of the present disclosure on which the semiconductor element is mounted are adjacent to each other. FIG. 3 is a plan view showing a part of the wiring board of the present disclosure. FIG. 4 is a plan view showing a part of the wiring board of the present disclosure. FIG. 5 is a plan view showing a part of the wiring board of the present disclosure.

  An embodiment example of the wiring board 1 of the present disclosure will be described based on FIGS. 1 to 5. FIG. 1 is a schematic cross-sectional view showing a wiring board 1. FIG. 2 is a schematic cross-sectional view showing a state in which the wiring boards 1 on which the semiconductor elements S are mounted are lined up so that their side surfaces are in contact with each other.

  As shown in FIG. 2, the wiring boards 1 are arranged in a state in which their side surfaces are in contact with each other, for example, in a medical inspection device, and the semiconductor elements S mounted on the upper surface are arranged so that there are no gaps therebetween. It has a function. Although FIG. 2 shows an example in which three wiring boards 1 are arranged side by side for convenience of description, in reality, about 500 to 5000 wiring boards 1 are arranged vertically and horizontally.

  The wiring board 1 includes a laminate 2, electrodes 3, wiring conductors 4, and solder resists 5.

  The laminated body 2 is configured by laminating three or more insulating layers 6 including a first insulating layer 6a that is the first layer and a second insulating layer 6b that is the second layer from the top. The laminated body 2 has a function of ensuring an insulating property between adjacent wiring conductors 4 while ensuring a region where the wiring conductor 4 is provided between the insulating layers 6.

The insulating layer 6 contains an insulating material such as an allyl-modified polyphenylene ether resin, a polyimide resin, an epoxy resin, or a bismaleimide triazine resin. The insulating material contains insulating particles. Examples of the insulating particles include silica (SiO ₂ ) and alumina (AlO ₃ ). The insulating layer 6 contains glass fiber. Although it does not need to contain glass fiber, it is advantageous to contain glass fiber from the viewpoint of ensuring the flatness and rigidity of the wiring board 1.

  In this example, an example is shown in which eight insulating layers 6 including the first insulating layer 6a and the second insulating layer 6b are stacked, but the number of stacked layers may be adjusted as necessary. The thickness of each insulating layer 6 is set to, for example, 50 to 200 μm.

  A plurality of via holes 7 that electrically connect the wiring conductors 4 located above and below the insulating layer 6 are located in each insulating layer 6. The via-hole conductor 7 a is located inside the via-hole 7. That is, the via hole 7 is a conductive path for electrically connecting the wiring conductors 4 located above and below via the insulating layer 6. The diameter of the via hole 7 is set to, for example, 50 to 200 μm.

  Wiring regions 8 are respectively located between the upper surface and the lower surface of the laminated body 2 and between the insulating layers 6. Inside the wiring region 8, an electrode 3, a wiring conductor 4, and an external electrode 9 described later are located. That is, the wiring region 8 is a region where the conductive path in the wiring board 1 is located. The wiring region 8 is located inside the outer peripheral edge of the insulating layer 6 by a predetermined distance, and is not exposed to the side surface of the wiring substrate 1.

  In the present disclosure, the wiring region 8 located in at least one of the layers lower than the second insulating layer 6b is located so as to fit within the wiring region 8 located in the first insulating layer 6a when seen in a plan view. ing.

  In other words, the wiring conductor 4 located in at least one layer lower than the second insulating layer 6b is closer to the center of the insulating layer 6 than the wiring conductor 4 located in the first insulating layer 6a when seen in a plan view. It can be said that it is located.

  In FIG. 1, an example in which the wiring region 8 located in all layers below the second insulating layer 6b is located so as to fit within the wiring region 8 located in the first insulating layer 6a in plan perspective Is shown. In other words, the wiring conductors 4 located in all layers below the second insulating layer 6b are located closer to the center of the insulating layer 6 than the wiring conductors 4 located in the first insulating layer 6a. I can say. As a result, the shortest distance between the outer peripheral edge of the wiring board 1 and the wiring conductor 4 below the second insulating layer 6b is the shortest distance between the outer peripheral edge of the wiring board 1 and the wiring conductor 4 located on the upper surface of the first insulating layer 6a. Greater than the interval.

  As shown in FIG. 3, the electrode 3 is located in the wiring region 8 on the upper surface of the first insulating layer 6a. The electrode 3 is connected to the electrode of the semiconductor element S by, for example, solder. As a result, the semiconductor element S and the wiring board 1 are electrically connected. The electrode 3 has, for example, a circular shape. The diameter of the electrode 3 is set to, for example, 200 to 400 μm.

  The electrode 3 includes a first electrode 3a located along the outer peripheral edge of the wiring region 8 and a second electrode 3b located closer to the center than the first electrode 3a. In other words, the first electrode 3a is located on the outermost periphery in the wiring region 8.

  The first electrode 3a is electrically connected to the wiring conductor 4 located on the upper surface of the second insulating layer 6b through the via hole 7 located immediately below. This is because the electrodes 3 are arranged in the wiring region 8 as densely as possible, so that a region for providing a conductive path is secured from the first electrode 3a toward the center of the first insulating layer 6a in plan view. Because it is difficult to do.

  As shown in FIG. 4, the wiring conductor 4 on the upper surface of the second insulating layer 6b is connected to the first via land 4a electrically connected to the first electrode 3a and the first via land 4a electrically connected to the second electrode 3b. It has two via lands 4b.

  The first via land 4a has an oval shape having a longitudinal direction from the outer peripheral side to the central side of the second insulating layer 6b, for example. The first via land 4a is connected to the via hole 7 directly below the first electrode 3a on the upper surface on the outer peripheral side. The first via land 4a is connected to the via hole 7 connected to the wiring conductor 4 in the lower layer on the lower surface on the center side.

  That is, in the second insulating layer 6b, the first via land 4a is located from the outer peripheral side toward the central side, and has a function of bringing the conductive path on the outer peripheral side closer to the central side. Since the area of the second via land 4b is smaller than the area of the electrode 3, it is possible to secure a region for providing the first via land 4a which is a conductive path for bringing the conductive path on the outer peripheral side closer to the center side. Depends on.

  The second via land 4b has, for example, a circular shape. The second via land 4b is connected to the via hole 7 directly below the second electrode 3b on the upper surface. The second via land 4b is connected to the via hole 7 which is connected to the wiring conductor 4 in the lower layer on the lower surface. The diameter of the second via land 4b is set to, for example, 150 to 350 μm.

  As described above, since the first via land 4a has a function of bringing the conductive path on the outer peripheral side closer to the center side, the wiring region 8 located in the insulating layer 6 below the second insulating layer 6b. 5 can be positioned so as to fit within the wiring region 8 located on the first insulating layer 6a as seen in a plan view, as shown in FIG.

  The wiring conductors 4 are located in the respective wiring regions 8. The wiring conductor 4 mainly constitutes a conductive path of the wiring board 1.

  The wiring conductor 4 contains a good conductive metal such as copper foil. The thickness of the wiring conductor 4 is set to, for example, 10 to 20 μm.

  A part of the wiring conductor 4 located on the lower surface of the laminated body 2 has an external electrode 9 connected to an external substrate. The external electrode 9 is connected to the external substrate via solder or a connector. As a result, the semiconductor element S and the external substrate are electrically connected to each other via the wiring conductor 1.

  The solder resist 5 is located on the upper surface and the lower surface of the laminated body 2, although this is not an essential requirement in the present disclosure. The solder resist 5 has a first opening 5 a exposing the electrode 3 and a second opening 5 b exposing the external electrode 9.

  The solder resist 5 has a function of reducing damage to the wiring conductor 4 due to heat treatment when mounting the semiconductor element S, for example. The respective openings may have different shapes. The openings having different shapes can also be used as alignment marks when mounting the semiconductor element S, for example.

  Such a wiring board 1 is formed through the following steps, for example.

  First, a prepreg for the insulating layer 6 is prepared and a via hole 7 is formed by laser processing. The diameter of the via hole 7 is set to, for example, about 50 to 200 μm.

  The prepreg has a plurality of product areas so that a plurality of wiring boards 1 can be simultaneously formed.

  Next, the via hole 7 is filled with a conductor paste to form a through-hole conductor 7a.

  Next, conductor patterns are transferred and embedded on the upper surface and the lower surface of the prepreg. At this time, the through-hole conductor 7a and the conductor pattern are electrically connected. The conductor pattern is a copper foil formed in a predetermined pattern on a transfer film. As a result, the unit 1 having the wiring conductors 4 on the upper surface and the lower surface of the prepreg is formed.

  Next, the same processing as above is performed to prepare the unit 2 having the through-hole conductor 7a and the wiring conductor 4 only on one side of the prepreg. Then, the unit 2 is laminated on the unit 1 in a state where the surface of the unit 2 on which the wiring conductor 4 is not formed and the upper surface of the unit 1 overlap each other.

  Next, the unit 1 and the unit 2 are brought into close contact with each other by applying pressure from above the unit 2 under heating.

  Next, the unit 3 having the through-hole conductor 7a and the wiring conductor 4 only on one side of the prepreg is prepared. Then, the unit 3 is laminated on the unit 1 in a state where the surface of the unit 3 on which the wiring conductor 4 is not formed and the lower surface of the unit 1 overlap each other.

  Next, pressure is applied from above the unit 3 to bring the unit 1 and the unit 3 into close contact with each other.

  Similarly, a panel-shaped laminated body is formed by preparing a unit having the wiring conductors 4 only on one surface side and sequentially laminating the units until the required number of layers is obtained. A plurality of electrodes 3 formed at the same time as the wiring conductors 4 are formed on the uppermost unit of the panel-shaped laminate. Thereby, the plurality of electrodes 3 are located on the upper surface of the panel-shaped laminate.

  Next, the solder resist 5 is formed on the upper surface and the lower surface of the panel-shaped laminate. The solder resist 5 is, for example, a film of a thermosetting resin having a photosensitivity such as an acrylic modified epoxy resin attached to the upper surface and the lower surface of the panel-shaped laminate, and the first opening 5a exposing the electrode 3 by exposure and development. , And the second opening 5b exposing the external electrode 9 is formed, and then thermosetting is performed.

  Finally, the plurality of wiring boards 1 are formed at the same time by cutting the panel-shaped laminated body into individual pieces. At the time of cutting, the cutting position is determined so that the distance between the outer peripheral edge of the wiring board 1 and the electrode 3 becomes a predetermined value. In other words, the semiconductor element S can be mounted at a predetermined position on the upper surface of the wiring board 1 by cutting with the electrode 3 on the upper surface side of the panel-shaped laminate as a reference.

  Therefore, in the wiring board 1, the electrodes 3 and the wiring conductors 4 located on the first insulating layer 6a are located at a predetermined distance from the outer peripheral edge of the wiring board 1. Then, the first electrode 3a is electrically connected to the wiring conductor 4 on the upper surface of the second insulating layer 6b by the via hole 7 directly below.

  However, the wiring conductors 4 located in the insulating layer 6 below the second insulating layer 6b do not necessarily have a predetermined distance from the outer peripheral edge of the wiring board 1 when, for example, a stacking deviation occurs in the above-described stacking step or the like. Not necessarily located in. That is, when the panel-shaped laminate is cut, since the wiring conductor 4 located in the insulating layer 6 below the second insulating layer 6b is not used as a reference, the outer peripheral edge of the wiring board 1 and the wiring conductor 4 are predetermined. In some cases, it may not be possible to form them at intervals of.

  The wiring board 1 of the present disclosure includes a laminated body 2 in which three or more insulating layers 6 including a first insulating layer 6a and a second insulating layer 6b are laminated with each other, an upper surface, a lower surface of the laminated body 2, and an insulating layer 6. In the wiring region 8, the wiring region 8 located between them, the first electrode 3a located along the outer peripheral edge of the wiring region 8 in the wiring region 8 on the upper surface of the first insulating layer 6a, It has the wiring conductor 4 located and a plurality of via holes 7.

  The first electrode 3a is electrically connected to the wiring conductor 4 located on the upper surface of the second insulating layer 6b by the via hole 7 located directly below the first electrode 3a among the plurality of via holes 7, and also has a plurality of insulation properties. The wiring region 8 of the layer 6 which is located below the second insulating layer 6b is located so as to be included in the wiring region 8 of the first insulating layer 6a when seen in a plan view.

  Therefore, even if the outer peripheral edge of the wiring board 1 and the wiring conductor 4 located in the insulating layer 6 below the second insulating layer 6b are not located at a predetermined interval, the wiring conductor 4 Can be reduced from being exposed from the outer peripheral edge of the wiring board 1.

  In other words, by setting in advance such that the wiring region 8 located below the second insulating layer 6b fits within the wiring region 8 located in the first insulating layer 6a in plan perspective, It is possible to reduce the influence of positional deviation of the wiring conductor 4 due to stacking deviation or the like.

  As a result, when the wiring boards 1 on which the semiconductor elements S are mounted are aligned vertically and horizontally in the inspection device without any gaps and the radiation is arranged so as not to leak from between the semiconductor elements S adjacent to each other, the wiring boards 1 are separated from each other. It is possible to prevent the wiring conductors 4 from being exposed from between the stacked insulating layers 6 and to prevent the wiring conductors adjacent to each other from being short-circuited. As a result, the wiring board 1 in which the semiconductor element S can function normally can be provided.

DESCRIPTION OF SYMBOLS 1 wiring board 2 laminated body 3 electrode 4 wiring conductor 6 insulating layer 6a first insulating layer 6b second insulating layer 7 via hole 8 wiring area

Claims (2)

A laminated body in which three or more insulating layers including a first insulating layer which is the first layer from the top and a second insulating layer which is the second layer are laminated with each other;
A wiring region located between the upper surface of the laminate, the lower surface and the insulating layers,
An electrode located along the outer peripheral edge of the wiring region in the wiring region on the upper surface of the first insulating layer;
A wiring conductor located in the wiring region,
A plurality of via holes that are located in the plurality of insulating layers and that electrically connect the wiring conductors located above and below the insulating layer,
Has
The electrode is electrically connected to the wiring conductor located on the upper surface of the second insulating layer by a via hole located directly below the electrode among the plurality of via holes, and
The wiring region located in at least one lower layer than the second insulating layer among the plurality of insulating layers fits within the wiring region located in the first insulating layer when seen in a plan view. Wiring board characterized by being located.   Among the plurality of insulating layers, the wiring region located in all layers lower than the second insulating layer is located so as to fit within the wiring region located in the first insulating layer when seen in a plan view. The wiring board according to claim 1, wherein:

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