TWI529880B - Semiconductor device, semiconductor package and method for making the same - Google Patents

Description

Semiconductor component, semiconductor package structure and method of manufacturing same

The present invention relates to a semiconductor device, a semiconductor package structure, and a method of fabricating the same. In particular, the present invention relates to a semiconductor device having a back side metallization (BSM) and a thermal interface material (TIM), a semiconductor package structure, and a method of fabricating the same.

In a conventional semiconductor package structure, a heat sink is usually covered to contact the back surface of the wafer on the substrate and to discharge the heat generated by the wafer. Since the material of the heat sink is copper, and the material of the wafer is 矽, the bonding effect and heat dissipation effect of the two are not good. In order to improve the above disadvantages, a solution is to add a back side metallization (BSM) and a thermal interface material (TIM) on the back surface of the wafer, and the heat sink first contacts the thermal interface material, and then passes through The reflow process causes the heat sink to bond to the thermal interface material.

The backside metallization comprises a plurality of metal layers, and the thermal interface material comprises at least one metal layer. Several combinations of the backside metallization and the thermal interface material are known. However, in the prior art, it is inevitable that voids will be generated in the thermal interface material during the reflow process (Void ), thus affecting the bonding effect and heat dissipation effect. In addition, the temperatures required for the reflow process of the prior art are quite high.

One aspect of the disclosure relates to a semiconductor component. In one embodiment, the semiconductor device includes a semiconductor die, a backside metallization (BSM), a thermal interface material (TIM), and a first intermetallic compound (Intermetallic Compound, IMC). The semiconductor die has a first surface and a second surface. The backside metallization is on the second surface of the semiconductor die. The thermal interface material is on the backside metallization and comprises an In-Zn alloy. The first intermetallic compound is between the backside metallization and the thermal interface material and comprises indium and no zinc.

Another aspect of the disclosure relates to a semiconductor package structure. In one embodiment, the semiconductor package structure includes a substrate, a semiconductor die, a backside metallization, a thermal interface material, a heat sink, a first intermetallic compound, and a second intermetallic compound. The semiconductor die has a first surface and a second surface, and the first surface of the semiconductor die is electrically connected to the substrate. The backside metallization is on the second surface of the semiconductor die. The thermal interface material is on the backside metallization and comprises an indium zinc alloy. The heat sink covers the semiconductor die to contact the thermal interface material and includes at least one copper layer. The first intermetallic compound is between the backside metallization and the thermal interface material and comprises indium and no zinc. The second intermetallic compound is between the thermal interface material and the heat sink and comprises indium without zinc.

Another aspect of the disclosure is directed to a method of fabricating a semiconductor package structure. In one embodiment, the method of manufacturing includes the steps of: (a) forming a backside metallization on a second surface of a semiconductor die; (b) electrically connecting a first surface of the semiconductor die to a substrate; (c) providing an oxide-removing material to the backside metallization; (d) forming a thermal interface material on the backside metallization, wherein the thermal interface material comprises an indium-zinc alloy; (e) a heat sink covering the semiconductor die to contact the thermal interface material, wherein the heat sink comprises at least a copper layer; and (f) performing reflow to form a first intermetallic compound and a second intermetallic metal a compound wherein the first intermetallic compound is located The backside metallization and the thermal interface material comprise between indium and no zinc; the second intermetallic compound is between the thermal interface material and the heat sink and comprises indium and no zinc.

In the present embodiment, since the indium zinc alloy has a state in which solid and liquid coexist. Therefore, in the reflow process, if a void (Void) is formed in the thermal interface material, the liquid indium zinc alloy can fill the void immediately, so that the thermal interface material does not exist after the reflow process. There are any holes, and the bonding effect and heat dissipation effect between the heat interface material and the heat sink can be increased.

1‧‧‧An embodiment of the semiconductor package structure of the present invention

1a‧‧‧Another embodiment of the semiconductor package structure of the present invention

10‧‧‧Semiconductor components

12‧‧‧Substrate

14‧‧‧Semiconductor grain

15‧‧‧Bumps

16‧‧‧ Back side metallization

17‧‧‧Reducing gas

18‧‧‧Hot interface materials

20‧‧‧ Heat sink

21‧‧‧ Nickel layer

31‧‧‧ Curve

32‧‧‧ Curve

121‧‧‧The first surface of the substrate

122‧‧‧Second surface of the substrate

141‧‧‧ First surface of the semiconductor die

142‧‧‧Second surface of the semiconductor die

161‧‧‧First metal layer

162‧‧‧Second metal layer

163‧‧‧ Third metal layer

164‧‧‧ Flux

181‧‧‧First intermetallic compound

182‧‧‧Secondary metal compound

182a‧‧‧Secondary metal compound

183‧‧‧ Flux

1 shows a schematic cross-sectional view of one embodiment of a semiconductor package structure of the present invention. .

Fig. 2 is a partially enlarged schematic view showing a region A of Fig. 1.

3 and 4 are schematic views showing an embodiment of a method of fabricating a semiconductor package structure of the present invention.

FIG. 5 is a schematic view showing another embodiment of a method of fabricating a semiconductor package structure of the present invention.

Figure 6 shows a solid-liquid equilibrium phase diagram of an indium zinc alloy.

Figure 7 is a graph showing the ratio of zinc in the indium-zinc alloy, the liquidus temperature, and the reflow time, wherein the reflow temperature is 200 °C.

Figure 8 is a graph showing the ratio of zinc in the indium-zinc alloy, the liquidus temperature, and the reflow time, wherein the reflow temperature is 250 °C.

Figure 9 is a cross-sectional view showing another embodiment of the semiconductor package structure of the present invention.

Fig. 10 is a partially enlarged schematic view showing a region B of Fig. 9.

Referring to Figure 1, there is shown a cross-sectional schematic view of one embodiment of a semiconductor package structure of the present invention. The semiconductor package structure 1 includes a substrate 12, a semiconductor component 10, and a heat sink 20. The substrate 12 is a package substrate comprising a first surface 121, a second surface 122 and a plurality of internal electrical connection elements (not shown). Internal electrical connecting elements The first surface 121 and the second surface 122 are electrically connected.

The semiconductor device 10 includes a semiconductor die 14 , a plurality of bumps 15 , a back side metallization (BSM) 16 , and a thermal interface material 18 .

The semiconductor die 14 includes a first surface 141 and a second surface 142.

The bumps 15 are located on the first surface 141 of the semiconductor die 14 and electrically connected to the first surface 141 of the semiconductor die 14 to the second surface 122 of the substrate 12. That is, the semiconductor die 14 is flip-chip bonded to the substrate 12.

The backside metallization 16 is located on the second surface 142 of the semiconductor die 14.

The thermal interface material 18 is located on the backside metallization 16.

The heat sink 20 covers the semiconductor die 14 to contact the thermal interface material 18. In this embodiment, the heat sink 20 is further bonded to the second surface 122 of the substrate 12 for discharging heat generated by the semiconductor die 14. The heat sink 20 includes at least one copper layer. In the embodiment, the heat sink 20 is made of copper.

Referring to Figure 2, a partial enlarged view of area A of Figure 1 is shown. As shown, the backside metallization 16 comprises a plurality of metal layers, that is, the backside metallization 16 can be a metal layer, a two metal layer, or a metal layer of three or more layers. In this embodiment, the backside metallization 16 sequentially includes a first metal layer 161, a second metal layer 162, and a third metal layer 163. The first metal layer 161 is located on the second surface 142 of the semiconductor die 14 and is an aluminum layer, a titanium layer or a chromium layer. The second metal layer 162 is located on the first metal layer 161 and is a nickel layer or a nickel vanadium alloy layer. The third metal layer 163 is located on the second metal layer 162 and is a copper layer. In other words, the uppermost metal layer of the backside metallization 16 is a copper layer. Preferably, the first metal layer 161 and the second metal layer 162 are sputtered, and the copper layer of the third metal layer 163 is composed of a sputtered copper and an electroplated copper. It is located on sputtered copper and has a thickness of approximately 5 μm.

The thermal interface material 18 is located on the third metal layer 163 and includes at least one metal layer. In this embodiment, the thermal interface material 18 is a single metal layer, and the material is indium. In-Zn alloy, and the weight percentage of zinc in the indium zinc alloy is 5 wt% to 30 wt%. However, in other embodiments, the material of the thermal interface material 18 is Bi-In alloy. The copper layer of the heat sink 20 is in direct contact with the thermal interface material 18.

After the reflow process, the heat sink 20 is in close contact with the thermal interface material 18, and a first intermetallic compound (IMC) 181 and a second intermetallic compound are formed in the thermal interface material 18. 182. The first intermetallic compound 181 is located between the third metal layer 163 of the backside metallization 16 and the thermal interface material 18, and the indium of the thermal interface material 18 reacts with the copper of the third metal layer 163. And formed Cu ₁₁ In ₉ . Therefore, the first intermetallic compound 181 contains indium and does not contain zinc. The second intermetallic compound 182 is located between the thermal interface material 18 and the heat sink 20, and is formed by the reaction of indium in the thermal interface material 18 with copper of the heat sink 20 to form Cu ₁₁ In ₉ . Therefore, the second intermetallic compound 182 contains indium and does not contain zinc.

Since the indium zinc alloy has a state in which solid and liquid coexist. Therefore, in the reflow process, if a void is formed in the thermal interface material 18, the liquid indium zinc alloy can immediately fill the void, so that the thermal interface material 18 is after the reflow process. There is no void, and the bonding effect and heat dissipation effect between the thermal interface material 18 and the heat sink 20 can be increased.

Referring to Figures 3 and 4, there is shown a schematic diagram of one embodiment of a method of fabricating a semiconductor package structure of the present invention. Referring to FIG. 3, a backside metallization 16 is formed on the second surface 142 of a semiconductor die 14. The backside metallization 16 comprises a plurality of metal layers. In this embodiment, the backside metallization 16 sequentially includes a first metal layer 161, a second metal layer 162, and a third metal layer 163 (FIG. 2). The first metal layer 161 (eg, an aluminum layer, a titanium layer, or a chromium layer) is formed on the second surface 142 of the semiconductor die 14 first. Next, the second metal layer 162 (for example, a nickel layer or a nickel vanadium alloy layer) is formed on the first metal layer 161. Next, the third metal layer 163 (eg, a copper layer) is formed on the second metal layer 162. Preferably, the first metal layer 161 and the second metal layer 162 are sputtered, and the third metal The copper layer of layer 163 is first formed with a sputtered copper on the second metal layer 162, and then an electroplated copper is formed on the sputtered copper, and the thickness of the electroplated copper is about 5 μm.

Next, the semiconductor die 14 is electrically connected to a substrate 12. In this embodiment, the substrate 12 is a package substrate including a first surface 121, a second surface 122, and a plurality of internal electrical connection elements (not shown). The internal electrical connection components are used to electrically connect the first surface 121 and the second surface 122. The semiconductor die 14 further includes a second surface 142 and a plurality of bumps 15. The bumps 15 are located on the first surface 141 of the semiconductor die 14. The semiconductor die 14 is flip-chip bonded to the substrate 12 by the bumps 15 such that the first surface 141 of the semiconductor die 14 is electrically connected to the second surface 122 of the substrate 12.

Referring to Figure 4, an oxide-removing material is provided to the backside metallization 16 to prevent the backside metallization 16 from being bonded due to oxidation. In the present embodiment, the oxide-removing material is a flux 164 formed on the back side of the backside metallization 16. Next, a thermal interface material 18 is provided. In the present embodiment, the thermal interface material 18 is a single-layer metal foil, the material of which is an in-Zn alloy, and the weight percentage of zinc in the indium-zinc alloy is 5 wt% to 30 wt%. However, in other embodiments, the material of the thermal interface material 18 is Bi-In alloy. In order to remove the oxide of the thermal interface material 18, a flux 183 is formed on the upper and lower surfaces of the thermal interface material 18. It can be understood that the material of the flux 164 and the flux 183 can be different compositions.

Next, the thermal interface material 18 is placed on the backside metallization 16. Next, a heat sink (Lid) 20 (FIG. 1) is placed over the semiconductor die 14 to contact the thermal interface material 18. In the present embodiment, the heat sink 20 is a heat sink that is further bonded to the second surface 122 of the substrate 12. The heat sink 20 includes at least one copper layer. In the embodiment, the heat sink 20 is made of copper, and the copper layer of the heat sink 20 directly contacts the heat interface material 18.

Next, reflow is performed to form a semiconductor package structure 1, as shown in FIG. After the reflow process, the heat sink 20 is in close contact with the thermal interface material 18, and a first intermetallic compound (IMC) 181 and a second intermetallic compound are formed in the thermal interface material 18. 182 (Figure 2). The first intermetallic compound 181 is located between the third metal layer 163 of the backside metallization 16 and the thermal interface material 18, and the indium of the thermal interface material 18 reacts with the copper of the third metal layer 163. And formed Cu ₁₁ In ₉ . Therefore, the first intermetallic compound 181 contains indium and does not contain zinc. The second intermetallic compound 182 is located between the thermal interface material 18 and the heat sink 20, and is formed by the reaction of indium in the thermal interface material 18 with copper of the heat sink 20 to form Cu ₁₁ In ₉ . Therefore, the second intermetallic compound 182 contains indium and does not contain zinc.

Referring to Figure 5, there is shown a schematic diagram of another embodiment of a method of fabricating a semiconductor package structure of the present invention. The manufacturing method of the present embodiment is substantially the same as the manufacturing method of FIGS. 3 to 4, except that in the present embodiment, the material for removing oxide is a reducing gas (for example, hydrogen gas, Nitrogen, fluorine or chlorine) without the use of flux. In detail, the backside metallization 16 together with the semiconductor die 14 and the substrate 12 are placed in a channel filled with the reducing gas 17. Next, the thermal interface material 18 is placed on the backside metallization 16. Next, the heat sink 20 (FIG. 1) covers the semiconductor die 14 to contact the thermal interface material 18. Next, reflow is performed. It is to be noted that all of the above processes are carried out in a tunnel filled with the reducing gas 17.

Referring to Figure 6, a solid-liquid equilibrium phase diagram of an indium-zinc alloy is shown. In the figure, the abscissa is the ratio of the number of moles of zinc in the indium-zinc alloy, and the ordinate is the temperature. As shown in the figure, the curve 31 (corresponding temperature is 413K) is a solid phase line, when the curve 31 is below, the indium zinc alloy is solid; the curve 32 is a liquidus, and when the curve 32 is above, the indium zinc alloy is It is a liquid state; between the curve 31 and the curve 32, the indium zinc alloy is a solid-liquid coexistence. Further, as the proportion of the molar amount of zinc in the indium-zinc alloy is higher, the area where the solid-liquid coexists is larger, that is, the coexistence of solid-liquid is more likely to occur. In this embodiment, in the reflow process, since the indium in the thermal interface material 18 reacts with the copper of the third metal layer 163 and the copper of the heat sink 20 to form a intermetallic compound (Cu ₁₁ In ₉ ). And zinc does not react with copper. Therefore, the ratio of the number of moles of zinc in the indium-zinc alloy in the hot interface material 18 is higher and higher. At this time, as long as the temperature exceeds 413 K, the indium-zinc alloy exhibits a state in which solid and liquid coexist. In this case, if voids are formed in the thermal interface material 18, the liquid indium zinc alloy can immediately fill the voids, so that there is no void in the thermal interface material 18 after the reflow process. The hole can increase the bonding effect and heat dissipation effect between the thermal interface material 18 and the heat sink 20.

Referring to Fig. 7, it is a graph showing the relationship between the proportion of zinc in the indium-zinc alloy, the liquidus temperature, and the reflow time when the reflow temperature is set to 200 °C. In the figure, the abscissa is the reflow time, the left ordinate is the atomic percentage (at.%) of zinc in the indium-zinc alloy, and the right ordinate is the temperature of the liquidus of the indium-zinc alloy. The figure shows two indium-zinc alloys with a ratio of starting components. The first one: zinc is 10 wt% (in weight percent) of indium zinc alloy (equivalent to 16.3 at.% (atomic percent) of indium zinc alloy). And the second: zinc is 20 wt% (by weight) of indium zinc alloy (equivalent to 30.5 at.% (atomic percent) of zinc indium zinc alloy). The four curves in the figure are represented as follows: The first one: ■ represents the liquidus temperature of the indium zinc alloy with a zinc content of 16.3 atomic percent (at.%) in the starting composition as a function of time; ◆ represents a zinc content of 16.3 atoms in the starting component. Percent (at.%) of the zinc component of the indium zinc alloy as a function of time; second: x represents the liquidus temperature of the indium zinc alloy with a zinc content of 30.5 atomic percent (at.%) in the starting composition as a function of time; ▲ represents the zinc component of the indium zinc alloy with a zinc content of 30.5 atomic percent (at.%) in the starting composition as a function of time. It can be seen from the figure that at the reflow temperature of 200 ° C, the proportion of zinc in the indium zinc alloy increases with time, and the liquidus temperature of the indium zinc alloy also increases. For example, after 300 seconds, the liquidus temperature of the indium zinc alloy increased by about 15 °C.

Referring to Fig. 8, the set reflow temperature is 250 ° C, which shows the relationship between the proportion of zinc in the indium zinc alloy, the liquidus temperature and the reflow time. In the figure, the horizontal coordinate system is for reflow The left ordinate is the atomic percentage (at.%) of zinc in the indium-zinc alloy, and the right ordinate is the temperature of the liquidus of the indium-zinc alloy. The figure shows two indium-zinc alloys with a ratio of starting components. The first one: zinc is 10 wt% (in weight percent) of indium zinc alloy (equivalent to 16.3 at.% (atomic percent) of indium zinc alloy). And the second: zinc is 20 wt% (by weight) of indium zinc alloy (equivalent to 30.5 at.% (atomic percent) of zinc indium zinc alloy). The four curves in the figure are represented as follows: The first one: ■ represents the liquidus temperature of the indium zinc alloy with a zinc content of 16.3 atomic percent (at.%) in the starting composition as a function of time; ◆ represents a zinc content of 16.3 atoms in the starting component. Percent (at.%) of the zinc component of the indium zinc alloy as a function of time; second: x represents the liquidus temperature of the indium zinc alloy with a zinc content of 30.5 atomic percent (at.%) in the starting composition as a function of time; ▲ represents the zinc component of the indium zinc alloy with a zinc content of 30.5 atomic percent (at.%) in the starting composition as a function of time. It can be seen from the figure that at the reflow temperature of 250 ° C, the proportion of zinc in the indium zinc alloy increases with time, and the liquidus temperature of the indium zinc alloy also increases. For example, after 300 seconds, the liquidus temperature of the indium zinc alloy increased by about 20 °C.

Referring to Figure 9, a cross-sectional schematic view of another embodiment of a semiconductor package structure of the present invention is shown. The semiconductor package structure 1a of the present embodiment is substantially the same as the semiconductor package structure 1 shown in FIG. 1, and the differences are as follows. In the semiconductor package structure 1a of the embodiment, the heat sink 20 further includes a nickel layer 21 on the copper layer of the heat sink 20. The nickel layer 21 is in direct contact with the thermal interface material 18.

Referring to Fig. 10, a partially enlarged schematic view of a region B of Fig. 9 is shown. As shown, the indium in the thermal interface material 18 reacts with the nickel layer 21 of the heat sink 20 to form a second intermetallic compound 182a, and the second intermetallic compound 182a is In ₂₇ Ni ₁₀ . Therefore, the second intermetallic compound 182a contains indium and does not contain zinc. The manufacturing method of the semiconductor package structure 1a of the present embodiment is substantially the same as the manufacturing method shown in FIG. 3 and FIG. 4, except that the nickel layer 21 is first formed on the copper layer of the heat sink 20, and the heat sink is further disposed. The semiconductor die 14 is covered to contact the thermal interface material 18. Next, reflow is performed to form a semiconductor package structure 1a. During the reflow process, the indium in the thermal interface material 18 reacts with the nickel layer 21 of the heat sink 20, so that the proportion of zinc in the thermal interface material 18 increases with time.

However, the above embodiments are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims.

1‧‧‧An embodiment of the semiconductor package structure of the present invention

10‧‧‧Semiconductor components

12‧‧‧Substrate

14‧‧‧Semiconductor grain

15‧‧‧Bumps

16‧‧‧ Back side metallization

18‧‧‧Hot interface materials

20‧‧‧ Heat sink

121‧‧‧The first surface of the substrate

122‧‧‧Second surface of the substrate

141‧‧‧ First surface of the semiconductor die

142‧‧‧Second surface of the semiconductor die

Claims (18)

A semiconductor device comprising: a semiconductor die having a first surface and a second surface; a backside metallization on the second surface of the semiconductor die; a thermal interface material on the backside metallization And comprising an indium zinc alloy; and a first intermetallic compound between the back side metallization and the thermal interface material, and comprising indium without zinc; wherein the content of zinc in the indium zinc alloy of the thermal interface material It is 5 wt% to 30 wt%. The semiconductor device of claim 1, wherein the backside metallization comprises a plurality of metal layers, wherein the uppermost metal layer is a copper layer, and the first intermetallic compound is Cu ₁₁ In ₉ . The semiconductor device of claim 2, wherein the backside metallized copper layer is composed of a sputtered copper and an electroplated copper, and the electroplated copper has a thickness of about 5 μm. The semiconductor device of claim 2, wherein the backside metallization comprises a first metal layer, a second metal layer and a third metal layer, the first metal layer being located on the second surface of the semiconductor die And being an aluminum layer, a titanium layer or a chromium layer; the second metal layer is on the first metal layer and is a nickel layer or a nickel vanadium alloy layer; the third metal layer is located in the second metal On the layer, and is a copper layer. A semiconductor package structure comprising: a substrate; a semiconductor die having a first surface and a second surface, the first surface of the semiconductor die being electrically connected to the substrate; and a back side metallization a second surface of the semiconductor die; a thermal interface material on the backside metallization and comprising an indium zinc alloy; a heat sink covering the semiconductor die to contact the thermal interface material, and at least The first intermetallic compound is disposed between the backside metallization and the thermal interface material, and comprises indium instead of zinc; and a second intermetallic compound located in the thermal interface material and the heat dissipation Between the sheets, and containing indium without containing zinc; wherein the content of zinc in the indium zinc alloy of the thermal interface material is from 5 wt% to 30 wt%. The semiconductor package of the requested item 5, wherein the back side metallization comprises a plurality of metal layers, wherein the uppermost layer of copper-based metal layer and the first dielectric-based metal compound is Cu ₁₁ In _9. The semiconductor package structure of claim 6, wherein the backside metallized copper layer is composed of a sputtered copper and an electroplated copper, and the electroplated copper has a thickness of about 5 μm. The semiconductor package structure of claim 6, wherein the back side metallization comprises a first metal layer, a second metal layer and a third metal layer, the first metal layer being located at the second of the semiconductor die On the surface, and is an aluminum layer, a titanium layer or a chromium layer; the second metal layer is on the first metal layer and is a nickel layer or a nickel vanadium alloy layer; the third metal layer is located in the second layer On the metal layer, it is a copper layer. The semiconductor package structure of claim 5, wherein the copper layer of the heat sink is in direct contact with the thermal interface material, and the second intermetallic compound is Cu ₁₁ In ₉ . The semiconductor package structure of claim 5, wherein the heat sink further comprises a nickel layer, the nickel layer directly contacting the thermal interface material, and the second intermetallic compound is In ₂₇ Ni ₁₀ . A method of fabricating a semiconductor package structure, comprising the steps of: (a) forming a backside metallization on a second surface of a semiconductor die; (b) electrically connecting a first surface of the semiconductor die to the first surface a substrate; (c) providing an oxide removing material to the back side metallization; (d) forming a thermal interface material on the backside metallization, wherein the thermal interface material comprises an indium zinc alloy; (e) covering a semiconductor die with a heat sink to contact the thermal interface material, wherein the heat sink is at least And comprising (f) performing reflow soldering to form a first intermetallic compound and a second intermetallic compound, wherein the first intermetallic compound is between the backside metallization and the thermal interface material, And comprising indium without containing zinc; the second intermetallic compound is located between the thermal interface material and the heat sink, and comprises indium instead of zinc. The manufacturing method of claim 11, wherein in the step (a), the backside metal plating comprises a plurality of metal layers, wherein the uppermost metal layer is a copper layer, and in the step (f), the first metal compound is For Cu ₁₁ In ₉ . The method of claim 12, wherein in the step (a), the backside metallized copper layer is composed of a sputtered copper and an electroplated copper, and the electroplated copper has a thickness of about 5 μm. The manufacturing method of claim 12, wherein in the step (a), the backside metal plating comprises a first metal layer, a second metal layer and a third metal layer, the first metal layer being located in the semiconductor On the second surface of the crystal grain, and is an aluminum layer, a titanium layer or a chromium layer; the second metal layer is on the first metal layer and is a nickel layer or a nickel vanadium alloy layer; the third metal layer It is located on the second metal layer and is a copper layer. The manufacturing method of claim 11, wherein in the step (c), the material for removing the oxide is a reducing gas or a flux. The manufacturing method of claim 11, wherein in the step (d), the content of zinc in the indium zinc alloy of the thermal interface material is from 5 wt% to 30 wt%. The manufacturing method of claim 11, wherein in the step (e), the copper layer of the heat sink is in direct contact with the thermal interface material; and in the step (f), the second intermetallic compound is Cu ₁₁ In ₉ . The manufacturing method of claim 11, wherein in the step (e), the heat sink further comprises a nickel layer directly contacting the thermal interface material; and in the step (f), the second metal intermetallic compound is In ₂₇ Ni ₁₀ .