JP7310482B2 - Bonding structure and liquid phase diffusion bonding method - Google Patents

Description

The present invention relates to a bonding structure and a liquid phase diffusion bonding method.

There is a technique of disposing a Sn layer between a Cu wiring of a substrate and an electronic component and bonding the substrate and the electronic component with a CuSn bonding layer by liquid phase diffusion bonding (for example, Patent Document 1).

JP 2013-229474 A

By the way, for example, as shown in FIG. 19, as a bonding structure in which a bonding layer 102 is formed between a Cu wiring 100 and a semiconductor chip 101, the bonding layer 102 is formed between the Cu3Sn intermetallic compound layer 103 on the Cu wiring side. , and an intermetallic compound layer 104 of Cu6Sn5 on the semiconductor chip side. Therefore, as shown in FIG. 20, as a liquid phase diffusion bonding method for bonding the Cu wiring 100 and the semiconductor chip 101, in a state in which the Sn thin film 105 is sandwiched between the Cu wiring 100 and the semiconductor chip 101, For example, the Cu wiring 100 and the semiconductor chip 101 are bonded under a temperature atmosphere of about 350.degree. In other words, in liquid phase diffusion bonding, Cu has a high melting point of about 1080°C and Sn has a low melting point of about 230°C. As a result, Cu is diffused and bonded. Cu6Sn5, which is an intermetallic compound, is formed during this bonding, and when Cu further diffuses into the Cu6Sn5 on the Cu wiring side, it is replaced with Cn3Sn, which is an intermetallic compound. As a result, an intermetallic compound layer 103 of Cu3Sn is formed on the Cu wiring side and an intermetallic compound layer 104 of Cu6Sn5 is formed on the semiconductor chip side.

Of the Cu3Sn intermetallic compound layer 103 on the Cu wiring side and the Cu6Sn5 intermetallic compound layer 104 on the semiconductor chip side, phase transformation occurs only in the Cu6Sn5 intermetallic compound layer 104 at a constant temperature. That is, Cu6Sn5 has the property of transforming its crystal structure into a hexagonal crystal structure at a high temperature range of 186°C or higher, and to a monoclinic crystal structure at a temperature lower than 186°C. Since it is heated to 186° C. or higher during bonding, it becomes a hexagonal crystal at that point. After that, it is cooled, but since the cooling rate in the bonding furnace is fast, the time required for the above-mentioned phase transformation cannot be satisfied, and it does not transform to the monoclinic crystal, which is the stable phase at low temperatures. exists as a hexagonal crystal. However, since the hexagonal crystal structure is not stable at low temperatures, it is in an unstable state and gradually undergoes phase transformation to monoclinic crystals. Also, the progress of the phase transformation is accelerated by the temperature rise. During this phase transformation, the Cu6Sn5 intermetallic compound layer 104 increases in volume by about 2%. As a result, strain is generated, which may cause cracks, which may reduce reliability.

An object of the present invention is to provide a bonding structure and a liquid phase diffusion bonding method capable of suppressing the occurrence of cracks in the bonding layer.

A bonding structure that solves the above problem is a bonding structure in which a bonding layer is formed between a Cu wiring and a semiconductor chip, wherein the bonding layer comprises a Cu3Sn intermetallic compound layer on the Cu wiring side and the semiconductor The gist is to form a two-layer structure with an intermetallic compound layer of (Cu, Ni)6Sn5 on the chip side.

According to this, the bonding layer has a two-layer structure of a Cu3Sn intermetallic compound layer on the Cu wiring side and a (Cu, Ni)6Sn5 intermetallic compound layer on the semiconductor chip side. Compared to a two-layer structure of a Cu3Sn intermetallic compound layer on the wiring side and a Cu6Sn5 intermetallic compound layer on the semiconductor chip side, the occurrence of cracks due to the volume change accompanying the phase transformation of Cu6Sn5 is suppressed. be able to.

A bonding structure that solves the above problem is a bonding structure in which a bonding layer is formed between a Cu wiring and a semiconductor chip, and the bonding layer is a single layer made of an intermetallic compound layer of (Cu, Ni) 6 Sn 5 The gist is that it is a structure.

According to this, since the bonding layer has a one-layer structure consisting of an intermetallic compound layer of (Cu, Ni)6Sn5, the bonding layer consists of the intermetallic compound layer of Cu3Sn on the Cu wiring side and the intermetallic compound layer of Cu6Sn5 on the semiconductor chip side. The occurrence of cracks due to the volume change due to the phase transformation of Cu6Sn5 can be suppressed compared to the case of forming a two-layer structure with the intermetallic compound layer of .

A bonding structure that solves the above problem is a bonding structure in which a bonding layer is formed between a Cu wiring and a semiconductor chip, and the bonding layer is an intermetallic compound in which (Cu, Ni)6Sn5 and Cu6Sn5 are mixed. The gist is that it has a one-layer structure consisting of layers.

According to this, since the bonding layer has a one-layer structure composed of an intermetallic compound layer in which (Cu, Ni)6Sn5 and Cu6Sn5 are mixed, the bonding layer includes the Cu3Sn intermetallic compound layer on the Cu wiring side, Compared to the case of forming a two-layer structure with an intermetallic compound layer of Cu6Sn5 on the semiconductor chip side, the occurrence of cracks due to volume change due to phase transformation of Cu6Sn5 can be suppressed.

A liquid phase diffusion bonding method for solving the above problem is a liquid phase diffusion bonding method for bonding a Cu wiring and a semiconductor chip, wherein between the Cu wiring and the semiconductor chip, from the Cu wiring side, the semiconductor chip The gist of the invention is that the Cu wiring and the semiconductor chip are joined in an atmosphere at a temperature higher than the melting point of Sn in a state in which a Ni thin film, a Sn thin film, a Ni thin film, and a Cu thin film are sandwiched in order from one side to another.

According to this, a Ni thin film, a Sn thin film, a Ni thin film, and a Cu thin film are sandwiched between the Cu wiring and the semiconductor chip in this order from the Cu wiring side to the semiconductor chip side, and in a temperature atmosphere above the melting point of Sn. Below, the Cu wiring and the semiconductor chip are bonded to form two bonding layers: the Cu3Sn intermetallic compound layer on the Cu wiring side and the (Cu, Ni)6Sn5 intermetallic compound layer on the semiconductor chip side. Since the bonding layer has a layered structure, compared to the case where the bonding layer has a two-layer structure of a Cu3Sn intermetallic compound layer on the Cu wiring side and a Cu6Sn5 intermetallic compound layer on the semiconductor chip side, the phase transformation of Cu6Sn5 It is possible to suppress the occurrence of cracks due to volume change.

A liquid phase diffusion bonding method for solving the above problem is a liquid phase diffusion bonding method for bonding a Cu wiring and a semiconductor chip, wherein between the Cu wiring and the semiconductor chip, from the Cu wiring side, the semiconductor chip The gist of the present invention is that the Cu wiring and the semiconductor chip are bonded to each other in an atmosphere at a temperature higher than the melting point of Sn in a state in which a thin Ni film, a thin Sn film, and a thin Cu film are sandwiched in order from one side to another.

According to this, in a state where a Ni thin film, a Sn thin film, and a Cu thin film are sandwiched in order from the Cu wiring side to the semiconductor chip side between the Cu wiring and the semiconductor chip, under a temperature atmosphere above the melting point of Sn, By bonding the Cu wiring and the semiconductor chip, the bonding layer has a two-layer structure of the Cu3Sn intermetallic compound layer on the Cu wiring side and the (Cu, Ni)6Sn5 intermetallic compound layer on the semiconductor chip side. Therefore, compared with the case where the bonding layer has a two-layer structure of a Cu3Sn intermetallic compound layer on the Cu wiring side and a Cu6Sn5 intermetallic compound layer on the semiconductor chip side, the volume change due to the phase transformation of Cu6Sn5 It is possible to suppress the occurrence of cracks caused by the

A liquid phase diffusion bonding method for solving the above problem is a liquid phase diffusion bonding method for bonding a Cu wiring and a semiconductor chip, wherein between the Cu wiring and the semiconductor chip, from the Cu wiring side, the semiconductor chip The gist of the present invention is that the Cu wiring and the semiconductor chip are joined in an atmosphere at a temperature higher than the melting point of Sn in a state in which a Sn thin film, a Ni thin film, and a Cu thin film are sandwiched in order from one side to another.

According to this, in a state in which a Sn thin film, a Ni thin film, and a Cu thin film are sandwiched in order from the Cu wiring side to the semiconductor chip side between the Cu wiring and the semiconductor chip, under a temperature atmosphere above the melting point of Sn, By bonding the Cu wiring and the semiconductor chip, the bonding layer has a two-layer structure of the Cu3Sn intermetallic compound layer on the Cu wiring side and the (Cu, Ni)6Sn5 intermetallic compound layer on the semiconductor chip side. Therefore, compared with the case where the bonding layer has a two-layer structure of a Cu3Sn intermetallic compound layer on the Cu wiring side and a Cu6Sn5 intermetallic compound layer on the semiconductor chip side, the volume change due to the phase transformation of Cu6Sn5 It is possible to suppress the occurrence of cracks caused by the

A liquid phase diffusion bonding method for solving the above problem is a liquid phase diffusion bonding method for bonding a Cu wiring and a semiconductor chip, wherein between the Cu wiring and the semiconductor chip, from the Cu wiring side, the semiconductor chip The gist of the present invention is that the Cu wiring and the semiconductor chip are joined in an atmosphere at a temperature higher than the melting point of Sn in a state in which an Sn thin film, a Cu thin film, and a Ni thin film are sandwiched in order from one side to another.

According to this, in a state in which a Sn thin film, a Cu thin film, and a Ni thin film are sandwiched in order from the Cu wiring side to the semiconductor chip side between the Cu wiring and the semiconductor chip, under a temperature atmosphere above the melting point of Sn, By bonding the Cu wiring and the semiconductor chip, the bonding layer has a two-layer structure of a Cu3Sn intermetallic compound layer on the Cu wiring side and a (Cu, Ni)6Sn5 intermetallic compound layer on the semiconductor chip side. Therefore, compared to the case where the bonding layer has a two-layer structure of a Cu3Sn intermetallic compound layer on the Cu wiring side and a Cu6Sn5 intermetallic compound layer on the semiconductor chip side, the volume change due to the phase transformation of Cu6Sn5 It is possible to suppress the occurrence of cracks caused by

Here, a Sn thin film is formed on the Cu wiring, a Ni thin film and a Cu thin film are formed on the semiconductor chip in this order, and the Cu thin film is arranged on the Sn thin film. A Sn thin film, a Cu thin film, and a Ni thin film are preferably sandwiched between the Cu wiring and the semiconductor chip in this order from the Cu wiring side to the semiconductor chip side.

A liquid phase diffusion bonding method for solving the above problem is a liquid phase diffusion bonding method for bonding a Cu wiring and a semiconductor chip, wherein between the Cu wiring and the semiconductor chip, from the Cu wiring side, the semiconductor chip The gist of the invention is that the Cu wiring and the semiconductor chip are joined in an atmosphere at a temperature higher than the melting point of Sn in a state in which a Ni thin film, a Sn thin film, a Cu thin film, and a Ni thin film are sandwiched in order from one side to another.

According to this, a Ni thin film, a Sn thin film, a Cu thin film, and a Ni thin film are sandwiched in order from the Cu wiring side to the semiconductor chip side between the Cu wiring and the semiconductor chip, and in a temperature atmosphere above the melting point of Sn. Below, the Cu wiring and the semiconductor chip are bonded to form two bonding layers: the Cu3Sn intermetallic compound layer on the Cu wiring side and the (Cu, Ni)6Sn5 intermetallic compound layer on the semiconductor chip side. Since the bonding layer has a layered structure, compared to the case where the bonding layer has a two-layer structure of a Cu3Sn intermetallic compound layer on the Cu wiring side and a Cu6Sn5 intermetallic compound layer on the semiconductor chip side, the phase transformation of Cu6Sn5 It is possible to suppress the occurrence of cracks due to volume change.

Here, a Ni thin film and a Sn thin film are formed in order on the Cu wiring, a Ni thin film and a Cu thin film are formed in order on the semiconductor chip, and the Cu thin film is arranged on the Sn thin film. As a result, a Ni thin film, a Sn thin film, a Cu thin film, and a Ni thin film are sandwiched between the Cu wiring and the semiconductor chip in this order from the Cu wiring side to the semiconductor chip side.

According to the present invention, it is possible to suppress the occurrence of cracks in the bonding layer.

The schematic diagram which shows the joining structure in embodiment. FIG. 4 is a schematic diagram showing the relationship between the semiconductor chip and the wiring substrate before bonding; FIG. 4 is a diagram showing an elemental mapping image of Cu by FE-EPMA in a cross section of a joint. FIG. 4 is a diagram showing an elemental mapping image of Sn by FE-EPMA in the cross section of the joint. FIG. 4 is a view showing an elemental mapping image of Ni by FE-EPMA in the cross section of the joint. The figure which shows the SEM image in the cross section of a joint part. The figure which shows the backscattered electron image in the cross section of a junction part. FIG. 4 is a diagram showing an elemental mapping image of Cu by FE-EPMA in a cross section of a joint in a conventional structure; FIG. 4 is a diagram showing an elemental mapping image of Sn by FE-EPMA in a cross section of a joint in a conventional structure; The figure which shows the SEM image in the cross section of the joint part in a conventional structure. The figure which shows the backscattered electron image in the cross section of the junction part in a conventional structure. FIG. 10 is a schematic diagram showing the relationship between a semiconductor chip and a wiring substrate before bonding in another example; FIG. 10 is a schematic diagram showing the relationship between a semiconductor chip and a wiring substrate before bonding in another example; FIG. 10 is a schematic diagram showing the relationship between a semiconductor chip and a wiring substrate before bonding in another example; FIG. 10 is a schematic diagram showing the relationship between a semiconductor chip and a wiring substrate before bonding in another example; The schematic diagram which shows the junction structure in another example. The schematic diagram which shows the junction structure in another example. The schematic diagram which shows the junction structure in another example. FIG. 2 is a schematic diagram showing a joint structure for explaining a problem; FIG. 2 is a schematic diagram showing the relationship between a semiconductor chip and a wiring substrate before bonding for explaining a problem;

An embodiment embodying the present invention will be described below with reference to the drawings.
As shown in FIG. 1 , the bonding structure 10 has a bonding layer 40 formed between a Cu wiring 22 and a semiconductor chip 30 . The bonding layer 40 has a two-layer structure of a Cu3Sn intermetallic compound layer 41 on the Cu wiring 22 side and a (Cu,Ni)6Sn5 intermetallic compound layer 42 on the semiconductor chip 30 side. That is, of the intermetallic compound (IMC) layers having a two-layer structure, the layer 41 on the Cu wiring 22 side is a Cu-rich intermetallic compound layer, and the layer 42 on the semiconductor chip 30 side is an Sn-rich intermetallic compound layer. is.

The wiring substrate 20 has a Cu wiring 22 patterned on the upper surface of an insulating substrate 21 , and the Cu wiring 22 extends on the insulating substrate 21 . The semiconductor chip 30 is made of silicon (Si) and has vertical power transistors and the like built therein. Then, the back electrode of the vertical power transistor is electrically connected to the Cu wiring 22 of the wiring board 20 .

Next, a joining method will be described.
As shown in FIG. 2, it is a liquid phase diffusion bonding (TLP) method for bonding the Cu wiring 22 and the semiconductor chip 30 .

A rear surface electrode 31 is formed on the rear surface of the semiconductor chip 30, and the rear surface electrode 31 is formed by laminating a Ti layer, a Ni layer, and an Ag layer in this order. That is, the back electrode 31 of the semiconductor chip 30 has a Ti/Ni/Ag structure. The thickness of the back electrode 31 is about 0.6 μm.

Between the Cu wiring 22 and the semiconductor chip 30, a Ni thin film 50, a Sn thin film 51, a Ni thin film 53, and a Cu thin film 52 are sandwiched in order from the Cu wiring 22 side toward the semiconductor chip 30 side. Specifically, a Sn thin film 51 is formed on the Cu wiring 22 with a Ni thin film 50 interposed therebetween. A Ni thin film 53 is formed on the rear surface electrode 31 of the semiconductor chip 30 with a Cu thin film 52 interposed therebetween, and an Au thin film 54 is formed on the surface of the Ni thin film 53 to ensure wettability.

The thickness t1 of the Ni thin film 50 is 0.5 to 1.5 μm, the thickness t2 of the Sn thin film 51 is 5 μm, the thickness t3 of the Cu thin film 52 is 0.5 to 1.0 μm, and the thickness of the Ni thin film 53 is 0.5 to 1.0 μm. The thickness t4 is 0.5 to 1.0 μm, and the thickness t5 of the Au thin film 54 is 0.1 μm.

Specifically, for example, the thickness t1 of the Ni thin film 50=0.5 μm, the thickness t2 of the Sn thin film 51=5 μm, the thickness t3 of the Cu thin film 52=0.5 μm, and the thickness t4 of the Ni thin film 53=1 .0 μm. In addition, for example, the thickness t1 of the Ni thin film 50=1.0 μm, the thickness t2 of the Sn thin film 51=5 μm, the thickness t3 of the Cu thin film 52=0.5 μm, and the thickness t4 of the Ni thin film 53=1.0 μm. 0 μm. In addition, for example, the thickness t1 of the Ni thin film 50=1.5 μm, the thickness t2 of the Sn thin film 51=5 μm, the thickness t3 of the Cu thin film 52=0.5 μm, and the thickness t4 of the Ni thin film 53=1.5 μm. 0 μm. In addition, for example, the thickness t1 of the Ni thin film 50=0.5 μm, the thickness t2 of the Sn thin film 51=5 μm, the thickness t3 of the Cu thin film 52=1.0 μm, and the thickness t4 of the Ni thin film 53=0.5 μm. 5 μm. In addition, for example, the thickness t1 of the Ni thin film 50 = 1.0 µm, the thickness t2 of the Sn thin film 51 = 5 µm, the thickness t3 of the Cu thin film 52 = 1.0 µm, and the thickness t4 of the Ni thin film 53 = 0.0 µm. 5 μm. In addition, for example, the thickness t1 of the Ni thin film 50=1.5 μm, the thickness t2 of the Sn thin film 51=5 μm, the thickness t3 of the Cu thin film 52=1.0 μm, and the thickness t4 of the Ni thin film 53=0.5 μm. 5 μm.

Note that the Cu thin film 52 is formed by sputtering and cannot be formed very thick.
In this way, the Ni thin film 50, the Sn thin film 51, the Ni thin film 53, and the Cu thin film 52 are sandwiched between the Cu wiring 22 and the semiconductor chip 30 in this order from the Cu wiring 22 side to the semiconductor chip 30 side. put in the furnace. Then, the Cu wiring 22 and the semiconductor chip 30 are bonded together in a H2 reducing atmosphere at a temperature of 300° C. or higher, for example, 350° C. for five minutes, for example.

In the liquid phase diffusion bonding, Cu with a high melting point and Sn with a low melting point are brought into contact with each other through the Ni thin film 50. When the temperature rises in the bonding furnace, Sn melts and becomes a liquid phase, and Cu diffuses to form Cu6Sn5. After that, the Cu of the Cu wiring 22 diffuses into the Cu6Sn5 on the Cu wiring side and replaces it with Cn3Sn to form an intermetallic compound layer of Cu3Sn on the Cu wiring side and an intermetallic compound layer of Cu6Sn5 on the semiconductor chip side. It is formed.

Furthermore, Ni diffuses from the Ni thin film 50 and the Ni thin film 53 to the bonding layer, and Cu6Sn5 changes to (Cu, Ni)6Sn5. Further, Cu diffuses from the Cu thin film 52 to the bonding layer to change Cu6Sn5 into Cu3Sn.

In this way, a two-layer structure is formed between the intermetallic compound layer 41 of Cu3Sn on the side of the Cu wiring 22 and the intermetallic compound layer 42 of (Cu,Ni)6Sn5 on the side of the semiconductor chip 30 as shown in FIG. A layer 40 is obtained. That is, Ni is diffused into Cu6Sn5 to form (Cu, Ni)6Sn5 in a laminated structure of a Cu3Sn intermetallic compound layer and a Cu6Sn5 intermetallic compound layer as a bonding layer. Also, the amount of Cu diffused into the bonding layer is increased to reduce the proportion of Cu6Sn5 as much as possible.

Next, the action will be described.
By diffusing Ni into the bonding layer, Cu6Sn5, which undergoes phase transformation when temperature changes, which is presumed to be the cause of cracks, is changed into stable (Cu, Ni)6Sn5 without phase transformation.

In addition, by increasing the amount of Cu diffusion into the bonding layer, one of the two IMCs (intermetallic compounds) generated in the bonding layer, Cu6Sn5, which is one of the IMCs in which cracks occur, is replaced with the other IMC in which cracks are less likely to occur. Change to Cu3Sn.

FIG. 8 is an elemental mapping image of Cu by FE-EPMA in the cross section of the joint in the conventional structure shown in FIG. On the other hand, in the present embodiment, as shown in FIG. 3, in the elemental mapping image of Cu by FE-EPMA in the cross section of the joint, the Cu wiring 22 side of the intermetallic compound (IMC) layer having a two-layer structure layer 41 is a Cu-rich intermetallic compound layer and becomes Cu3Sn. It can be seen that the layer 42 on the side of the semiconductor chip 30 is a Sn-rich intermetallic compound layer and is (Cu, Ni)6Sn5. In particular, as shown in FIG. 2, there is a Cu thin film 52 on top, so the amount of Cu increases. That is, the ratio of Cu3Sn is increased while becoming (Cu, Ni)6Sn5 due to the upper Cu thin film 52 .

As shown in FIG. 4, in the elemental mapping image of Sn by FE-EPMA in the cross section of the joint, the ratio of the Cu3Sn layer thickness to the total thickness of the joint layer at the analysis point, that is, the ratio to the entire joint layer is The average is about 23%.

FIG. 9 is an elemental mapping image of Sn by FE-EPMA in the cross section of the joint in the conventional structure shown in FIG. As shown in FIG. 9, the ratio of the thickness of the Cu3Sn layer to the total thickness of the bonding layer at the analysis points, that is, the ratio to the total thickness of the bonding layer is about 11% on average.

From FIGS. 4 and 9, it can be seen that in this embodiment, the ratio of the Cu3Sn layer thickness is approximately double that of the conventional structure.
As shown in FIG. 5, in the elemental mapping image of Ni by FE-EPMA in the cross section of the joint, it is the layer 42 on the semiconductor chip 30 side of the intermetallic compound (IMC) layer having a two-layer structure (Cu , Ni) 6 Sn 5 , Ni is incorporated, so it can be seen that the layer 42 is a Ni-rich intermetallic compound layer.

As shown in FIG. 4, in the elemental mapping image of Sn by FE-EPMA in the cross section of the joint, cracks occurred in the conventional structure of FIG. 9 in comparison with the conventional structure of FIG. It can be seen that no cracks occurred in the morphology.

In the conventional structure shown in FIG. 19, as shown in FIGS. 10 and 11, the SEM image and backscattered electron image of the cross section of the joint show that cracks have occurred in the joint layer. On the other hand, in the present embodiment, as shown in FIGS. 6 and 7, in the SEM image and backscattered electron image of the cross section of the joint, the semiconductor chip 30 in the intermetallic compound (IMC) layer having the two-layer structure It can be seen that no cracks have occurred in the side layer 42 . Therefore, it can be seen that the supply of Ni has the effect of suppressing cracks.

In this way, by arranging Sn in layers using the Sn thin film 51 and performing Cu/Sn liquid phase diffusion bonding, lead-free, low-cost high-temperature bonding can be obtained.
In particular, an intermetallic compound layer 41 of Cu3Sn and an intermetallic compound layer 42 of (Cu, Ni)6Sn5 are formed on the bonding layer 40, and the melting points of Cu3Sn and (Cu, Ni)6Sn5 are 676° C. and 415° C., respectively. It has a high melting point and enables high temperature bonding. In the case of ordinary solder, it must be melted at the time of joining and the temperature must be raised above the melting point. However, at a low temperature of about 232 to 400° C., the melting point of Sn, liquid phase diffusion occurs and bonding becomes possible.

Specifically, on the substrate 20 side, a Ni thin film 50 is provided as a lower layer on the surface of the Cu wiring 22 of the substrate 20, and an Sn thin film 51 is provided as an upper layer. A Ni thin film 53 is also provided on the semiconductor chip 30 side. 19, 20, 8, 9, 10, and 11, in which cracks are generated by Ni diffusion, is changed to (Cu, Ni) 6Sn5 to prevent phase transformation, Cracks due to volume change are suppressed.

That is, in FIGS. 19, 20, 8, 9, 10, and 11, the Cu6Sn5 intermetallic compound in the Cu3Sn intermetallic compound layer 103 and the Cu6Sn5 intermetallic compound layer 104 constituting the bonding layer 102 Phase transformation occurs only in layer 104 at a certain temperature. Cu6Sn5 has the property of transforming its crystal structure into a hexagonal crystal structure at a high temperature range of 186°C or higher and to a monoclinic crystal structure at a temperature lower than 186°C. Although it is cooled, it is forced cooling under control in the bonding furnace instead of natural cooling, and since the cooling rate in the bonding furnace is high at that time, the time required for phase transformation cannot be satisfied. Therefore, even if the temperature is less than 186° C., it does not transform into the monoclinic crystal, which is a stable phase at low temperatures, and remains as a hexagonal crystal. As a result, since the hexagonal crystal structure is not stable at low temperatures, it is in an unstable state, and gradually undergoes a phase transformation to monoclinic crystals even if left at room temperature. Also, the progress of the phase transformation is accelerated by the temperature rise. During this phase transformation, the volume of the intermetallic compound layer 104 of Cu6Sn5 increases by about 2%, and strain is generated, which contributes to the generation of cracks.

In this embodiment, the Sn thin film 51 is provided on the surface of the Cu wiring 22 via the Ni thin film 50, and the Ni thin film 53 is provided on the semiconductor chip 30 side, thereby changing Cu6Sn5 to (Cu, Ni)6Sn5 by Ni diffusion. prevent phase transformation. As a result, the occurrence of cracks in the bonding layer 40 due to volume change can be suppressed.

A Cu thin film 52 is formed on the semiconductor chip 30 side. As a result, Cu diffusion is promoted to change Cu6Sn5 into Cu3Sn, thereby reducing the proportion of Cu6Sn5, preventing phase transformation, and suppressing cracks due to volume change.

In this way, a lead-free high-temperature bonding material with high reliability, low cost, high workability, and high heat dissipation is provided, which greatly suppresses the occurrence of cracks due to the volume change accompanying the phase transformation of Cu6Sn5. be able to.

In addition, since Cu6Sn5 is changed to Cu3Sn, the melting point of SAC305 (Sn3Ag0.5Cu solder), which is a Pb-free low-temperature solder, is 217 to 228°C, and the melting point of Pb5Sn, which is a high-temperature Pb solder, is 303 (305)°C. On the other hand, Cu3Sn has a melting point of 676° C., and Cu6Sn5 has a melting point of 415° C., so that a connection structure with a higher melting point can be obtained.

In addition, SAC305 (Sn3Ag0.5Cu solder), which is a Pb-free low-temperature solder, has a thermal conductivity of 22 to 55 W / mk and a layer thickness of about 50 to 150 μm, and Pb5Sn, which is a high-temperature Pb solder, has a thermal conductivity of 35.2 W. /mk, and the layer thickness is about 50 to 150 μm, while Cu3Sn has a thermal conductivity of 70 W/mk, and Cu6Sn5 has a thermal conductivity of 34 W/mk and a layer thickness of about 5 to 20 μm. Therefore, a connection structure with higher heat dissipation can be obtained.

In addition, SAC305 (Sn3Ag0.5Cu solder), which is a Pb-free low-temperature solder, has an electrical resistivity of 11 to 15 μΩcm and a layer thickness of about 50 to 150 μm. While the thickness is about 50 to 150 μm, Cu3Sn has an electrical resistivity of 8.9 μΩcm, Cu6Sn5 has an electrical resistivity of 17.5 μΩcm, and the layer thickness is about 5 to 20 μm. connection structure can be obtained.

According to the above embodiment, the following effects can be obtained.
(1) As the bonding structure 10 in which the bonding layer 40 is formed between the Cu wiring 22 and the semiconductor chip 30, the bonding layer 40 consists of the Cu3Sn intermetallic compound layer 41 on the Cu wiring 22 side and the Cu3Sn intermetallic compound layer 41 on the semiconductor chip 30 side. It forms a two-layer structure with an intermetallic compound layer 42 of (Cu, Ni)6Sn5. Therefore, compared to the case where the bonding layer has a two-layer structure of a Cu3Sn intermetallic compound layer on the Cu wiring side and a Cu6Sn5 intermetallic compound layer on the semiconductor chip side, the volume change due to the phase transformation of Cu6Sn5 It is possible to suppress the occurrence of cracks.

(2) As a liquid phase diffusion bonding method for bonding the Cu wiring 22 and the semiconductor chip 30, a Ni thin film is sequentially formed between the Cu wiring 22 and the semiconductor chip 30 from the Cu wiring 22 side toward the semiconductor chip 30 side. 50, the Sn thin film 51, the Ni thin film 53, and the Cu thin film 52 are sandwiched, and the Cu wiring 22 and the semiconductor chip 30 are bonded in an atmosphere at a temperature higher than the melting point of Sn. Therefore, the bonding layer 40 has a two-layer structure of the Cu3Sn intermetallic compound layer 41 on the Cu wiring 22 side and the (Cu,Ni)6Sn5 intermetallic compound layer 42 on the semiconductor chip 30 side. , Compared to the case of forming a two-layer structure of a Cu3Sn intermetallic compound layer on the Cu wiring side and a Cu6Sn5 intermetallic compound layer on the semiconductor chip side, the occurrence of cracks due to the volume change accompanying the phase transformation of Cu6Sn5 is suppressed. can be suppressed.

Embodiments are not limited to the above, and may be embodied as follows, for example.
○ As shown in FIG. 12, as a liquid-phase diffusion bonding method for bonding the Cu wiring 22 and the semiconductor chip 30, between the Cu wiring 22 and the semiconductor chip 30, from the Cu wiring 22 side to the semiconductor chip 30 side With the Ni thin film 60, the Sn thin film 61, and the Cu thin film 62 sandwiched in order, the Cu wiring 22 and the semiconductor chip 30 may be joined in an atmosphere at a temperature higher than the melting point of Sn.

Specifically, a Sn thin film 61 is formed on the Cu wiring 22 with a Ni thin film 60 interposed therebetween. A Cu thin film 62 is formed on the back electrode 31 of the semiconductor chip 30 and an Au thin film 63 is formed on the surface of the Cu thin film 62 .

The thickness t10 of the Ni thin film 60 is 0.5 to 1.5 μm, the thickness t11 of the Sn thin film 51 is 5 μm, the thickness t12 of the Cu thin film 62 is 0.5 to 1.0 μm, and the thickness of the Au thin film 63 is 0.5 to 1.0 μm. The thickness t13 is 0.1 μm.

Specifically, for example, the thickness t10 of the Ni thin film 60 is 0.5 μm, the thickness t11 of the Sn thin film 61 is 5 μm, and the thickness t12 of the Cu thin film 62 is 0.5 μm. In addition, for example, the thickness t10 of the Ni thin film 60 is 1.0 μm, the thickness t11 of the Sn thin film 61 is 5 μm, and the thickness t12 of the Cu thin film 62 is 0.5 μm. In addition, for example, the thickness t10 of the Ni thin film 60 is 1.5 μm, the thickness t11 of the Sn thin film 61 is 5 μm, and the thickness t12 of the Cu thin film 62 is 0.5 μm. In addition, for example, the thickness t10 of the Ni thin film 60 is 0.5 μm, the thickness t11 of the Sn thin film 61 is 5 μm, and the thickness t12 of the Cu thin film 62 is 1.0 μm. In addition, for example, the thickness t10 of the Ni thin film 60 is 1.0 μm, the thickness t11 of the Sn thin film 61 is 5 μm, and the thickness t12 of the Cu thin film 62 is 1.0 μm. In addition, for example, the thickness t10 of the Ni thin film 60 is 1.5 μm, the thickness t11 of the Sn thin film 61 is 5 μm, and the thickness t12 of the Cu thin film 62 is 1.0 μm.

According to this, the melting point of Sn is By bonding the Cu wiring 22 and the semiconductor chip 30 under the above temperature atmosphere, the bonding layers are formed into a Cu3Sn intermetallic compound layer 41 on the Cu wiring 22 side and a (Cu, Ni) bonding layer on the semiconductor chip 30 side. Since it has a two-layer structure with the intermetallic compound layer 42 of 6Sn5, when the bonding layer has a two-layer structure of the intermetallic compound layer of Cu3Sn on the Cu wiring side and the intermetallic compound layer of Cu6Sn5 on the semiconductor chip side. Compared to , it is possible to suppress the occurrence of cracks due to the volume change accompanying the phase transformation of Cu6Sn5.

In FIG. 12, when the Cu thin film 62 is provided on the semiconductor chip 30 side, it is difficult to form the Cu thin film 62 thickly. Therefore, it is difficult to replace all of Cu6Sn5 with Cu3Sn, and Cu6Sn5 tends to remain. Phase transformation that causes cracks can be suppressed.

In other words, the diffusion of Ni into Sn is not as easy as that of Cu, and the amount of diffusion is limited, so the incorporation of Ni into Cu6Sn5 is not sufficient and all Cu6Sn5 is replaced by (Cu,Ni)6Sn5. difficult to replace. It is conceivable to increase the thickness of the Ni thin film 60 to increase the amount of Ni supplied, but even in that case it is difficult to completely eliminate Cu6Sn5, and if the thickness of the Ni thin film 60 is increased, the It may become a barrier layer and hinder the diffusion of Cu from the underlying Cu wiring 22 . 2 and 12, in FIG. 2, Ni can be supplied from both the upper and lower sides of the Cu wiring 22 side and the semiconductor chip 30 side. That is, as described above, the diffusion of Ni into Sn is less than that of Cu, and it is difficult for the diffused Ni to spread evenly throughout the Sn thin film. Therefore, with only the Ni thin film 60 on the side of the Cu wiring 22 in FIG. 12, the range of diffusion into Sn tends to be biased toward the side of the Cu wiring 22, and the amount of diffusion on the side of the semiconductor chip 30 is inevitably small. On the other hand, Cu6Sn5 into which Ni is to be incorporated exists on the semiconductor chip 30 side. Therefore, it is difficult to sufficiently replace Cu6Sn5 present on the semiconductor chip 30 side with (Cu, Ni)6Sn5 only with the Ni thin film 60 on the Cu wiring 22 side in FIG. In FIG. 2, since the amount of Ni supplied on the semiconductor chip 30 side increases, the replacement of Cu6Sn5, which is the IMC generated on the semiconductor chip 30 side, with (Cu, Ni)6Sn5 increases, and most (or all) of (Cu, Ni)6Sn5, and a layer in which Cu6Sn5 is slightly scattered can be formed. In addition to increasing the diffusion amount of Ni in FIG. Ni can be diffusely supplied.

Not all Cu6Sn5 is completely replaced with (Cu, Ni)6Sn5, and some Cu6Sn5 remains. However, even if Cu6Sn5 cannot be completely eliminated, a sufficient crack suppression effect can be obtained. That is, the smaller the Cu6Sn5 lumps, the smaller the stress associated with the volume change caused by the phase transformation, and the less cracks are generated. Moreover, even if a crack occurs, it is limited to a very small fine area and can be suppressed to a level that poses no problem in terms of reliability.

○ As shown in FIG. 13, as a liquid-phase diffusion bonding method for bonding the Cu wiring 22 and the semiconductor chip 30, between the Cu wiring 22 and the semiconductor chip 30, from the Cu wiring 22 side to the semiconductor chip 30 side With the Sn thin film 70, the Ni thin film 72, and the Cu thin film 71 sandwiched in order, the Cu wiring 22 and the semiconductor chip 30 may be bonded together in an atmosphere at a temperature higher than the melting point of Sn.

Specifically, a Sn thin film 70 is formed on the Cu wiring 22 . A Ni thin film 72 is formed on the rear surface electrode 31 of the semiconductor chip 30 with a Cu thin film 71 interposed therebetween, and an Au thin film 73 is formed on the surface of the Ni thin film 72 .

The thickness t20 of the Sn thin film 70 is 5 μm, the thickness t21 of the Cu thin film 71 is 0.5 to 1.0 μm, the thickness t22 of the Ni thin film 72 is 0.5 to 1.0 μm, and the thickness t22 of the Au thin film 73 is 0.5 to 1.0 μm. The thickness t23 is 0.1 μm.

Specifically, for example, the thickness t20 of the Sn thin film 70 is 5 μm, the thickness t21 of the Cu thin film 71 is 0.5 μm, and the thickness t22 of the Ni thin film 72 is 1.0 μm. In addition, for example, the thickness t20 of the Sn thin film 70 is 5 μm, the thickness t21 of the Cu thin film 71 is 1.0 μm, and the thickness t22 of the Ni thin film 72 is 0.5 μm.

According to this, the melting point of Sn is By bonding the Cu wiring 22 and the semiconductor chip 30 under the above temperature atmosphere, the bonding layers are formed into a Cu3Sn intermetallic compound layer 41 on the Cu wiring 22 side and a (Cu, Ni) bonding layer on the semiconductor chip 30 side. Since it has a two-layer structure with the intermetallic compound layer 42 of 6Sn5, when the bonding layer has a two-layer structure of the intermetallic compound layer of Cu3Sn on the Cu wiring side and the intermetallic compound layer of Cu6Sn5 on the semiconductor chip side. Compared to , it is possible to suppress the occurrence of cracks due to the volume change accompanying the phase transformation of Cu6Sn5.

(circle) you may make it show in FIG. 14 instead of FIG. In FIG. 14, as a liquid phase diffusion bonding method for bonding the Cu wiring 22 and the semiconductor chip 30, Sn is placed between the Cu wiring 22 and the semiconductor chip 30 in order from the Cu wiring 22 side toward the semiconductor chip 30 side. With the thin film 70, the Cu thin film 82, and the Ni thin film 81 sandwiched therebetween, the Cu wiring 22 and the semiconductor chip 30 are bonded together in an atmosphere at a temperature higher than the melting point of Sn. According to this, the bonding layer has a two-layer structure of the Cu3Sn intermetallic compound layer 41 on the Cu wiring 22 side and the (Cu,Ni)6Sn5 intermetallic compound layer 42 on the semiconductor chip 30 side. Compared to the case where the layer has a two-layer structure of a Cu3Sn intermetallic compound layer on the Cu wiring 22 side and a Cu6Sn5 intermetallic compound layer on the semiconductor chip 30 side, the volume change due to the phase transformation of Cu6Sn5 It is possible to suppress the occurrence of cracks.

Here, the Sn thin film 70 is formed on the Cu wiring 22 , the Ni thin film 81 and the Cu thin film 82 are formed on the semiconductor chip 30 in this order, and the Cu thin film 82 is arranged on the Sn thin film 70 . As a result, the Sn thin film 70 , the Cu thin film 82 , and the Ni thin film 81 are sandwiched between the Cu wiring 22 and the semiconductor chip 30 in this order from the Cu wiring 22 side toward the semiconductor chip 30 side.

14, the thickness t31 of the Ni thin film 81 is 0.5 μm, the thickness t32 of the Cu thin film 82 is 0.5 μm, the thickness t33 of the Au thin film 73 is 0.1 μm, The thickness t34 of the Sn thin film 70 is 5 μm.

Hereinafter, the case of FIG. 14 will be described in detail while comparing FIGS. 13 and 14. FIG.
In FIG. 13, a Cu thin film 71 is formed on the surface of the back electrode 31 of the semiconductor chip 30, and a Ni thin film 72 is formed on the surface of the Cu thin film 71. Easy to survive. As a result, the remaining upper Ni thin film 72 serves as a barrier layer for the lower Cu thin film 71 , and the diffusion of Cu from the Cu thin film 71 may be suppressed. In this case, the amount of Cu in the Sn thin film 70 is insufficient, and the conversion of the IMC Cu6Sn5 to Cu3Sn does not proceed sufficiently, resulting in a large amount remaining. ) There is a possibility that the conversion to 6Sn5 may not be completed and cracks may occur.

In FIG. 14, a Ni thin film 81 is formed on the surface of the back electrode 31 of the semiconductor chip 30 and a Cu thin film 82 is formed on the surface of the Ni thin film 81 . According to this structure, when die-bonding onto the Sn thin film 70 on the Cu wiring 22 on the substrate side, when the Cu thin film 82 and the Ni thin film 81 on the semiconductor chip 30 side diffuse into the Sn thin film 70 on the substrate side, Cu diffusion occurs not only from the Cu wiring 22 on the substrate side but also from the Cu thin film 82 on the semiconductor chip 30 side, and the absolute amount of Cu diffusion into the Sn thin film 70 increases.

Therefore, Cu3Sn and Cu6Sn5, which are two types of IMC (intermetallic compound) generated in the conventional structure, are changed to Cu3Sn by diffusing Cu into Cu6Sn5, and the existence ratio of Cu6Sn5 can be greatly reduced. Furthermore, Ni diffuses into the Sn thin film 70 from the Ni thin film 81 on the semiconductor chip 30 side, Ni is taken into the slightly remaining Cu6Sn5, and changes to (Cu, Ni)6Sn5, thereby preventing the occurrence of cracks. can be suppressed. Moreover, the Cu thin film 82 on the upper layer side diffuses into the Sn thin film 70 and disappears, and the Ni thin film 81 on the lower layer side does not easily diffuse. In other words, since the Cu thin film 82 is easily diffused, it can be prevented from diffusing and disappearing at the same time as the bonding, preventing the diffusion of Ni from the underlying Ni thin film 81 .

Cracks are generated mainly in Cu6Sn5 as described above, and are less likely to occur in Cu3Sn. Further, the occurrence of cracks in Cu6Sn5 is caused by volume change accompanying phase transformation, but (Cu, Ni)6Sn5 does not undergo phase transformation, so cracks do not occur.

Therefore, by increasing the amount of Cu diffusion into the Sn thin film 70 on the substrate side and by diffusing Ni, Cu6Sn5, which is prone to cracking, is reduced, and Cu3Sn, which is difficult to crack, and the remaining Cu6Sn5 ( By changing to Cu, Ni)6Sn5, the occurrence of cracks can be effectively suppressed.

Thus, the Ni thin film provided on the semiconductor chip 30 side is more difficult to diffuse than the Cu thin film. However, in FIG. 14, the Cu thin film 82 is arranged on the upper layer side and the Ni thin film 81 is arranged on the lower layer side. Ni thin film 81 does not hinder the diffusion of Cu, and Cu can be efficiently diffused and supplied into Sn thin film 70 .

As described above, Ni diffusion and Cu diffusion can be compatible, and both can be efficiently diffused into the Sn thin film 70 without impairing the diffusion of each other. As a result, Cu6Sn5 is reduced by Cu diffusion, and Ni is incorporated into the remaining Cu6Sn5 to change it to (Cu, Ni)6Sn5, which is less likely to undergo phase transformation. be able to.

In addition, in FIG. 14, film formation is not limited to sputtering film formation, vapor deposition film formation, plating film formation, and the like. Although the precision of the film thickness is high in the sputtering film formation, it is difficult to form a film with a thickness of 1 μm or more. On the other hand, plating is inferior to sputtering in film thickness accuracy, but can increase the thickness. Therefore, the film thickness can be set by appropriately selecting each of these film forming methods. As for the thickness, since Cu of the Cu thin film 82 is easily diffused, even if the thickness t32 of the Cu thin film 82 is set to, for example, about 2 μm, the diffusion of the underlying Ni thin film 81 is not hindered. The thickness t31 of the lower layer Ni thin film 81 can also be increased within the range possible by the film forming method.

(circle) you may make it show in FIG. 15 as a modification of FIG. In FIG. 15, as a liquid phase diffusion bonding method for bonding the Cu wiring and the semiconductor chip 30, a Ni thin film is sequentially formed between the Cu wiring 22 and the semiconductor chip 30 from the Cu wiring 22 side toward the semiconductor chip 30 side. 91, with the Sn thin film 51, the Cu thin film 82, and the Ni thin film 81 sandwiched therebetween, the Cu wiring 22 and the semiconductor chip 30 are bonded together in an atmosphere at a temperature higher than the melting point of Sn. According to this, the bonding layer has a two-layer structure of the Cu3Sn intermetallic compound layer 41 on the Cu wiring 22 side and the (Cu,Ni)6Sn5 intermetallic compound layer 42 on the semiconductor chip 30 side. Compared to the case where the layer has a two-layer structure of a Cu3Sn intermetallic compound layer on the Cu wiring side and a Cu6Sn5 intermetallic compound layer on the semiconductor chip side, cracks due to volume change accompanying phase transformation of Cu6Sn5 are less likely to occur. The occurrence can be suppressed.

Here, the Ni thin film 91 and the Sn thin film 51 are formed in order on the Cu wiring 22 , the Ni thin film 81 and the Cu thin film 82 are formed in order on the semiconductor chip 30 , and the Cu thin film 51 is formed on the Sn thin film 51 . By disposing the thin film 82, the Ni thin film 91, the Sn thin film 51, the Cu thin film 82, and the Ni thin film 81 are sandwiched between the Cu wiring 22 and the semiconductor chip 30 in this order from the Cu wiring 22 side toward the semiconductor chip 30 side. state.

Thus, the Ni thin film 91 is arranged between the Cu wiring 22 and the Sn thin film 51 on the substrate side. If the thickness t41 of the Ni thin film 91 is too thick, it becomes a barrier layer and prevents the Cu wiring 22 from diffusing. Preferably, the thickness t41 of the Ni thin film 91 is set to 0.1 to 0.3 μm. In this case, the Ni thin film 91 can be arranged without hindering the diffusion of the Cu wiring 22 below.

Further, diffusion of the Ni thin film 81 on the semiconductor chip 30 side into the Sn thin film 51 is not as easy as that of Cu. Therefore, when diffusing Ni from the Ni thin film 81 to the Sn thin film 51, it is more effective to diffuse Ni from the Ni thin film 91 as shown in FIG.

More specifically, when both the Ni thin film 81 and the Ni thin film 91 are provided, diffusion into the Sn thin film 51 is relatively easy. That is, compared with the case where only the Ni thin film 81 is arranged without the Ni thin film 91, the arrangement of the Ni thin film 91 makes it easier for Ni to diffuse from the Ni thin film 91 on the substrate side into the Sn thin film 51. It is presumed that diffusion into the Sn thin film 51 is facilitated as a result of the induction of diffusion from the Ni thin film 81 on the side of the semiconductor chip 30 where diffusion is relatively difficult. Diffusion from the Ni thin film 91 on the substrate side into the Sn thin film 51 is relatively easier than diffusion from the Ni thin film 81 into the Sn thin film 51 because the Ni thin film 91 and the Sn thin film 51 are separated by plating, for example. While the semiconductor chips 30 are laminated and closely attached, the separate semiconductor chip 30 is only mounted on the Sn thin film 51 by die mounting, and the mounting surface is not in close contact. The reason for this is thought to be that they are separated by minute gaps. Furthermore, since the Ni thin film 91 on the substrate side is formed over a wide area on the entire surface of the Cu wiring 22, Ni is easily diffused and supplied also from the periphery outside the region where the semiconductor chip 30 is mounted. The Ni thin film 81 on the 30 side is arranged only in the mounting area of the semiconductor chip 30 . Therefore, since the Ni thin film 81 does not exist outside the arrangement area of the semiconductor chip 30 (because Ni is not diffused and supplied from outside the semiconductor chip arrangement area), the absolute amount of Ni diffused into the Sn thin film 51 is This is thought to be the reason why the diffusion from the Ni thin film 91 into the Sn thin film 51 is relatively easier than the diffusion from the Ni thin film 81 into the Sn thin film 51 .

(circle) it is good also as a structure shown in FIG. 16 instead of FIG. In FIG. 16, the intermetallic compound layer 41 of Cu3Sn and the intermetallic compound layer 42 of (Cu,Ni)6Sn5 each have a network structure of the intermetallic compound with Sn single phase in the gaps.

The Cu3Sn intermetallic compound layer 41 has an intermetallic compound (IMC) 41a dispersed in a single Sn phase 41b, and has a three-dimensional mesh-like intermetallic compound 41a. That is, it has a network structure of the intermetallic compound 41a with the Sn single phase 41b in the gaps. More specifically, the Cu3Sn intermetallic compound layer 41 is intricately composed of an intermetallic compound 41a forming a three-dimensional network and a single Sn phase 41b in the interstices of the network.

The (Cu,Ni)6Sn5 intermetallic compound layer 42 has an intermetallic compound (IMC) 42a dispersed in a single Sn phase 42b, and has a three-dimensional mesh-like intermetallic compound 42a. That is, it has a network structure of the intermetallic compound 42a with the Sn single phase 42b in the gaps. Specifically, the intermetallic compound layer 42 of (Cu, Ni)6Sn5 is composed of intermetallic compounds 42a forming a three-dimensional network and Sn single phases 42b in the interstices of the network.

Thus, the intermetallic compound layer 41 of Cu3Sn and the intermetallic compound layer 42 of (Cu, Ni)6Sn5 respectively have intermetallic compounds 41a and 42a forming a three-dimensional network structure, and are bonded in a network structure. It is layered. More specifically, the intermetallic compound layer 41 of Cu3Sn and the intermetallic compound layer 42 of (Cu,Ni)6Sn5 respectively form a three-dimensional mesh and are interconnected between the intermetallic compounds 41a and 42a and the gaps in the mesh. The Sn single phases 41b and 42b are intricate. More specifically, the intermetallic compound layer 41 of Cu3Sn and the intermetallic compound layer 42 of (Cu,Ni)6Sn5 respectively have Sn single phases 41b and 42b in the interstices of the intermetallic compounds 41a and 42a, and , at least part of the boundaries between the intermetallic compounds 41a, 42a and the single Sn phases 41b, 42b are non-linear and have an intricate structure.

In addition, although the intermetallic compounds 41a and 42a in FIG. 16 are shown as if they are separated from each other, the figure is a schematic representation of one cross section in an easy-to-understand manner, and is actually three-dimensional. are connected to each other in a network state.

In this way, the intermetallic compound layer 41 of Cu3Sn and the intermetallic compound layer 42 of (Cu, Ni)6Sn5 are not microscopically single layers, but have a structure in which each IMC and Sn are intertwined. , and the IMCs are connected to each other in a network to obtain high-temperature bonding. In this structure, Sn enters and exists in the gaps of the IMC network, and the IMC is also connected in a network state, so that a certain stress relaxation effect can be obtained and reliability can be ensured.

○ Although the film thicknesses of Cu (t3, t12, t21) and the film thicknesses of Ni (t1, t4, t10, t22) in FIGS.
(circle) although the film thickness of Sn was illustrated as 5 micrometers, it is not limited to this. For example, it may be 3 μm, 4 μm, or 6 μm.

○ It is not always necessary to have a Cu3Sn intermetallic compound layer in the bonding layer. In other words, the Cu diffusion state varies, and the amount of Cu diffusion may be small. In addition, when the Ni layer is laminated on the Cu wiring, the amount of Cu diffusion is further reduced. As a result, the Cu3Sn layer may not occur. However, even in that case, by diffusing Ni, Cu6Sn5 can be sufficiently replaced with (Cu, Ni)6Sn5, and cracks can be suppressed.

That is, as shown in FIG. 17 instead of FIG. 1, a bonding structure in which a bonding layer 45 is formed between the Cu wiring 22 and the semiconductor chip 30, and the bonding layer 45 is made of (Cu, Ni)6Sn5 metal. It may be a one-layer structure consisting of an intercompound layer. According to this, since the bonding layer 45 has a one-layer structure composed of an intermetallic compound layer of (Cu, Ni)6Sn5, the bonding layer consists of the Cu3Sn intermetallic compound layer on the Cu wiring side and the Cu3Sn intermetallic compound layer on the semiconductor chip side. Compared to the case of forming a two-layer structure with an intermetallic compound layer of Cu6Sn5, it is possible to suppress the occurrence of cracks due to the volume change accompanying the phase transformation of Cu6Sn5.

○ The configuration is not limited to replacing all the Cu6Sn5 layers with (Cu, Ni)6Sn5. That is, there is variation in the diffusion state of Ni, and Cu6Sn5 may partially remain. Even in this case, generation of cracks is reduced as compared with the conventional structure, and the effect of suppressing cracks can be obtained.

That is, as shown in FIG. 18 instead of FIG. 1, the bonding structure has a bonding layer 46 formed between the Cu wiring 22 and the semiconductor chip 30. The bonding layer 46 is composed of (Cu, Ni)6Sn5 and Cu6Sn5. It may be a one-layer structure consisting of an intermetallic compound layer in which According to this, since the bonding layer 46 has a one-layer structure composed of an intermetallic compound layer in which (Cu, Ni)6Sn5 and Cu6Sn5 are mixed, the bonding layer is the Cu3Sn intermetallic compound layer on the Cu wiring side. , the occurrence of cracks due to the volume change due to the phase transformation of Cu6Sn5 can be suppressed as compared with the case of forming a two-layer structure with the intermetallic compound layer of Cu6Sn5 on the semiconductor chip side.

○ The bonding temperature is not limited to 300°C. At least the melting point of Sn is 232° C. or higher.
(circle) the back electrode (Ti/Ni/Ag) 31 desirably includes at least a Ti layer.

DESCRIPTION OF SYMBOLS 10... Joining structure 22... Cu wiring 30... Semiconductor chip 40... Joining layer 41... Intermetallic compound layer of Cu3Sn 42... Intermetallic compound layer of (Cu, Ni)6Sn5 45... Joining layer 46... Bonding layer 50... Ni thin film, 51... Sn thin film, 52... Cu thin film, 53... Ni thin film, 60... Ni thin film, 61... Sn thin film, 62... Cu thin film, 70... Sn thin film, 71... Cu thin film, 72... Ni thin film, 81... Ni thin film, 82... Cu thin film, 91... Ni thin film.

Claims (10)

A bonding structure in which a bonding layer is formed between a Cu wiring and a semiconductor chip,
The bonding structure is characterized in that the bonding layer has a two-layer structure of a Cu3Sn intermetallic compound layer on the Cu wiring side and a (Cu,Ni)6Sn5 intermetallic compound layer on the semiconductor chip side. A bonding structure in which a bonding layer is formed between a Cu wiring and a semiconductor chip,
A bonding structure, wherein the bonding layer has a one-layer structure composed of an intermetallic compound layer of (Cu, Ni)6Sn5. A bonding structure in which a bonding layer is formed between a Cu wiring and a semiconductor chip,
A bonding structure, wherein the bonding layer has a one-layer structure composed of an intermetallic compound layer in which (Cu, Ni)6Sn5 and Cu6Sn5 are mixed. A liquid phase diffusion bonding method for bonding a Cu wiring and a semiconductor chip,
Between the Cu wiring and the semiconductor chip, a Ni thin film, a Sn thin film, a Ni thin film, and a Cu thin film having a thickness of 0.5 μm to 1.0 μm are sandwiched in order from the Cu wiring side to the semiconductor chip side, A liquid phase diffusion bonding method, wherein the Cu wiring and the semiconductor chip are bonded in an atmosphere at a temperature higher than the melting point of Sn. A liquid phase diffusion bonding method for bonding a Cu wiring and a semiconductor chip,
The melting point of Sn is A liquid-phase diffusion bonding method, wherein the Cu wiring and the semiconductor chip are bonded under the temperature atmosphere described above. A liquid phase diffusion bonding method for bonding a Cu wiring and a semiconductor chip,
In a state in which a Sn thin film, a Ni thin film, and a Cu thin film are sandwiched in order from the Cu wiring side to the semiconductor chip side between the Cu wiring and the semiconductor chip, the Cu wiring is heated in an atmosphere at a temperature equal to or higher than the melting point of Sn. and the semiconductor chip. A liquid phase diffusion bonding method for bonding a Cu wiring and a semiconductor chip,
In a state where a Sn thin film, a Cu thin film, and a Ni thin film are sandwiched in order from the Cu wiring side to the semiconductor chip side between the Cu wiring and the semiconductor chip, the Cu wiring is heated in a temperature atmosphere equal to or higher than the melting point of Sn. and the semiconductor chip. In the liquid phase diffusion bonding method according to claim 7,
A Sn thin film is formed on the Cu wiring, and a Ni thin film and a Cu thin film are formed on the semiconductor chip in this order. By disposing the Cu thin film on the Sn thin film, the Cu wiring and the semiconductor chip, a Sn thin film, a Cu thin film, and a Ni thin film are sandwiched in order from the Cu wiring side to the semiconductor chip side. A liquid phase diffusion bonding method for bonding a Cu wiring and a semiconductor chip,
Ni thin film, Sn thin film, Cu thin film, and Ni thin film are sandwiched between the Cu wiring and the semiconductor chip in this order from the Cu wiring side to the semiconductor chip side, in an atmosphere at a temperature higher than the melting point of Sn, A liquid phase diffusion bonding method, wherein the Cu wiring and the semiconductor chip are bonded together. In the liquid phase diffusion bonding method according to claim 9,
An Ni thin film and an Sn thin film are formed in order on the Cu wiring, and an Ni thin film and a Cu thin film are formed in order on the semiconductor chip, and the Cu thin film is arranged on the Sn thin film. Ni thin film, Sn thin film, Cu thin film, and Ni thin film are sandwiched in order from the Cu wiring side to the semiconductor chip side between the Cu wiring and the semiconductor chip by liquid phase diffusion bonding. Method.