JP4703492B2 - Lead-free solder material - Google Patents
Lead-free solder material Download PDFInfo
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- JP4703492B2 JP4703492B2 JP2006160824A JP2006160824A JP4703492B2 JP 4703492 B2 JP4703492 B2 JP 4703492B2 JP 2006160824 A JP2006160824 A JP 2006160824A JP 2006160824 A JP2006160824 A JP 2006160824A JP 4703492 B2 JP4703492 B2 JP 4703492B2
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/732—Location after the connecting process
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- H01L2224/73265—Layer and wire connectors
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Abstract
Description
本発明は、電子機器、電気機器、機械部品などの組立で用いられる鉛フリーはんだ材料に関する。 The present invention, electronic equipment, electrical equipment, relates to lead-free solder material that is used in the assembly of machine parts.
半導体装置は、一般に半導体素子（半導体チップ）と基材とを具備し、半導体素子は、はんだ材料などにより基材に接合されている。パワーデバイス製品のような半導体装置は、放熱特性を必要とするため、基材となるリードフレームには放熱部が設けられており、半導体素子は放熱部に接合されている。 A semiconductor device generally includes a semiconductor element (semiconductor chip) and a base material, and the semiconductor element is bonded to the base material with a solder material or the like. Since a semiconductor device such as a power device product requires heat dissipation characteristics, a lead frame serving as a base is provided with a heat dissipation portion, and the semiconductor element is bonded to the heat dissipation portion.
半導体素子とリードフレームの放熱部とを接合する工程は、ダイボンド工程と呼ばれる。ダイボンド工程の後、半導体素子とリードフレームとの接合体は、ワイヤーボンド工程やリフロー工程を経て、最終製品となる。 The process of joining the semiconductor element and the heat dissipation part of the lead frame is called a die bonding process. After the die bonding process, the joined body of the semiconductor element and the lead frame is a final product through a wire bonding process and a reflow process.
従来のパワーデバイス製品は、ダイボンド工程において、一般的にＰｂとＳｎとを含む合金（Ｐｂ−Ｓｎ合金）からなる高温はんだ材料を用いている（特許文献１参照）。Ｐｂ−Ｓｎ合金の融点は、３００℃近傍であるため、ワイヤーボンド工程やリフロー工程による加熱では、Ｐｂ−Ｓｎ合金の再溶融は起こりにくい。よって、作業工程において、半導体素子とリードフレームの放熱部との間で、ボイドの発生が防止され、良好な放熱特性が確保される。 Conventional power device products use a high-temperature solder material generally made of an alloy containing Pb and Sn (Pb—Sn alloy) in a die bonding process (see Patent Document 1). Since the melting point of the Pb—Sn alloy is around 300 ° C., remelting of the Pb—Sn alloy hardly occurs by heating in the wire bonding process or the reflow process. Therefore, in the work process, generation of voids is prevented between the semiconductor element and the heat dissipation portion of the lead frame, and good heat dissipation characteristics are ensured.
Ｐｂ−Ｓｎ合金は、熱伝導性にも優れており、更に、硬度が２５Ｈｖ程度と低いため、均一なワイヤー形状に容易に加工できる。よって、はんだ材料を半導体素子やリードフレームの接合面に供給する際、はんだ材料の供給量のバラツキが抑制され、効率的に作業を行うことができる。 The Pb—Sn alloy is excellent in thermal conductivity and has a hardness as low as about 25 Hv, so that it can be easily processed into a uniform wire shape. Therefore, when supplying the solder material to the bonding surface of the semiconductor element or the lead frame, the variation in the supply amount of the solder material is suppressed, and the work can be performed efficiently.
更に、Ｐｂ−Ｓｎ合金は、半導体素子を構成するＳｉなどの線膨張係数と、一般的に使用されているリードフレーム（主に銅製）の線膨張係数との差を緩和する機能を有するため、半導体素子にクラック等が発生するのを防止できる。
近年、環境規制の観点から、鉛を含まないはんだ材料（鉛フリーはんだ材料）の開発が積極的に進められている。しかし、パワーデバイス製品には放熱特性が要求され、更に、リフロー工程の際には、はんだ材料が再溶融しないことが要求される。 In recent years, from the viewpoint of environmental regulations, development of solder materials that do not contain lead (lead-free solder materials) has been actively promoted. However, power device products are required to have heat dissipation characteristics, and further, it is required that the solder material does not remelt during the reflow process .
一方、鉛フリーはんだ材料の多くは、融点が高い。融点の高い鉛フリーはんだ材料を溶融させるためには、製造設備の作業温度を上昇させる必要があり、設備投資のコストが高くなる。また、入手可能な鉛フリーはんだ材料は、Ｐｂ−Ｓｎ合金からなるはんだ材料と比較して硬度が高いため、リードフレームとの接合面において半導体素子に応力が発生しやすい。そのため、半導体素子にクラックが発生する場合があり、パワーデバイス製品の信頼性が低くなる。 On the other hand, many of the lead-free solder material, the melting point is not high. In order to melt a lead-free solder material having a high melting point, it is necessary to raise the operating temperature of the production facility, which increases the cost of capital investment. Moreover, since the available lead-free solder material has a higher hardness than a solder material made of a Pb—Sn alloy, stress is likely to be generated in the semiconductor element at the joint surface with the lead frame. Therefore, a crack may occur in the semiconductor element, and the reliability of the power device product is lowered.
本発明は、上記を鑑み、従来の作業温度を大幅に上昇させることがなく、半導体素子にクラックが発生する確率を低減することができる鉛フリーはんだ材料を提供することを目的の１つとする。 In view of the above, it is an object of the present invention to provide a lead-free solder material that can reduce the probability of occurrence of cracks in a semiconductor element without significantly increasing the conventional working temperature.
本発明は、Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金１００質量部と、０．０５〜２質量部の残部Ｓｎとで構成される鉛フリーはんだ材料であり、Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金は、第１共晶合金であるＺｎ−Ａｌ合金と第２共晶合金であるＧｅ−Ｎｉ合金とからなり、Ｚｎ、Ａｌ、ＧｅおよびＮｉの含有量がそれぞれ９４．３質量％、５質量％、０．５質量％および０．２質量％である、鉛フリーはんだ材料（鉛フリーはんだ材料Ａ）に関する。 The present invention is a lead-free solder material composed of 100 parts by mass of a Zn-Al-Ge-Ni alloy and 0.05 to 2 parts by mass of the remaining Sn, and the Zn-Al-Ge-Ni alloy It consists of a Zn—Al alloy that is a 1 eutectic alloy and a Ge—Ni alloy that is a second eutectic alloy , and the contents of Zn, Al, Ge, and Ni are 94.3 mass%, 5 mass%, and 0. 5 wt% and Ru 0.2% by mass, related to lead-free solder material (lead-free solder material A).
本発明によれば、Ｚｎ−Ａｌ合金からなる第１共晶合金とＧｅ−Ｎｉ合金からなる第２共晶合金とを含む合金（Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金）からなる鉛フリーはんだ材料の融点を低下させると共に、その硬度を低減できる。よって、例えば２５０〜３５０℃の融点を有し、加工性に優れ、かつ、半導体素子と基材との線膨張係数の差による応力を緩和できる鉛フリーはんだ材料を提供できる。 According to the present invention, a lead-free solder material made of an alloy (Zn—Al—Ge—Ni alloy) containing a first eutectic alloy made of a Zn—Al alloy and a second eutectic alloy made of a Ge—Ni alloy. The melting point can be lowered and the hardness can be reduced. Therefore, it is possible to provide a lead-free solder material having a melting point of, for example, 250 to 350 ° C., excellent workability, and capable of relieving stress due to a difference in linear expansion coefficient between the semiconductor element and the base material.
本発明によれば、電子部品、電子機器などの鉛フリー化が可能となるだけでなく、パワーデバイス製品のような半導体装置の製造工程において、作業温度を低くすることができる。よって、信頼性の高い製品を供給することができる。本発明の鉛フリーはんだは、ワイヤーや金属箔への加工が容易であり、作業効率も向上する。 According to the present invention, not only lead-free electronic parts and electronic equipment can be made, but also the working temperature can be lowered in the manufacturing process of a semiconductor device such as a power device product. Therefore, a highly reliable product can be supplied. The lead-free solder of the present invention can be easily processed into a wire or metal foil, and the working efficiency is improved.
実施の形態１
本実施形態は、第１共晶合金と第２共晶合金とを含む合金材料からなり、第１共晶合金は、Ｚｎ−Ａｌ合金からなり、第２共晶合金は、Ｇｅ−Ｎｉ合金からなり、合金材料は、更に、Ｓｎを含み、合金材料に含まれるＳｎの量が、第１共晶合金と第２共晶合金との合計１００質量部あたり、０．０５〜２質量部である、鉛フリーはんだ材料に関する。
Embodiment 1
The present embodiment is made of an alloy material including a first eutectic alloy and a second eutectic alloy, the first eutectic alloy is made of a Zn—Al alloy, and the second eutectic alloy is made of a Ge—Ni alloy. The alloy material further includes Sn, and the amount of Sn contained in the alloy material is 0.05 to 2 parts by mass per 100 parts by mass in total of the first eutectic alloy and the second eutectic alloy. , Relating to lead-free solder materials.
Ｚｎ−Ａｌ合金からなる第１共晶合金とＧｅ−Ｎｉ合金からなる第２共晶合金とを含む合金（Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金）は、本実施形態の鉛フリーはんだ材料の母材（ベース）となる。 An alloy (Zn-Al-Ge-Ni alloy) including a first eutectic alloy made of a Zn-Al alloy and a second eutectic alloy made of a Ge-Ni alloy is a base material of the lead-free solder material of the present embodiment. (Base).
第１共晶合金と第２共晶合金とを溶融状態で混合し、その後、凝固させると、均一な合金が得られる。しかし、合金を微視的に見ると、第１共晶合金と第２共晶合金とを区別できる。例えば、はんだ材料の断面を電子顕微鏡などで観察することにより、第１共晶合金と第２共晶合金の存在を観察することができる。 When the first eutectic alloy and the second eutectic alloy are mixed in a molten state and then solidified, a uniform alloy is obtained. However, when the alloy is viewed microscopically, the first eutectic alloy and the second eutectic alloy can be distinguished. For example, the presence of the first eutectic alloy and the second eutectic alloy can be observed by observing a cross section of the solder material with an electron microscope or the like.
ここで、Ｚｎ−Ａｌ合金とは、２〜７質量％（好ましくは約５質量％）のＡｌを含み、残部がＺｎからなる２元共晶合金を示す。Ｚｎ−Ａｌ合金は、約３８５℃の共晶点を有する。Ｇｅ−Ｎｉ合金とは、２０〜３８質量％（好ましくは約２８質量％）のＮｉを含み、残部がＧｅからなる２元共晶合金を示す。Ｇｅ−Ｎｉ合金は、約７７５℃の共晶点を有する。 Here, the Zn—Al alloy refers to a binary eutectic alloy containing 2 to 7 mass % (preferably about 5 mass %) of Al and the balance being Zn. The Zn—Al alloy has an eutectic point of about 385 ° C. The Ge—Ni alloy refers to a binary eutectic alloy containing 20 to 38 mass % (preferably about 28 mass %) of Ni and the balance being Ge. The Ge—Ni alloy has a eutectic point of about 775 ° C.
第１共晶合金と第２共晶合金との合計に占める第２共晶合金の含有量は、０．０５〜２質量％が好ましく、０．１〜１．５質量％が更に好ましく、０．３〜１質量％が特に好ましい。 The content of the second eutectic alloy in the total of the first eutectic alloy and the second eutectic alloy is preferably 0.05 to 2% by mass, more preferably 0.1 to 1.5% by mass , 3 to 1% by mass is particularly preferable.
母材、すなわちＺｎ−Ａｌ−Ｇｅ−Ｎｉ合金の融点は、３８５〜４２０℃であり、現行品であるＰｂ−Ｓｎ合金の融点（２９０〜３３０℃）よりも高くなっている。よって、Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金を溶融させ、半導体素子と基材とを接続するためには、製造設備の作業温度を、少なくとも現行より約６０℃程度上昇させる必要がある。しかし、作業温度を上昇させると、製造設備の熱劣化が起こりやすくなる。 The melting point of the base material, that is, the Zn—Al—Ge—Ni alloy is 385 to 420 ° C., which is higher than the melting point (290 to 330 ° C.) of the current Pb—Sn alloy. Therefore, in order to melt the Zn—Al—Ge—Ni alloy and connect the semiconductor element and the base material, it is necessary to raise the working temperature of the manufacturing facility at least about 60 ° C. from the current level. However, when the working temperature is raised, thermal deterioration of the production equipment is likely to occur.
Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金の硬度は、ビッカース硬度で、約９０Ｈｖであり、現行品であるＰｂ−Ｓｎ合金の硬度（約２５Ｈｖ）よりも高くなっている。よって、Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金を、例えばワイヤー状に均一に加工することは困難である。このことは、半導体素子や基材の接合面に、鉛フリーはんだ材料を供給する際に、はんだ材料の供給量にバラツキが生じることを意味する。 The hardness of the Zn—Al—Ge—Ni alloy is about 90 Hv in terms of Vickers hardness, which is higher than the hardness (about 25 Hv) of the current Pb—Sn alloy. Therefore, it is difficult to uniformly process a Zn—Al—Ge—Ni alloy into, for example, a wire shape. This means that the supply amount of the solder material varies when the lead-free solder material is supplied to the bonding surface of the semiconductor element or the base material.
鉛フリーはんだ材料の硬度を下げることは、融点を下げることと同様に、半導体装置の製造においては重要である。 Reducing the hardness of the lead-free solder material is important in the manufacture of semiconductor devices, as is reducing the melting point.
表１は、Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金にＳｎを添加した場合の融点と硬度を示している。ただし、Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金におけるＺｎ、Ａｌ、ＧｅおよびＮｉの含有量は、それぞれ９４．３質量％、５質量％、０．５質量％および０．２質量％である。表１中に示したＳｎの添加量（質量部）は、母材であるＺｎ−Ａｌ−Ｇｅ−Ｎｉ合金１００質量部あたりの量である。硬度比率は、Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金のビッカース硬度に対する、Ｓｎを添加した合金材料のビッカース硬度の割合を、百分率で示している。 Table 1 shows the melting point and hardness when Sn is added to the Zn—Al—Ge—Ni alloy. However, the contents of Zn, Al, Ge, and Ni in the Zn—Al—Ge—Ni alloy are 94.3 mass %, 5 mass %, 0.5 mass %, and 0.2 mass %, respectively. The addition amount (parts by mass ) of Sn shown in Table 1 is an amount per 100 parts by mass of the Zn—Al—Ge—Ni alloy as the base material. The hardness ratio indicates the percentage of the Vickers hardness of the alloy material added with Sn to the Vickers hardness of the Zn—Al—Ge—Ni alloy.
Ｓｎの添加量が２質量部を超えると、Ｚｎ中に固溶しないＳｎが遊離するため、Ｓｎの融点である２３２℃程度の低温で、合金材料の一部が溶融する。このような低融点成分がはんだ材料に含まれると、半導体装置を基板（マザーボード）に実装する際に、リフロー装置による加熱により、はんだ材料が再溶融する可能性がある。その結果、パワーデバイス製品などでは、半導体素子と基材との間にボイドが発生し、放熱特性が劣化する。よって、Ｓｎの添加量は、Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金１００質量部あたり、２質量部以下とすることが必要である。 When the addition amount of Sn exceeds 2 parts by mass , Sn that does not dissolve in Zn is liberated, so that a part of the alloy material melts at a low temperature of about 232 ° C., which is the melting point of Sn. When such a low melting point component is contained in the solder material, the solder material may be re-melted by heating by the reflow device when the semiconductor device is mounted on the substrate (motherboard). As a result, in power device products and the like, voids are generated between the semiconductor element and the base material, and the heat dissipation characteristics are deteriorated. Therefore, the addition amount of Sn needs to be 2 parts by mass or less per 100 parts by mass of the Zn—Al—Ge—Ni alloy.
表１から、Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金に、Ｓｎを添加することにより、合金材料の硬度が顕著に低下することがわかる。合金材料の硬度が低下すると、はんだ材料が供給される接合面における応力が緩和されやすい。 From Table 1, it can be seen that the hardness of the alloy material is significantly reduced by adding Sn to the Zn-Al-Ge-Ni alloy. When the hardness of the alloy material decreases, the stress at the joint surface to which the solder material is supplied is likely to be relaxed.
本実施形態の鉛フリーはんだ材料は、従来と同様に、ワイヤー、金属箔、インゴットなどの状態で、半導体素子や基材の接合面に供給することができる。鉛フリーはんだ材料の溶融を伴う接合は、水素ガスまたは窒素ガスを含む雰囲気中で行うことが好ましい。 The lead-free solder material of this embodiment can be supplied to the joining surface of a semiconductor element or a base material in the state of a wire, a metal foil, an ingot, or the like, as in the past. The joining involving melting of the lead-free solder material is preferably performed in an atmosphere containing hydrogen gas or nitrogen gas.
参考形態１
本参考形態は、第１共晶合金と第２共晶合金とを含む合金材料からなり、第１共晶合金は、Ｚｎ−Ａｌ合金からなり、第２共晶合金は、Ｇｅ−Ｎｉ合金からなり、合金材料は、更に、ＳｎおよびＩｎを含み、合金材料に含まれるＳｎの量が、第１共晶合金と第２共晶合金との合計１００質量部あたり、０．０５〜２質量部であり、合金材料に含まれるＩｎの量が、第１共晶合金と第２共晶合金との合計１００質量部あたり、０．０５〜３質量部である、鉛フリーはんだ材料に関する。
Reference form 1
This reference form is made of an alloy material including a first eutectic alloy and a second eutectic alloy, the first eutectic alloy is made of a Zn—Al alloy, and the second eutectic alloy is made of a Ge—Ni alloy. becomes, the alloy material further comprises Sn and in, the amount of Sn contained in the alloy material, the total weight per 100 parts by weight of the first eutectic alloy and a second eutectic alloy, 0.05-2 parts by weight , and the amount of in contained in the alloy material, the total weight per 100 parts by weight of the first eutectic alloy and a second eutectic alloy is 0.05 to 3 parts by weight, about lead-free solder material.
Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金に、Ｓｎと共に、Ｉｎを添加することにより、合金材料の融点と硬度を、更に低下させることができる。例えば、Ｚｎ−５Ａｌ−０．２Ｎｉ−０．５Ｇｅ（５質量％のＡｌと、０．２質量％のＮｉと、０．５質量％のＧｅを含み、残部がＺｎである合金）１００質量部に対し、２質量部のＳｎを添加すると、融点は約７．５℃程度低下し、硬度は約１４%程度低下する。このはんだ材料に、更に３質量部のＩｎを添加すると、融点は更に約７℃低下し、硬度は約１０％程度低下する。 By adding In together with Sn to the Zn—Al—Ge—Ni alloy, the melting point and hardness of the alloy material can be further reduced. For example, Zn-5Al-0.2Ni-0.5Ge (an alloy containing 5% by mass of Al, 0.2% by mass of Ni, 0.5% by mass of Ge and the balance being Zn) 100 parts by mass On the other hand, when 2 parts by mass of Sn is added, the melting point decreases by about 7.5 ° C., and the hardness decreases by about 14%. When 3 parts by mass of In is further added to this solder material, the melting point further decreases by about 7 ° C., and the hardness decreases by about 10%.
表２は、Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金にＳｎとＩｎとを添加した場合の融点と硬度を示している。ただし、Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金におけるＺｎ、Ａｌ、ＧｅおよびＮｉの含有量は、それぞれ９４．３質量％、５質量％、０．５質量％および０．２質量％である。表１中に示したＳｎおよびＩｎの添加量（質量部）は、母材であるＺｎ−Ａｌ−Ｇｅ−Ｎｉ合金１００質量部あたりの量である。硬度比率は、Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金のビッカース硬度に対する、ＳｎおよびＩｎを添加した合金材料のビッカース硬度の割合を、百分率で示している。
なお、Ｉｎの添加量が４質量％になると、Ｓｎ−Ｉｎ共晶合金（融点約１２０℃）の生成量が多くなる。
Table 2 shows the melting point and hardness when Sn and In are added to the Zn—Al—Ge—Ni alloy. However, the contents of Zn, Al, Ge, and Ni in the Zn—Al—Ge—Ni alloy are 94.3 mass %, 5 mass %, 0.5 mass %, and 0.2 mass %, respectively. The addition amount (parts by mass ) of Sn and In shown in Table 1 is an amount per 100 parts by mass of the Zn—Al—Ge—Ni alloy as the base material. The hardness ratio indicates the percentage of the Vickers hardness of the alloy material to which Sn and In are added with respect to the Vickers hardness of the Zn—Al—Ge—Ni alloy.
Note that when the amount of In added is 4% by mass, the amount of Sn—In eutectic alloy (melting point: about 120 ° C.) increases.
参考形態２
本参考形態は、第１共晶合金と第２共晶合金とを含む合金材料と、合金材料の表面を被覆する金属層とを含み、第１共晶合金は、Ｚｎ−Ａｌ合金からなり、第２共晶合金は、Ｇｅ−Ｎｉ合金からなり、金属層は、ＳｎまたはＳｎ−Ｉｎ合金からなる、鉛フリーはんだ材料に関する。Ｓｎの融点は２３２℃であり、Ｓｎ−Ｉｎ合金の融点は１２０℃である。これらの融点は、かなり低いため、本参考形態の鉛フリーはんだ材料は、半導体素子や基材の接合面との濡れ性に優れている。また、接合が完了した後には、金属層が合金材料に溶け込んでいるため、実施の形態１および参考形態１の鉛フリーはんだ材料を用いた場合と同様に、接続不良が生じにくく、半導体素子のクラックも生じにくい。
This reference form includes an alloy material containing a first eutectic alloy and a second eutectic alloy, and a metal layer covering the surface of the alloy material, and the first eutectic alloy is made of a Zn-Al alloy, The second eutectic alloy is made of a Ge—Ni alloy, and the metal layer is related to a lead-free solder material made of Sn or a Sn—In alloy. The melting point of Sn is 232 ° C., and the melting point of the Sn—In alloy is 120 ° C. These melting points, since much lower, lead-free solder material of this preferred embodiment is excellent in wettability between the bonding surfaces of the semiconductor elements and the substrate. In addition, since the metal layer is dissolved in the alloy material after the joining is completed, connection failure is unlikely to occur as in the case of using the lead-free solder material of Embodiment 1 and Reference Embodiment 1 , and the semiconductor element Cracks are less likely to occur.
金属層は、第１共晶合金と第２共晶合金とを含む合金材料の表面の少なくとも一部、または、表面全体を被覆している。第１共晶合金と第２共晶合金とを含む合金材料の形状は、特に限定されず、例えばワイヤー、シート（箔）、粒状物などの形状を有する。例えば、第１共晶合金と第２共晶合金とを含む合金材料がシート状である場合、金属層は、シートの少なくとも一方の面に形成されていればよいが、両面に形成されていることが好ましい。この場合、一方の面にＳｎからなる層を形成し、他方の面にＳｎ−Ｉｎ合金からなる層を形成してもよく、両面にＳｎからなる層またはＳｎ−Ｉｎ合金からなる層を形成してもよい。 The metal layer covers at least a part of the surface of the alloy material including the first eutectic alloy and the second eutectic alloy or the entire surface. The shape of the alloy material including the first eutectic alloy and the second eutectic alloy is not particularly limited, and for example, has a shape such as a wire, a sheet (foil), and a granular material. For example, when the alloy material including the first eutectic alloy and the second eutectic alloy is in the form of a sheet, the metal layer may be formed on at least one surface of the sheet, but is formed on both surfaces. It is preferable. In this case, a layer made of Sn may be formed on one side and a layer made of Sn—In alloy may be formed on the other side, and a layer made of Sn or a layer made of Sn—In alloy may be formed on both sides. May be.
図１は、本参考形態に係るシート（箔）状の鉛フリーはんだ材料の一例の断面を概念的に示している。シート状の鉛フリーはんだ材料１０は、第１共晶合金と第２共晶合金とを含む合金材料からなる内層１１と、上層金属層１２と、下層金属層１３とを具備する。上層金属層１２および下層金属層１３は、ＳｎまたはＳｎ−Ｉｎ合金からなり、例えばメッキ法により、合金材料からなる内層１１の表面に形成されている。
Figure 1 is an example of a cross section of a sheet (foil) shaped lead-free solder material according to this reference embodiment conceptually shown. The sheet-like lead-
上層金属層１２および下層金属層１３は、それぞれ独立に、Ｓｎ単体からなる層でもよく、Ｓｎ−Ｉｎ合金からなる層でもよい。内層１１の厚みをＴとするとき、上層金属層１２および下層金属層１３の厚みｔは、それぞれ０．００５≦ｔ／Ｔ≦０．３を満たすことが好ましく、０．０１≦ｔ／Ｔ≦０．１５を満たすことが更に好ましい。ただし、第１共晶合金と第２共晶合金とを含む合金材料からなる内層１００質量部あたり、Ｓｎが０．０５〜２質量部、Ｉｎが０．０５〜３質量部となるように、各層の厚みを制御することが望ましい。
The
Ｓｎ−Ｉｎ合金に含まれるＩｎの量は、特に限定されないが、例えば４０〜７０質量％であることが好ましい。参考形態３においても同様である。
The amount of In contained in the Sn—In alloy is not particularly limited, but is preferably 40 to 70% by mass , for example. The same applies to the
実施の形態２
本実施形態は、第１接合面を有する半導体素子と、第２接合面を有する基材と、第１接合面と第２接合面とを接合する鉛フリーはんだ材料とを含む半導体装置に関する。ここで、鉛フリーはんだ材料には、実施の形態１の鉛フリーはんだ材料を用いることができる。
The present embodiment relates to a semiconductor device including a semiconductor element having a first joint surface, a base material having a second joint surface, and a lead-free solder material that joins the first joint surface and the second joint surface. Here, the lead-free solder material of Embodiment 1 can be used as the lead-free solder material.
図２Ａは、本実施形態に係る半導体装置の一例を概念的に示す上面図である。図２Ｂは図２Ａのｂ−ｂ線断面図である。
半導体装置（例えばパワートランジスタ）２０は、下面に第１接合面を有する半導体素
子２１と、上面に第２接合面を有する放熱部２２ａを含む基材（リードフレーム）２２と、第1接合面と第２接合面とを接合する鉛フリーはんだ材料２３とを具備する。基材２２は、第１リード２４と一体となっている。半導体素子２１は、金属線２６を介して、２つの第２リード２５と接続されている。半導体素子２１、第２リード２５の一端および金属線２６は、破線で示した封止樹脂２７により封止されている。
FIG. 2A is a top view conceptually showing an example of the semiconductor device according to the present embodiment. 2B is a cross-sectional view taken along the line bb of FIG. 2A.
A semiconductor device (for example, a power transistor) 20 includes a
半導体素子や基材の接合面における応力を十分に緩和し、半導体装置の信頼性を十分に向上させる観点から、接合面における鉛フリーはんだ材料の厚み（半導体素子の第１接合面と、基材の放熱部の第２接合面との間の距離）は、４０μm以上とすることが好ましい。 The thickness of the lead-free solder material on the joint surface (the first joint surface of the semiconductor element and the base material) from the viewpoint of sufficiently relaxing the stress on the joint surface of the semiconductor element and the base material and sufficiently improving the reliability of the semiconductor device. The distance between the second heat sink and the second joint surface is preferably 40 μm or more.
参考形態３
本参考形態は、第１接合面を有する半導体素子と、第２接合面を有する基材と、第１接合面および第２接合面の少なくとも一方に存在する金属層と、第１接合面と第２接合面との間に付与される鉛フリーはんだ材料とを含み、鉛フリーはんだ材料は、第１共晶合金と第２共晶合金とを含む合金材料からなり、第１共晶合金は、Ｚｎ−Ａｌ合金からなり、第２共晶合金は、Ｇｅ−Ｎｉ合金からなり、金属層は、ＳｎまたはＳｎ−Ｉｎ合金からなる半導体装置部品の組み合わせに関する。
This reference form includes a semiconductor element having a first bonding surface, a base material having a second bonding surface, a metal layer present on at least one of the first bonding surface and the second bonding surface, the first bonding surface, A lead-free solder material applied between the two joint surfaces, the lead-free solder material is made of an alloy material containing a first eutectic alloy and a second eutectic alloy, and the first eutectic alloy is: It is made of a Zn—Al alloy, the second eutectic alloy is made of a Ge—Ni alloy, and the metal layer is related to a combination of semiconductor device parts made of Sn or Sn—In alloy.
図３は、本参考形態に係る半導体装置部品の組み合わせの一例を概念的に示す断面図である。半導体装置部品の組み合わせ３０は、以下の要領で得ることができる。
まず、第１接合部を有する半導体素子（例えばパワートランジスタ）３１と、第２接合部である放熱部３２ａ、第１リード３４および第２リード３５を有する基材（リードフレーム）３２とを作製する。
Figure 3 is a cross-sectional view schematically showing an example of a combination of the semiconductor device parts according to this preferred embodiment. The semiconductor
First, a semiconductor element (for example, a power transistor) 31 having a first junction, and a base material (lead frame) 32 having a
次に、第１接合部および第２接合部の少なくとも一方に、めっき法により、ＳｎまたはＳｎ−Ｉｎ合金からなる金属層３３ａを形成する。更に、第１接合部と第２接合部との間に、鉛フリーはんだ材料３３を介在させる。ここで、鉛フリーはんだ材料には、実施の形態１〜３の鉛フリーはんだ材料を用いることができる。その後、鉛フリーはんだ材料と金属層とを、加熱し、冷却すると、第１接合部と第２接合部とが接合される。
Next, a
次に、半導体素子３１と、第２リード３５とを、金属線３６を介して接続し、最後に、半導体素子３１、第２リード３５の一端および金属線３６を封止樹脂３７により封止することにより、実施の形態２と同様の半導体装置が得られる。
Next, the
このように、半導体素子や基材の接合面に、予め、低融点であるＳｎ層（融点２３２℃）またはＳｎ−Ｉｎ合金層（融点１２０℃）を形成しておくことにより、鉛フリーはんだ材料と、半導体素子や基材の接合面との濡れ性が向上する。また、接合が完了した後には、金属層が鉛フリーはんだ材料に溶け込んでいるため、実施の形態１および参考形態１の鉛フリーはんだ材料を用いた場合と同様に、接続不良が生じにくく、半導体素子のクラックも生じにくい。 Thus, a lead-free solder material is formed by previously forming a Sn layer (melting point 232 ° C.) or a Sn—In alloy layer (melting point 120 ° C.) having a low melting point on the bonding surface of the semiconductor element or the base material. And the wettability with the joint surface of a semiconductor element or a base material improves. In addition, since the metal layer is dissolved in the lead-free solder material after the joining is completed, the connection failure is less likely to occur as in the case where the lead-free solder material of the first embodiment and the reference embodiment 1 is used. It is difficult for the device to crack.
本発明の鉛フリーはんだ材料は、特に、パワーデバイス装置のような半導体装置に好適である。本発明を適用することで、従来のＰｂ−Ｓｎ合金からなるはんだ材料と同様の設備で半導体装置を生産することが可能となる。本発明は、フリップチップ、ＢＧＡ（BallGrid Array）、モジュールなどの接続用途にも適用できる。 The lead-free solder material of the present invention is particularly suitable for a semiconductor device such as a power device device. By applying the present invention, it becomes possible to produce a semiconductor device with the same equipment as a solder material made of a conventional Pb—Sn alloy. The present invention can also be applied to connection applications such as flip chip, BGA (BallGrid Array), and modules.
１０ 鉛フリーはんだ材料
１１ 内層
１２ 上層金属層
１３ 下層金属層
２０ 半導体装置
３０ 半導体装置部品の組み合わせ
２１、３１ 半導体素子
２２、３２ 基材
２２ａ、３２ａ 放熱部
２３、３３ 鉛フリーはんだ材料
２４、３４ 第１リード
２５、３５ 第２リード
２６、３６ 金属線
２７、３７ 封止樹脂
３３ａ 金属層
DESCRIPTION OF
Claims (1)
前記Ｚｎ−Ａｌ−Ｇｅ−Ｎｉ合金は、第１共晶合金であるＺｎ−Ａｌ合金と第２共晶合金であるＧｅ−Ｎｉ合金とからなり、Ｚｎ、Ａｌ、ＧｅおよびＮｉの含有量がそれぞれ９４．３質量％、５質量％、０．５質量％および０．２質量％である、鉛フリーはんだ材料。 A lead-free solder material composed of 100 parts by mass of a Zn-Al-Ge-Ni alloy and the remaining Sn of 0.05 to 2 parts by mass;
The Zn-Al-Ge-Ni alloy is composed of a Zn-Al alloy which is a first eutectic alloy and a Ge-Ni alloy which is a second eutectic alloy , and the contents of Zn, Al, Ge and Ni are respectively 94.3 wt%, 5 wt%, Ru der 0.5 wt% and 0.2 wt%, lead-free solder material.
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| JP5723523B2 (en) * | 2009-09-11 | 2015-05-27 | 株式会社日立製作所 | Connecting material, manufacturing method of connecting material, semiconductor device, manufacturing method of semiconductor device, power module |
| CN102473650B (en) * | 2009-09-09 | 2014-09-24 | 株式会社日立制作所 | Connecting material, semiconductor device and method for manufacturing semiconductor device |
| US9217192B2 (en) | 2010-03-01 | 2015-12-22 | Osaka University | Semiconductor device and bonding material for semiconductor device |
| JP6015571B2 (en) * | 2013-06-18 | 2016-10-26 | 住友金属鉱山株式会社 | Pb-free Zn-Al alloy fuse |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53124150A (en) * | 1977-04-05 | 1978-10-30 | Nec Corp | Alloy soldering material |
| JPS62173095A (en) * | 1986-01-24 | 1987-07-29 | Showa Alum Corp | Sheet material for soldering |
| JPH04258397A (en) * | 1991-02-05 | 1992-09-14 | Furukawa Alum Co Ltd | Brazing filler metal for low temperature brazing for aluminum member |
| JPH11288955A (en) * | 1998-04-02 | 1999-10-19 | Sumitomo Metal Mining Co Ltd | High temperature soldering zn alloy |
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- 2006-06-09 JP JP2006160824A patent/JP4703492B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53124150A (en) * | 1977-04-05 | 1978-10-30 | Nec Corp | Alloy soldering material |
| JPS62173095A (en) * | 1986-01-24 | 1987-07-29 | Showa Alum Corp | Sheet material for soldering |
| JPH04258397A (en) * | 1991-02-05 | 1992-09-14 | Furukawa Alum Co Ltd | Brazing filler metal for low temperature brazing for aluminum member |
| JPH11288955A (en) * | 1998-04-02 | 1999-10-19 | Sumitomo Metal Mining Co Ltd | High temperature soldering zn alloy |
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| JP2007326137A (en) | 2007-12-20 |
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