JP5549118B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a surface electrode having a solder joint layer and a method for manufacturing the same.

  In a semiconductor device as a power device, the semiconductor device may be joined to a heat radiating plate such as a metal plate by soldering or the like, and heat generated in the semiconductor device may be radiated through the heat radiating plate. For example, in Patent Document 1, both the rear surface side and the front surface side of the semiconductor device are joined to the heat sink via solder. As a result, heat can be radiated from the heat sinks bonded to both the front and back sides of the semiconductor device.

  In Patent Document 1, a surface electrode is formed on the surface side of a semiconductor device, and a solder material is coated on the surface electrode at the stage of a wafer and soldered to a heat sink. The surface electrode for soldering requires a solder joint layer such as an Ni layer. In this case, an Al layer or an Al—Si layer needs to be formed between the Ni layer and the semiconductor substrate. On the other hand, if it is a surface electrode for connecting to an external member by wire bonding, for example, an Al—Si layer, an Al layer, or a laminate of these is used. In Patent Document 1, an Al—Si layer for performing wire bonding and an electrode in which an Al layer is laminated are used as they are, and a Ti layer as a barrier layer, a Ni layer as a solder joint layer, and an oxidation of the Ni layer on the surface thereof. An Au layer as a prevention layer is laminated. Thereafter, solder coating is performed on the surface of the Au layer, and after dicing, the metal plate and the surface electrode are joined via solder.

JP 2006-13080 A

  In a semiconductor device having a solder joint layer on the surface electrode, the wafer warp and the cracks in the solder joint layer such as the Ni layer are more likely to occur as the diameter of the wafer increases and the thickness decreases. The occurrence of wafer warpage and solder joint layer cracks makes it difficult to carry out the work in the subsequent manufacturing process, which causes problems in the electrical characteristics of the manufactured semiconductor device.

  As a result of diligent research, the present inventors have ensured the flatness of the interface between the solder bonding layer and the Al-Si layer or Al layer in order to suppress warpage of the wafer and cracks in the solder bonding layer. I found it effective. As a result of studying Al-Si layers and Al layers suitable for ensuring the flatness of the interface, the flatness can be ensured, but the generation of silicon nodules ensures the ohmic contact between the semiconductor substrate and the surface electrode. I also found out that it might not be possible.

  The present application has been made in view of such a point, and the purpose thereof is to ensure ohmic contact between the semiconductor substrate and the surface electrode, and to suppress warpage of the wafer and cracks in the solder bonding layer. Is to achieve both.

Therefore, the present application relates to a semiconductor substrate, a first layer in contact with the surface of the semiconductor substrate, a second layer in contact with the surface of the first layer, and a third layer stacked at a position farther from the semiconductor substrate than the second layer. And a surface electrode including a fourth layer laminated at a position farther from the semiconductor substrate than the third layer, wherein the first layer is formed by sputtering at a substrate temperature of 250 ° C. or lower. The formed aluminum-silicon alloy (Al-Si) layer or aluminum-silicon-copper alloy (Al-Si-Cu) layer, and the second layer is aluminum formed by sputtering at a substrate temperature of 400 ° C or higher. Disclosed is a semiconductor device that is an (Al) layer or an aluminum-copper (Al-Cu) alloy layer, the third layer is a solder joint layer, and the fourth layer is a solder layer.

In the semiconductor device described above, since an Al—Si layer or an Al—Si—Cu layer is used as the first layer in contact with the semiconductor substrate, generation of aluminum spikes in a heat treatment process such as a solder reflow process can be suppressed. In addition, since the first layer is formed by performing the sputtering method at a substrate temperature of 250 ° C. or lower, generation of silicon nodules can be prevented and ohmic contact between the semiconductor substrate and the surface electrode can be ensured. Furthermore, since the second layer formed on the surface is formed at a substrate temperature of 400 ° C. or higher, the flatness of the surface of the second layer can be secured, and the occurrence of wafer warpage and cracks in the solder joint layer can be prevented. it can. Unlike the Al-Si layer and the Al-Si-Cu layer, the Al layer and Al-Cu layer used as the second layer form a film with good flatness even when sputtering is performed at a substrate temperature of 400 ° C or higher. be able to.

This gun provides a method of manufacturing the semiconductor device. This manufacturing method includes a first step of performing a sputtering method at a substrate temperature of 250 ° C. or less to form a first layer on the surface of a semiconductor substrate with an Al—Si layer or an Al—Si—Cu layer, and a first step Later, a sputtering process is performed at a substrate temperature of 400 ° C. or lower to form a second layer with an Al layer or an Al—Cu layer on the surface of the first layer, and after the second process, Includes a third step of forming a third layer which is a solder bonding layer on the surface side, and a fourth step of forming a fourth layer which is a solder layer on the surface side of the third layer after the third step. Mu

According to the manufacturing method of a semiconductor device provided by the present gun, while ensuring an ohmic contact between the semiconductor substrate and the surface electrode, it is possible to suppress the crack of wafer warpage or solder bonding layer.

A semiconductor module including the semiconductor device according to the first embodiment. FIG. 3 is a diagram schematically showing a cross section in the vicinity of a surface electrode of the semiconductor device of Example 1. 6A and 6B illustrate a method for manufacturing the semiconductor device according to the first embodiment. 6A and 6B illustrate a method for manufacturing the semiconductor device according to the first embodiment. 6A and 6B illustrate a method for manufacturing the semiconductor device according to the first embodiment. 6A and 6B illustrate a method for manufacturing the semiconductor device according to the first embodiment. 6A and 6B illustrate a method for manufacturing the semiconductor device according to the first embodiment. 6A and 6B illustrate a method for manufacturing the semiconductor device according to the first embodiment. 1 is a conceptual diagram of a sputtering apparatus used in the method for manufacturing a semiconductor device of Example 1. The top view of the surface electrode of the semiconductor device of a modification. The top view of the surface electrode of the semiconductor device of a modification. The top view of the surface electrode of the semiconductor device of a modification. The figure which shows the relationship between the substrate temperature at the time of the sputtering of an Al layer, and the amount of wafer curvature.

  Embodiments of the present invention will be described below with reference to the drawings. A semiconductor device 10 according to the present embodiment is installed inside a semiconductor module 1 as shown in FIG. The semiconductor module 1 is covered with a molding material 24, the metal plate 22 is exposed on the back surface side, and the metal plate 23 is exposed on the front surface side. Leads 221 are connected to the metal plate 22, and leads 231 are connected to the metal plate 23.

  The semiconductor device 10 includes a semiconductor substrate 11, a back electrode 12, and a front electrode 13. The semiconductor device 10 is fixed between the two metal plates 22 and 23 by soldering the front electrode 13 and the front metal plate 23 and soldering the back electrode 12 and the rear metal plate 22. . Since the two metal plates 22 and 23 exposed to the outside of the semiconductor module 1 are joined, the heat generated in the semiconductor device 10 is easily radiated from the metal plates 22 and 23.

  FIG. 2 is a diagram schematically showing a cross section near the surface electrode of the semiconductor device 10. In FIG. 2, the configuration of the semiconductor device 10 repeated in the horizontal direction in the drawing is omitted, and a part thereof is shown. As shown in FIG. 2, a vertical trench gate type IGBT that can be used as a power device is built in the semiconductor substrate 11. On the semiconductor substrate 11, a first conductivity type collector region 18, a second conductivity type drift region 19, and a first conductivity type body region 14 are stacked from the back surface side. Is formed with a second conductivity type emitter region 15. A trench gate 17 penetrating the body region 14 from the surface side of the semiconductor substrate 11 is provided. The trench gate 17 is in contact with the emitter region 15. The trench gate 17 includes a gate electrode covered with a gate insulating film, and the surface of the gate electrode is covered with an interlayer insulating film 16 formed on a part of the surface of the semiconductor substrate 11.

  An Al—Si layer 131 is formed in contact with the surfaces of the semiconductor substrate 11 and the interlayer insulating film 16. Further, an Al layer 132, a Ni layer 133, an alloy layer 135, and a solder layer 134 are formed on the surface. A polyimide layer 140 as a protective film is formed on part of the surfaces of the Al—Si layer 131 and the Al layer 132, and is in contact with the side surfaces of the Ni layer 133, the alloy layer 135, and the solder layer 134.

  The Al—Si layer 131 is an example of a first layer containing silicon (Si) and containing aluminum (Al) as a main component, and is in contact with the surface of the semiconductor substrate 11 (the side on which the emitter region 15 is formed). Yes. Since the 1st layer contains Si which is the main ingredient of semiconductor substrate 11, it can control that an aluminum spike is generated by heat treatment processes, such as a solder reflow process. As will be described later, the Al—Si layer 131 is formed by performing sputtering at a substrate temperature of 250 ° C. or lower. When an Al—Si layer is used as the first layer, the mass concentration of Si is preferably 0.1 wt% or more. The first layer is preferably formed to a thickness of about 3 to 4 μm.

  As the first layer, an Al—Si—Cu alloy layer formed by sputtering at a substrate temperature of 250 ° C. or lower may be used. In this case, the mass concentration of copper (Cu) is preferably 0.3 wt% or more.

  The Al layer 132 is an example of a second layer containing Al as a main component, and is in contact with the surface of the Al—Si layer 131. As will be described later, the Al layer 132 is formed by performing sputtering at a substrate temperature of 400 ° C. or higher. When an Al layer is used as the second layer, the impurity mass concentration is preferably 0.1 wt% or less. The second layer is preferably formed to a thickness of 1 μm or more.

  As the second layer, an Al—Cu layer formed by sputtering at a substrate temperature of 400 ° C. or higher may be used. In this case, it is preferable that the mass concentration of Cu is 0.3 wt% or more. Unlike the Al-Si layer and Al-Si-Cu layer used as the first layer, the Al layer and Al-Cu layer used as the second layer are flat even when the sputtering method is performed at a substrate temperature of 400 ° C or higher. A good film can be formed.

  The Ni layer 133 is an example of a third layer that is a solder joint layer, and is in contact with the surface of the Al layer 132 in this embodiment. As the third layer, a material capable of forming a eutectic with solder can be used, and in addition to Ni used in this embodiment, Cu or the like can be suitably used. The third layer is preferably formed to a thickness of about 5 to 10 μm.

  A barrier metal layer may be formed between the second layer and the third layer. As the barrier metal layer, titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW) or the like that does not impair the flatness of the surface of the second layer can be suitably used.

  In this embodiment, an alloy layer 135 and a solder layer 134 are formed on the surface of the Ni layer 133. The solder layer 134 is an example of a fourth layer, and tin (Sn) -based, silver (Ag) -based, and lead (Pb) -based solder can be preferably used. The alloy layer 135 is formed by forming a part of the Ni layer 133 (third layer which is a solder joint layer) and a part of the solder layer 134 to form an alloy.

  An antioxidant layer that prevents the solder joint layer from being oxidized may be formed in contact with the surface of the third layer. As the antioxidant layer, a material that can prevent surface oxidation of the third layer and ensure wettability with solder can be used, and gold (Au), silver (Ag), or the like can be preferably used. When the antioxidant layer is formed on the surface of the third layer, the component of the antioxidant layer is one of the components of the alloy layer 135.

  Next, the manufacturing method of the surface electrode which concerns on a present Example is demonstrated. As shown in FIG. 3, a silicon wafer 100 is prepared in which an IGBT is formed on a semiconductor substrate 11 and an interlayer insulating film 16 is formed on the surface thereof. A surface electrode is manufactured by forming a first layer, a second layer, a third layer, and a fourth layer on the front surface side of the wafer 100.

(First step)
First, an Al—Si layer 131 as a first layer is formed on the surface of the wafer 100 by sputtering. FIG. 9 is a diagram conceptually showing a sputtering apparatus 36 for forming the Al—Si layer 131 and the Al layer 132 according to this embodiment. The sputtering apparatus 36 includes a backing plate 361, a target 362, and a stage 343 in the chamber 34. The sputtering apparatus 36 is configured to be able to apply a high voltage between the target 362 and the wafer placed on the stage 343. The target 362 and the stage 343 are opposed to each other in the chamber 34 and are spaced apart. The stage 343 is provided with temperature detection means, and can detect the temperature (substrate temperature) of the wafer 100 placed on the stage 343.

  The Al—Si layer 131 can be formed on the surface of the wafer 100 by placing the wafer 100 on the stage 343, using Al—Si alloy as the target 362, and performing sputtering. The wafer 100 is placed on the stage 343 such that the surface side on which the interlayer insulating film 16 is formed is the target 362 side. The inside of the chamber 34 is depressurized and controlled so that the substrate temperature becomes a predetermined temperature of 250 ° C. or lower based on the detection value of the temperature detection means installed on the stage 343. The substrate temperature is preferably set in the range of room temperature (25 ° C.) to 250 ° C. After the decompression is completed, the introduction of Ar gas is started, and a high voltage is applied between the target 362 and the wafer 100 placed on the stage 343. Thereby, as shown in FIG. 4, an Al—Si layer 131 can be formed on the surface of the wafer 100. In this embodiment, since the Al—Si layer 131 is formed at a substrate temperature of 250 ° C. or lower, generation of silicon nodules can be prevented.

(Second step)
Next, an Al layer 132 as a second layer is formed similarly by sputtering. The material used as the target 362 is made of high-purity Al, and sputtering is performed by controlling the substrate temperature to be a predetermined temperature of 400 ° C. or higher based on the detection value of the temperature detection means installed on the stage 343. The substrate temperature is preferably set in the range of 400 ° C. or higher and 500 ° C. or lower. Thereby, as shown in FIG. 5, the Al layer 132 can be formed on the surface of the Al—Si layer 131. Since the Al layer 132 is formed at a substrate temperature of 400 ° C. or higher, the flatness of the surface of the Al layer 132 can be ensured.

  When a barrier metal layer is formed between the second layer and the third layer, the barrier metal layer is formed on the surface of the wafer 100 in the state shown in FIG. For example, when a Ti layer is formed as the barrier metal layer, it can be formed by a method of performing sputtering using a target made of Ti.

  Next, the wafer 100 is taken out and a polyimide layer 140 as a protective layer is formed as shown in FIG. The polyimide layer 140 can be formed, for example, by applying polyamic acid to the wafer 100 and then polymerizing by annealing treatment.

(Third step)
Further, as shown in FIG. 7, a Ni layer 133 is formed as the third layer by electroless plating. The electroless plating of the Ni layer 133 can be performed by, for example, nickel-phosphorus alloy (Ni-P) plating using sodium hypophosphite as a reducing agent.

  When an antioxidant layer is formed between the third layer and the fourth layer, the antioxidant layer is formed on the surface of the wafer 100 in the state shown in FIG. For example, when an Au layer is formed as the antioxidant layer, it can be formed by a method such as electroless plating.

(4th process)
Next, as shown in FIG. 8, a solder layer 134 is applied to the surface as a fourth layer. Thereafter, a solder reflow process is performed. By the heat treatment performed in the solder reflow process, an alloy layer 135 is formed between the Ni layer 133 and the solder layer 134, and the semiconductor device 10 shown in FIG. 2 can be manufactured.

  FIG. 13 is a diagram showing a result of examining the amount of wafer warpage when the substrate temperature during sputtering is changed in the second step of forming the Al layer in the above manufacturing process. The vertical axis indicates the amount of wafer warpage in arbitrary units (Arbitrary Unit: arb.unit), and the amount of wafer warpage increases in the direction of the arrow on the vertical axis. The horizontal axis represents the substrate temperature during sputtering. The experimental points shown in FIG. 13 show the results of sputtering at substrate temperatures of 360 ° C., 380 ° C., 400 ° C., 420 ° C., and 450 ° C. in the step of forming the Al layer. The solid line in the graph of FIG. 13 is a line connecting the experimental points, and the broken line extending to the low temperature side from the experimental point indicates the result of simulation based on the experimental point. From FIG. 13, it can be seen that the wafer warpage is suppressed as the substrate temperature during the sputtering of the Al layer increases.

  Further, in the wafer sputtered at the substrate temperatures of 360 ° C. and 380 ° C. shown in FIG. 13, a conveyance abnormality occurred in the wafer conveyance process, and the generation of cracks in the wafer was observed. On the other hand, in the wafers sputtered at the substrate temperatures of 400 ° C., 420 ° C., and 450 ° C. shown in FIG. 13, no conveyance abnormality occurred in the wafer conveyance process, and no occurrence of cracks in the wafer was observed. From the above results, if the Al layer is formed by performing sputtering at a substrate temperature of 400 ° C. or higher as in the manufacturing method of the present embodiment, the warpage of the wafer is suppressed and the wafer conveyance abnormality does not occur, and the wafer It was found that no cracks were observed.

  As described above, in the manufacturing method according to this example, since the Al—Si layer 131 is formed by performing the sputtering method at a substrate temperature of 250 ° C. or less, generation of silicon nodules can be prevented, and the semiconductor substrate And ohmic contact with the surface electrode can be ensured. Furthermore, since the Al layer 132 is formed on the surface by sputtering at a substrate temperature of 400 ° C. or higher, the flatness of the surface of the Al layer 132 can be ensured. Thereby, the flatness of the surface of the Ni layer 133 formed on the surface of the Al layer 132 can be secured, and the warpage of the wafer and the occurrence of cracks in the Ni layer 133 can be prevented.

  In this embodiment, the surface electrode according to this embodiment is formed on the entire surface of the semiconductor device. However, the surface electrode may be formed on a part of the semiconductor device. In the case where the surface electrode according to the present embodiment is formed in a part of the semiconductor device, it is effective to form the surface electrode in a portion having a relatively large calorific value. For example, as shown in FIG. 10, in the semiconductor device, the surface electrode 13 according to the present embodiment is used only for the surface electrode of the main cell 3 where a large current flows and easily generates heat, and the surface electrode of the sense cell 5 that generates little heat is used. May use a conventional surface electrode 93. In addition, when the surface electrode according to the present embodiment is used only for a part of the surface electrode of the main cell 3, as shown in FIG. 11 and FIG. It is preferable to form the surface electrode 13 according to the embodiment.

  As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

  The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

DESCRIPTION OF SYMBOLS 1 Semiconductor module 3 Main cell 5 Sense cell 10 Semiconductor device 11 Semiconductor substrate 12 Back surface electrode 13 Front surface electrode 14 Body region 15 Emitter region 16 Interlayer insulation film 17 Trench gate 18 Collector region 19 Drift region 22 Back surface side metal plate 23 Surface side metal plate 24 Mold material 34 Chamber 36 Sputtering apparatus 100 Wafer 131 Al-Si layer 132 Al layer 133 Ni layer 134 Solder layer 135 Alloy layer 140 Polyimide layers 221 and 231 Lead 343 Stage 361 Backing plate 362 Target

Claims (1)

A method for manufacturing a semiconductor device comprising a semiconductor substrate and a surface electrode laminated on the surface of the semiconductor substrate,
Performing a sputtering method at a substrate temperature of 250 ° C. or lower to form a first layer with an Al—Si layer or an Al—Si—Cu layer on the surface of the semiconductor substrate;
After the first step, a second step of performing a sputtering method at a substrate temperature of 400 ° C. or higher to form a second layer with an Al layer or an Al—Cu layer on the surface of the first layer;
After the second step, a third step of forming a third layer which is a solder joint layer on the surface side of the second layer;
And a fourth step of forming a fourth layer, which is a solder layer, on the surface side of the third layer after the third step.

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