TWI525788B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TWI525788B
TWI525788B TW102138309A TW102138309A TWI525788B TW I525788 B TWI525788 B TW I525788B TW 102138309 A TW102138309 A TW 102138309A TW 102138309 A TW102138309 A TW 102138309A TW I525788 B TWI525788 B TW I525788B
Authority
TW
Taiwan
Prior art keywords
wiring
semiconductor device
type transistor
semiconductor wafer
lower layer
Prior art date
Application number
TW102138309A
Other languages
English (en)
Other versions
TW201503316A (zh
Inventor
小柳勝
末松靖弘
Original Assignee
東芝股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 東芝股份有限公司 filed Critical 東芝股份有限公司
Publication of TW201503316A publication Critical patent/TW201503316A/zh
Application granted granted Critical
Publication of TWI525788B publication Critical patent/TWI525788B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

半導體裝置 [相關申請案]
本申請案享有以美國專利臨時申請案61-843184號(申請日：2013年7月5日)為基礎申請案之優先權。本申請案係藉由參照該基礎申請案而包含基礎申請案之全部內容。
本實施形態一般而言係關於一種半導體裝置。
於半導體裝置中，伴隨介面之高速化，有將ODT(On Die Termination：片內終結器)電路用於IO(In/Out，輸入/輸出)終端之情形。
本發明之實施形態係提供一種應用ODT電路之較佳之半導體裝置。
根據實施形態，設置有形成於半導體晶片上之電晶體、下層配線、及上層配線。下層配線連接於上述電晶體之擴散層，且被引出至上述擴散層之外。上層配線自形成於上述半導體晶片上之焊墊電極被引出，且連接於上述下層配線，且電阻率小於上述下層配線。
1‧‧‧NAND記憶體
2‧‧‧傳輸線路
3‧‧‧控制器
4‧‧‧ODT電路
5‧‧‧ODT電路
11‧‧‧ODT電路
11A‧‧‧ODT電路
11B‧‧‧ODT電路
12‧‧‧輸出緩衝器
12A‧‧‧輸出緩衝器
12B‧‧‧輸出緩衝器
13‧‧‧輸入電路
13A‧‧‧輸入電路
13B‧‧‧輸入電路
14‧‧‧內部電路
B1‧‧‧半導體晶片
B11‧‧‧半導體晶片
B21‧‧‧半導體晶片
BD‧‧‧電路基板
BDA‧‧‧電路基板
BDB‧‧‧電路基板
BDC‧‧‧電路基板
BP‧‧‧IO端子
BPA‧‧‧IO端子
BPB‧‧‧IO端子
BPC‧‧‧IO端子
D1‧‧‧焊墊電極
D1A‧‧‧焊墊電極
D1B‧‧‧焊墊電極
D11‧‧‧焊墊電極
D21‧‧‧焊墊電極
F1‧‧‧擴散層
F2‧‧‧擴散層
F11‧‧‧擴散層
F12‧‧‧擴散層
F21A‧‧‧擴散層
F21B‧‧‧擴散層
F21C‧‧‧擴散層
F22A‧‧‧擴散層
F22B‧‧‧擴散層
F22C‧‧‧擴散層
F23‧‧‧基底擴散層
G1‧‧‧閘極電極
G11‧‧‧閘極電極
G21A‧‧‧閘極電極
G21B‧‧‧閘極電極
G21C‧‧‧閘極電極
GND‧‧‧接地電位
H1‧‧‧下層配線
H1A‧‧‧下層配線
H2‧‧‧下層配線
H3‧‧‧上層配線
H11‧‧‧下層配線
H12‧‧‧下層配線
H13‧‧‧上層配線
H14‧‧‧襯裏配線
H15‧‧‧襯裏配線
H21A‧‧‧下層配線
H21B‧‧‧下層配線
H21C‧‧‧下層配線
H22A‧‧‧下層配線
H22B‧‧‧下層配線
H22C‧‧‧下層配線
H23A‧‧‧上層配線
H23B‧‧‧上層配線
H23C‧‧‧上層配線
H24A‧‧‧襯裏配線
H24B‧‧‧襯裏配線
H24C‧‧‧襯裏配線
H25A‧‧‧上層配線
H25B‧‧‧上層配線
H25C‧‧‧上層配線
H26‧‧‧基底配線
N1‧‧‧N型電晶體
N1A‧‧‧N型電晶體
N1B‧‧‧N型電晶體
N2‧‧‧N型電晶體
N2A‧‧‧N型電晶體
N2B‧‧‧N型電晶體
P1‧‧‧P型電晶體
P1A‧‧‧P型電晶體
P1B‧‧‧P型電晶體
P2‧‧‧P型電晶體
P2A‧‧‧P型電晶體
P2B‧‧‧P型電晶體
P11‧‧‧P型電晶體
P21A‧‧‧P型電晶體
P21B‧‧‧P型電晶體
P21C‧‧‧P型電晶體
PA0~PA7‧‧‧半導體晶片
PB0~PB7‧‧‧半導體晶片
PC0~PC7‧‧‧半導體晶片
PE0~PE7‧‧‧半導體晶片
PK‧‧‧封裝
PKA‧‧‧封裝
PKB‧‧‧封裝
PKC‧‧‧封裝
R0‧‧‧保護電阻
R0A‧‧‧保護電阻
R0B‧‧‧保護電阻
R1‧‧‧電阻
R1A‧‧‧電阻
R1B‧‧‧電阻
R2‧‧‧電阻
R2A‧‧‧電阻
R2B‧‧‧電阻
R3‧‧‧電阻
R4‧‧‧電阻
R11‧‧‧電阻
R21A‧‧‧電阻
R21B‧‧‧電阻
R21C‧‧‧電阻
SA‧‧‧配線
SB‧‧‧配線
T1‧‧‧接點
T2‧‧‧接點
T3‧‧‧接點
T11‧‧‧接點
T13‧‧‧接點
T14‧‧‧接點
T15‧‧‧接點
T23A‧‧‧接點
T23B‧‧‧接點
T23C‧‧‧接點
T24A‧‧‧接點
T24B‧‧‧接點
T24C‧‧‧接點
T25A‧‧‧接點
T25B‧‧‧接點
T25C‧‧‧接點
VCC‧‧‧電源電位
WL‧‧‧接合線
WLA‧‧‧接合線
WLB‧‧‧接合線
WLC‧‧‧接合線
Z21‧‧‧STI
圖1係顯示第1實施形態之半導體裝置之系統構成之方塊圖。
圖2(a)、圖2(b)及圖2(c)係顯示使用於圖1之NAND記憶體之半導體晶片之概略構成例之方塊圖。
圖3(a)係顯示圖2(a)及圖2(b)之P型電晶體P1及電阻R1、及圖2(b) 及圖2(c)之P型電晶體P2及電阻R3之構成例之俯視圖，圖3(b)係沿著圖3(a)之配線H1切斷而得之剖面圖。
圖4係顯示應用於第2實施形態之半導體裝置之ODT電路之P型電晶體及電阻之構成例之俯視圖。
圖5(a)係顯示應用於第3實施形態之半導體裝置之ODT電路之P型電晶體及電阻之構成例之俯視圖，圖5(b)係沿著圖5(a)之配線H11切斷而得之剖面圖。
圖6(a)係顯示應用於第4實施形態之半導體裝置之ODT電路之P型電晶體及電阻之構成例之俯視圖，圖6(b)係沿著圖6(a)之配線H21A切斷而得之剖面圖。
圖7係顯示應用於第5實施形態之半導體裝置之ODT電路之P型電晶體及電阻之構成例之俯視圖。
圖8(a)係顯示第6實施形態之半導體裝置之系統構成之剖面圖，圖8(b)係顯示圖8(a)之半導體晶片P0之ODT電路11A之連接狀態之方塊圖，圖8(c)係顯示圖8(a)之各半導體晶片P1~P7之ODT電路11B之連接狀態之方塊圖。
圖9係顯示第7實施形態之半導體裝置之系統構成之剖面圖。
圖10係顯示第8實施形態之半導體裝置之系統構成之剖面圖。
以下參照隨附圖式，詳細地說明實施形態之半導體裝置。再者，本發明並不受該等實施形態限定。
(第1實施形態)
圖1係顯示第1實施形態之半導體裝置之系統構成之方塊圖。
於圖1中，NAND(Not AND，反及)記憶體1經由傳輸線路2而連接於控制器3。再者，控制器3可進行NAND記憶體1之讀寫控制、區塊選擇、錯誤校正等。NAND記憶體1以ODT電路4作為IO終端。控制器 3以ODT電路5作為IO終端。此處，ODT電路4可於NAND記憶體1之信號輸入時於其與傳輸線路2之間採取阻抗匹配，或者限制NAND記憶體1之輸入信號之上下限。ODT電路5可於控制器3之信號輸入時於其與傳輸線路2之間採取阻抗匹配，或者限制控制器3之輸入信號之上下限。
圖2(a)、圖2(b)及圖2(c)係顯示使用於圖1之NAND記憶體之半導體晶片之概略構成例之方塊圖。
於圖2(a)中，於半導體晶片B1中設置焊墊電極D1，焊墊電極D1連接ODT電路11、輸出緩衝器12、保護電阻R0及輸入電路13，且經由上述輸出緩衝器12、輸入電路13而連接於內部電路14。於內部電路14中，可設置NAND記憶體1之記憶胞陣列、列解碼器及行解碼器等。
於ODT電路11中，設置有P型電晶體P1、N型電晶體N1及電阻R1、R2。P型電晶體P1與電阻R1相互串聯連接，N型電晶體N1與電阻R2相互串聯連接。電阻R1、R2之連接點連接於焊墊電極D1。P型電晶體P1之源極連接於電源電位VCC，N型電晶體N1之源極連接於接地電位GND。
於輸出緩衝器12中，設置有P型電晶體P2及N型電晶體N2。P型電晶體P2及N型電晶體N2之連接點連接於焊墊電極D1。P型電晶體P2之源極連接於電源電位VCC，N型電晶體N2之源極連接於接地電位GND。ODT電路亦可作為輸出緩衝器之一部分而使用。
而且，於對焊墊電極D1輸入信號之情形時，P型電晶體P2及N型電晶體N2被斷開。又，藉由接通P型電晶體P1及N型電晶體N1，而將焊墊電極D1設定為電源電位VCC與接地電位GND之間之中間電位。此時，藉由使電阻R1、R2之合成電阻值與傳輸線路2之電阻值一致，可於其與傳輸線路2之間採取阻抗匹配。因此，可防止經由傳輸線路2而輸入至焊墊電極D1之信號被反射，可使信號之傳輸效率化。又， 可由電阻R1、R2限制經由傳輸線路2輸入至焊墊電極D1之信號之上下限，而可謀求信號之小振幅化。
圖2(b)係輸出緩衝器12亦與ODT電路同樣地以串聯電晶體與電阻元件而構成之情形。藉由將電阻插入至輸出緩衝器，具有使輸出時之驅動電阻線性化而更容易採取與基板配線之阻抗匹配之優點。於輸出緩衝器12中設置有P型電晶體P2、N型電晶體N2及電阻R3、R4。P型電晶體P2與電阻R3相互串聯連接，N型電晶體N2與電阻R4相互串聯連接。電阻R3、R4之連接點連接於焊墊電極D1。P型電晶體P2之源極連接於電源電位VCC，N型電晶體N2之源極連接於接地電位GND。
圖2(c)係僅為輸出緩衝器12之情形。與圖2(b)相同，藉由將電阻插入至輸出緩衝器，具有使輸出時之驅動電阻線性化而更容易採取與基板配線之阻抗匹配之優點。於輸出緩衝器12中設置有P型電晶體P2、N型電晶體N2及電阻R3、R4。P型電晶體P2與電阻R3相互串聯連接，N型電晶體N2與電阻R4相互串聯連接。電阻R3、R4之連接點連接於焊墊電極D1。P型電晶體P2之源極連接於電源電位VCC，N型電晶體N2之源極連接於接地電位GND。亦可使輸出緩衝器之一部分作為ODT發揮功能。
圖3(a)係顯示圖2(a)及圖2(b)之P型電晶體P1及電阻R1、以及圖2(b)及圖2(c)之P型電晶體P2及電阻R3之構成例之俯視圖，圖3(b)係沿著圖3(a)之配線H1切斷而得之剖面圖。由於輸出緩衝器之構成與ODT電路及ODT同樣地係將電晶體與電阻元件串聯連接，故以後以ODT電路為代表進行記載，但其中亦包含與ODT同樣地將電晶體與電阻元件串聯連接之輸出緩衝器作為對象。
於圖3(a)及圖3(b)中，於半導體晶片B1上設置有閘極電極G1。再者，半導體晶片B1之材料可使用單晶矽，閘極電極G1之材料可使用多晶矽。於閘極電極G1下之通道區域之兩側設置有擴散層F1、F2。 再者，閘極電極G1及擴散層F1、F2可用於圖2之P型電晶體P1中。此時，擴散層F1可構成P型電晶體P1之汲極，擴散層F2可構成P型電晶體P1之源極。
於擴散層F1上形成下層配線H1，下層配線H1被引出至擴散層F1之外。下層配線H1經由接點T1而連接於擴散層F1。再者，為了降低下層配線H1之配線電容，較佳為不使下層配線H1與閘極電極G1重疊。於擴散層F2上形成下層配線H2，下層配線H2經由接點T2而連接於擴散層F2。
又，於半導體晶片B1上設置焊墊電極D1，上層配線H3自焊墊電極D1被引出。上層配線H3經由接點T3而連接於下層配線H1。下層配線H1可由電阻率大於上層配線H3之材料構成。此時，下層配線H1可由熔點高於上層配線H3之材料構成，下層配線H1亦可由電遷移耐性高於上層配線H3之材料構成。例如，下層配線H1可使用W，上層配線H3可使用Al。圖中除了下層配線H1以外，僅顯示上層配線H3，但亦可進而存在複數個配線層作為H1之上層配線。例如亦可構成如於下層配線H1與上層配線H3之間存在Cu配線之情形。於以後之例中亦有僅顯示H3作為上層配線之情形，但關於該等亦為相同。
此處，引出至擴散層F1之外之下層配線H1可用作圖2之電阻R1。藉此，無須分別形成用作圖2之電阻R1之電阻元件，而可降低用於連接電阻元件之配線電容，故可提高信號傳輸速度。又，可降低電阻R1之值之不均，且可降低電遷移，而可提高ODT電路11之可靠性。再者，關於電阻R2亦可與電阻R1同樣地構成。
(第2實施形態)
圖4係顯示應用於第2實施形態之半導體裝置之ODT電路之P型電晶體及電阻之構成例之俯視圖。
於圖4中，於該ODT電路中設置有下層配線H1A以代替圖1之下層 配線H1。下層配線H1A可採用於擴散層F1之外折回之構造。藉此，不變更下層配線H1A之材料，可增大下層配線H1A之電阻值，且可增大電阻R1之值。
(第3實施形態)
圖5(a)係顯示應用於第3實施形態之半導體裝置之ODT電路之P型電晶體及電阻之構成例之俯視圖，圖5(b)係沿著圖5(a)之配線H11切斷而得之剖面圖。
於圖5(a)及圖5(b)中，於半導體晶片B11上並列設置有複數個閘極電極G11。再者，半導體晶片B11之材料可使用單晶矽，閘極電極G11之材料可使用多晶矽。於閘極電極G11下之通道區域之兩側設置擴散層F11、F12。再者，閘極電極G11及擴散層F11、F12可用於ODT電路之P型電晶體P11中。此時，擴散層F11可構成P型電晶體P11之汲極，擴散層F12可構成P型電晶體P11之源極。
於擴散層F11上形成下層配線H11，下層配線H11被引出至擴散層F11之外。下層配線H11經由接點T11而連接於擴散層F11。再者，為了降低下層配線H11之配線電容，較佳為不使下層配線H11與閘極電極G11重疊。於擴散層F12上形成下層配線H12，下層配線H12經由接點而連接於擴散層F12。於下層配線H12上形成上層配線H15，上層配線H15經由接點T15而連接於下層配線H12。
又，於半導體晶片B11上設置焊墊電極D11，上層配線H13自焊墊電極D11被引出。上層配線H13經由接點T13而連接於下層配線H11。下層配線H11可由電阻率大於上層配線H13之材料構成。此時，下層配線H11亦可由熔點高於上層配線H13之材料構成，下層配線H11亦可由電遷移耐性高於上層配線H13之材料構成。例如，下層配線H11可使用W，上層配線H13可使用Al。此處，被引出至擴散層F11之外之下層配線H11可用作串聯連接於ODT電路之P型電晶體P11之電阻R11。
又，於擴散層F11上設置內襯下層配線H11之襯裏配線H14，襯裏配線H14經由接點T14而連接於下層配線H11。再者，襯裏配線H14可由電阻率小於下層配線H11之材料構成。例如，襯裏配線H14可使用Al。進而，於電阻R11與擴散層F11之間之區間，設置內襯下層配線H11之襯裏配線H15，襯裏配線H15經由接點T15而連接於下層配線H11。
此處，藉由設置內襯下層配線H11之襯裏配線H14、H15，可將下層配線H11分成作為電阻R11起作用之部分與不作為電阻R11起作用之部分，而可提高電阻R11之值之精度。
(第4實施形態)
圖6(a)係顯示應用於第4實施形態之半導體裝置之ODT電路之P型電晶體及電阻之構成例之俯視圖，圖6(b)係沿著圖6(a)之配線H21A切斷後之剖面圖。
於圖6(a)及圖6(b)中，於半導體晶片B21上設置有複數個P型電晶體P21A、P21B、P21C。於P型電晶體P21A上並列設置有複數個閘極電極G21A，於P型電晶體P21B上並列設置有複數個閘極電極G21B，於P型電晶體P21C上並列設置有複數個閘極電極G21C。再者，半導體晶片B21之材料可使用單晶矽，閘極電極G21A、G21B、G21C之材料可使用多晶矽。於閘極電極G21A下之通道區域之兩側設置擴散層F21A、F22A，於閘極電極G21B下之通道區域之兩側設置擴散層F21B、F22B，於閘極電極G21C下之通道區域之兩側設置擴散層F21C、F22C。此時，擴散層F21A可構成P型電晶體P21A之汲極，擴散層F22A可構成P型電晶體P21A之源極。擴散層F21B可構成P型電晶體P21B之汲極，擴散層F22B可構成P型電晶體P21B之源極。擴散層F21C可構成P型電晶體P21C之汲極，擴散層F22C可構成P型電晶體P21C之源極。
於擴散層F21A上形成下層配線H21A，下層配線H21A被引出至擴散層F21A之外。下層配線H21A經由接點而連接於擴散層F21A。於擴散層F21B上形成下層配線H21B，下層配線H21B被引出至擴散層F21B之外。下層配線H21B經由接點而連接於擴散層F21B。於擴散層F21C上形成下層配線H21C，下層配線H21C被引出至擴散層F21C之外。下層配線H21C經由接點而連接於擴散層F21C。再者，為了降低下層配線H21A、H21B、H21C之配線電容，較佳為不使下層配線H21A、H21B、H21C與閘極電極G21A、G21B、G21C重疊。
於擴散層F22A、F22B、F22C上分別形成下層配線H22A、H22B、H22C，下層配線H22A、H22B、H22C經由接點而分別連接於擴散層F22A、F22B、F22C。於下層配線H22A、H22B、H22C上分別形成上層配線H25A、H25B、H25C，上層配線H25A、H25B、H25C分別經由接點T25A、T25B、T25C而連接於下層配線H22A、H22B、H22C。
又，於半導體晶片B21上設置焊墊電極D21，上層配線H23A、H23B、H23C自焊墊電極D21被引出。上層配線H23A、H23B、H23C分別經由接點T23A、T23B、T23C而連接於下層配線H21A、H21B、H21C。
下層配線H21A、H21B、H21C可由電阻率大於上層配線H23A、H23B、H23C之材料構成。此時，下層配線H21A、H21B、H21C可由熔點高於上層配線H23A、H23B、H23C之材料構成，下層配線H21A、H21B、H21C亦可由電遷移耐性高於上層配線H23A、H23B、H23C之材料構成。例如，下層配線H21A、H21B、H21C可使用W，上層配線H23A、H23B、H23C可使用Al。此處，被引出至擴散層F21A之外之下層配線H21A可用作串聯連接於P型電晶體P21A之電阻R21A。被引出至擴散層F21B之外之下層配線H21B可用作串聯連接於 P型電晶體P21B之電阻R21B。被引出至擴散層F21C之外之下層配線H21C可用作串聯連接於P型電晶體P21C之電阻R21C。
又，於各擴散層F21A、F21B、F21C上設置分別內襯下層配線H21A、H21B、H21C之襯裏配線H24A、H24B、H24C，襯裏配線H24A、H24B、H24C分別經由接點T24A、T24B、T24C而連接於下層配線H21A、H21B、H21C。再者，襯裏配線H24A、H24B、H24C可由電阻率小於下層配線H21A、H21B、H21C之材料構成。例如，襯裏配線H24A、H24B、H24C可使用Al。再者，於電阻R21A、R21B、R21C與擴散層F21A、F21B、F21C之間之各區間，設置分別內襯下層配線H21A、H21B、H21C之襯裏配線H25A、H25B、H25C，襯裏配線H25A、H25B、H25C分別經由接點T25A、T25B、T25C而連接於下層配線H21A、H21B、H21C。
又，於P型電晶體P21A、P21B、P21C與焊墊電極D21之間之區域，於半導體晶片B21上形成以STI(Shallow Trench Isolation：淺溝槽隔離)Z21所分離之短條狀之基底擴散層F23，且形成有短條狀之基底配線H26。再者，基底配線H26可由P型電晶體P21A、P21B、P21C之閘極電極材構成。基底擴散層F23及基底配線H26可於下層配線H21A、H21B、H21C下，以與下層配線H21A、H21B、H21C正交之方式交替並排配置。此時，基底擴散層F23及基底配線H26可由複數個下層配線H21A、H21B、H21C所共用。又，基底擴散層F23及基底配線H26可於下層配線H21A、H21B、H21C之折曲部分構成為L字狀。又，基底擴散層F23及基底配線H26之電位可設定為浮動狀態。再者，基底擴散層F23及基底配線H26可交替並排配置，亦可以相互重疊之方式配置。
此處，藉由設置基底擴散層F23及基底配線H26作為電阻R21A、R21B、R21C之基底層，可提高電阻R21A、R21B、R21C之基底層之 圖案之粗密之均一性。因此，以鑲嵌形成下層配線H21A、H21B、H21C時，由於可抑制下層配線H21A、H21B、H21C之嵌入部之碟陷(dishing)，而可使下層配線H21A、H21B、H21C之膜厚均一化，故可降低電阻R21A、R21B、R21C之值之不均一。又，藉由將基底擴散層F23及基底配線H26之電位設定為浮動狀態，可降低電阻R21A、R21B、R21C與基底層之間之寄生電容，而可提高信號傳輸速度。
再者，於上述實施形態中，雖針對設置有基底擴散層F23及基底配線H26作為電阻R21A、R21B、R21C之基底層之構成進行了說明，但亦可自電阻R21A、R21B、R21C下去除所有基底擴散層F23及基底配線H26，並設置包含絕緣體之β圖案作為電阻R21A、R21B、R21C之基底層。
(第5實施形態)
圖7係顯示應用於第5實施形態之半導體裝置之ODT電路之P型電晶體及電阻之構成例之俯視圖。
於圖7中，該ODT電路去除圖6(a)之基底擴散層F23，設置有基底配線H26作為電阻R21A、R21B、R21C之基底層。此處，藉由去除圖6(a)之基底擴散層F23，可去除電阻R21A、R21B、R21C與基底擴散層F23之間之寄生電容，而可提高信號傳輸速度。
(第6實施形態)
圖8(a)係顯示第6實施形態之半導體裝置之系統構成之剖面圖，圖8(b)係顯示圖8(a)之半導體晶片PE0之ODT電路11A之連接狀態之方塊圖，圖8(c)係顯示圖8(a)之各半導體晶片PE1~PE7之ODT電路11B之連接狀態之方塊圖。
於圖8(a)中，於封裝PK中設置電路基板BD，於電路基板BD上安裝有半導體晶片PE0~PE7。於電路基板BD之背面設置有IO端子BP。此處，於半導體晶片PE0中設置有焊墊電極D1A、ODT電路11A、輸 出緩衝器12A、保護電阻R0A及輸入電路13A。於ODT電路11A中設置有P型電晶體P1A、N型電晶體N1A及電阻R1A、R2A。於輸出緩衝器12A中設置有P型電晶體P2A及N型電晶體N2A。此處，焊墊電極D1A經由自焊墊電極D1A引出之配線SA而連接於ODT電路11A。於各半導體晶片PE1~PE7中設置有焊墊電極D1B、ODT電路11B、輸出緩衝器12B、保護電阻R0B及輸入電路13B。於ODT電路11B中設置有P型電晶體P1B、N型電晶體N1B及電阻R1B、R2B。於輸出緩衝器12B中設置有P型電晶體P2B及N型電晶體N2B。此處，焊墊電極D1B係藉由切斷自焊墊電極D1B引出之配線SB而與ODT電路11B斷接。再者，電阻R1A、R2A、R1B、R2B亦可與圖3(a)、圖4、圖5(a)、圖6(a)或圖7之構成相同。
半導體晶片PE0~PE7以露出焊墊電極D1A、D1B之方式錯開積層。而且，焊墊電極D1A、D1B藉由經由接合線WL連接於IO端子BP，而連接於同一通道。IO端子BP經由傳輸線路2而連接於控制器3。
而且，於對半導體晶片PE0~PE7之任一者之焊墊電極D1A、D1B輸入信號之情形時，P型電晶體P2A、P2B及N型電晶體N2A、N2B被斷開。又，藉由接通P型電晶體P1A及N型電晶體N1A，而將焊墊電極D1A、D1B設定為電源電位VCC與接地電位GND之間之中間電位。此時，藉由使電阻R1A、R2A之合成電阻值與傳輸線路2之電阻值一致，可於其與傳輸線路2之間採取阻抗匹配。因此，可防止經由傳輸線路2輸入至焊墊電極D1A、D1B之信號被反射，可使信號之傳輸效率化。又，可利用電阻R1A、R2A限制經由傳輸線路2輸入至焊墊電極D1A、D1B之信號之上下限，而可謀求信號之小振幅化。
又，藉由焊墊電極D1A、D1B共用ODT電路11A，可消除施加至焊墊電極D1B之ODT電路11B之電容，而可降低IO端子BP之引腳電 容。
例如，具有ODT元件之半導體晶片之IO焊墊與無ODT端子之半導體晶片之IO焊墊相比，電容(CL)重約30%。由於若通道內之IO焊墊之總電容較重，則無法高速驅動IO焊墊，故IO資料之傳送效率下降。例如，於1封裝內存在8個共用IO焊墊之半導體晶片之情形時，若搭載附帶有相同ODT元件之半導體晶片，則封裝之1個IO端子之引腳電容CIO1如下式所述：CIO1=封裝之配線電容+附帶ODT之晶片之電容(1.3×CL)×8
由於封裝之配線電容接近具有ODT之晶片電容，故：CIO1=1.3×CL+1.3×CL×8=1.3×CL×9=11.7×CL。
相對於此，若8個晶片中僅1晶片附帶ODT元件，其他晶片無ODT元件，則封裝之1個IO端子之引腳電容CIO2如下式所述：CIO2=封裝之配線電容+無ODT之晶片之電容(CL)×7+附帶ODT之晶片之電容(1.3×CL)=1.3×CL×2+CL×7=9.6×CL
因此，CIO1=11.7×CL=11.7/9.6×CIO2=1.22×CIO2，減少約22%之引腳電容。
再者，於圖8之例中，雖已針對於各半導體晶片PE1~PE7上設置ODT電路11B，且藉由切斷自焊墊電極D 1B引出之配線SB而將焊墊電極D1B與ODT電路11B斷接之構成進行說明，但亦可不於各半導體晶片PE1~PE7上設置ODT電路11B。
(第7實施形態)
圖9係顯示第7實施形態之半導體裝置之系統構成之剖面圖。
於圖9中，於封裝PKA中設置電路基板BDA，於電路基板BDA上安裝有半導體晶片PA0~PA7。於電路基板BDA之背面設置有IO端子BPA。各半導體晶片PA0~PA7之焊墊電極藉由經由接合線WLA連接於IO端子BPA，而連接於同一通道。再者，該封裝PKA與圖8之封裝 PK之構成相同。另一方面，於封裝PKB中設置電路基板BDB，於電路基板BDB上安裝有半導體晶片PB0~PB7。於電路基板BDB之背面設置有IO端子BPB。各半導體晶片PB0~PB7之焊墊電極藉由經由接合線WLB連接於IO端子BPB，而連接於同一通道。於各半導體晶片PB0~PB7上設置有圖8(c)之焊墊電極D1B、ODT電路11B、輸出緩衝器12B、保護電阻R0B及輸入電路13B。此處，焊墊電極D1B係藉由切斷自焊墊電極D1B被引出之配線SB而與ODT電路11B斷接。IO端子BPA、BPB藉由經由傳輸線路2連接於控制器3，而於複數個封裝PKA、PKB間採用同一通道構成。
而且，於對半導體晶片PA0~PA7、PB0~PB7之任一者之焊墊電極D1A、D1B輸入信號之情形時，P型電晶體P2A、P2B及N型電晶體N2A、N2B被斷開。又，藉由接通P型電晶體P1A及N型電晶體N1A，而將焊墊電極D1A、D1B設定為電源電位VCC與接地電位GND之間之中間電位。此時，藉由使電阻R1A、R2A之合成電阻值與傳輸線路2之電阻值一致，可於其與傳輸線路2之間採取阻抗匹配。因此，可防止經由傳輸線路2輸入至焊墊電極D1A、D1B之信號被反射，可使信號之傳輸效率化。又，可由電阻R1A、R2A限制經由傳輸線路2輸入至焊墊電極D1A、D1B之信號之上下限，而可謀求信號之小振幅化。
又，藉由以複數個封裝PKA、PKB之焊墊電極D1A、D1B共用ODT電路11A，可消除施加至複數個封裝PKA、PKB之焊墊電極D1B之ODT電路11B之電容，而可降低IO端子BPA、BPB之引腳電容。
(第8實施形態)
圖10係顯示第8實施形態之半導體裝置之系統構成之剖面圖。
於圖10中，於封裝PKA中設置電路基板BDA，於電路基板BDA上安裝有半導體晶片PA0~PA7。於電路基板BDA之背面設置有IO端子BPA。各半導體晶片PA0~PA7之焊墊電極藉由經由接合線WLA連 接於IO端子BPA，而連接於同一通道。於封裝PKC中設置電路基板BDC，於電路基板BDC上安裝有半導體晶片PC0~PC7。於電路基板BDC之背面設置有IO端子BPC。各半導體晶片PC0~PC7之焊墊電極藉由經由接合線WLC連接於IO端子BPC，而連接於同一通道。再者，該封裝PKA、PKC與圖8之封裝PK之構成相同。IO端子BPA、BPC經由傳輸線路2連接於控制器3，藉由於複數個封裝PKA、PKC間採用同一通道構成。
而且，於對封裝PKA之半導體晶片PA0~PA7之任一者之焊墊電極D1A、D1B輸入信號之情形時，半導體晶片PA0~PA7、PC0~PC7之P型電晶體P2A、P2B及N型電晶體N2A、N2B被斷開。又，藉由斷開封裝PKA之半導體晶片PA0之P型電晶體P1A及N型電晶體N1A，且接通封裝PKC之半導體晶片PC0之P型電晶體P1A及N型電晶體N1A，而將封裝PKC之半導體晶片PC0~PC7之焊墊電極D1A、D1B設定為電源電位VCC與接地電位GND之間之中間電位。
此時，藉由使電阻R1A、R2A之合成電阻值與傳輸線路2之電阻值一致，可於其與傳輸線路2之間採取阻抗匹配。因此，由於可防止經由傳輸線路2輸入至封裝PKC之焊墊電極D1A、D1B之信號被反射，且可防止來自封裝PKC側之反射波被輸入至封裝PKA側，故可使封裝PKA側之信號之傳輸效率化。
另一方面，於對封裝PKC之半導體晶片PC0~PC7之任一者之焊墊電極D1A、D1B輸入信號之情形時，半導體晶片PA0~PA7、PC0~PC7之P型電晶體P2A、P2B及N型電晶體N2A、N2B被斷開。又，藉由斷開封裝PKC之半導體晶片PC0之P型電晶體P1A及N型電晶體N1A，且接通封裝PKA之半導體晶片PA0之P型電晶體P1A及N型電晶體N1A，而將封裝PKA之半導體晶片PA0~PA7之焊墊電極D1A、D1B設定為電源電位VCC與接地電位GND之間之中間電位。
此時，藉由使電阻R1A、R2A之合成電阻值與傳輸線路2之電阻值一致，可於其與傳輸線路2之間採取阻抗匹配。因此，由於可防止經由傳輸線路2輸入至封裝PKA之焊墊電極D1A、D1B之信號被反射，且可防止來自封裝PKA側之反射波被輸入至封裝PKC側，故可使封裝PKC側之信號之傳輸效率化。
雖已說明本發明之若干實施形態，但該等實施形態係作為例子而提示者，並非意圖限定發明之範圍。該等新穎之實施形態可以其他各種形態實施，於不脫離發明主旨之範圍內可進行各種省略、置換、變更。該等實施形態或其變化包含在發明範圍或主旨內，且包含在申請專利範圍所揭示之發明及其均等之範圍內。
B1‧‧‧半導體晶片
D1‧‧‧焊墊電極
F1‧‧‧擴散層
F2‧‧‧擴散層
G1‧‧‧閘極電極
H1‧‧‧下層配線
H2‧‧‧下層配線
H3‧‧‧上層配線
P1‧‧‧P型電晶體
R1‧‧‧電阻
T1‧‧‧接點
T2‧‧‧接點
T3‧‧‧接點

Claims (19)

  1. 一種半導體裝置，其包括：電晶體，其形成於半導體晶片上；下層配線，其連接於上述電晶體之擴散層，且被引出至上述擴散層之外；及上層配線，其自形成於上述半導體晶片上之焊墊電極被引出，且連接於上述下層配線，且電阻率小於上述下層配線；其中於上述擴散層之外，上述下層配線包含折回構造。
  2. 如請求項1之半導體裝置，其中上述電晶體包含：P型電晶體、及N型電晶體，且上述下層配線包含：第1下層配線，其成為串聯連接於上述P型電晶體之第1電阻；及第2下層配線，其成為串聯連接於上述N型電晶體之第2電阻。
  3. 如請求項2之半導體裝置，其中上述P型電晶體、上述N型電晶體、上述第1電阻及上述第2電阻構成ODT(On Die Termination)電路或輸出緩衝器。
  4. 如請求項1之半導體裝置，其中上述下層配線之熔點高於上述上層配線。
  5. 如請求項1之半導體裝置，其中上述下層配線之電遷移耐性高於上述上層配線。
  6. 如請求項1之半導體裝置，其中上述下層配線為W，上述上層配線為Al或Cu。
  7. 如請求項1之半導體裝置，其於上述擴散層上進而包含內襯上述下層配線之襯裏配線。
  8. 一種半導體裝置，其包括：電晶體，其形成於半導體晶片上；下層配線，其連接於上述電晶體之擴散層，且被引出至上述擴散層之外；上層配線，其自形成於上述半導體晶片上之焊墊電極被引出，且連接於上述下層配線，且電阻率小於上述下層配線；及基底層，其以短條狀形成於被引出至上述擴散層之外之下層配線下。
  9. 如請求項8之半導體裝置，其中上述基底層含上述電晶體之閘極電極材而構成。
  10. 如請求項8之半導體裝置，其中上述基底層含被嵌入至上述半導體晶片且以STI(Shallow Trench Isolation)予以分離之擴散層而構成。
  11. 如請求項8之半導體裝置，其中上述基底層由複數個下層配線所共用。
  12. 如請求項8之半導體裝置，其中上述基底層與上述下層配線正交。
  13. 如請求項8之半導體裝置，其中上述基底層於上述下層配線之折曲部分構成為L字狀。
  14. 如請求項8之半導體裝置，其中上述基底層之電位設定為浮動狀態。
  15. 一種半導體裝置，其包括：第1半導體晶片，其包含連接於ODT電路之第1焊墊電極；及第2半導體晶片，其包含第2焊墊電極，該第2焊墊電極與上述第1焊墊電極連接於同一通道，且共用連接於上述第1焊墊電極之上述ODT電路。
  16. 如請求項15之半導體裝置，其中上述第1半導體晶片與上述第2半導體晶片於同一封裝內相互積層。
  17. 如請求項15之半導體裝置，其中上述第2焊墊電極與形成於上述第2半導體晶片之ODT電路切斷。
  18. 如請求項15之半導體裝置，其包含與搭載有上述第1半導體晶片及上述第2半導體晶片之第1封裝不同之第2封裝；且上述第2封裝包含第3半導體晶片，該第3半導體晶片具有與上述第1焊墊電極連接於同一通道、且共用上述ODT電路之第3焊墊電極。
  19. 一種半導體裝置，其包含：第1封裝，其搭載有共用第1ODT電路之複數個第1半導體晶片；及第2封裝，其搭載有共用第2ODT電路、且與上述第1半導體晶片構成同一通道之複數個第2半導體晶片；且於上述第1半導體晶片之信號輸入時斷開上述第1ODT電路，且接通上述第2ODT電路，於上述第2半導體晶片之信號輸入時斷開上述第2ODT電路，且接通上述第1ODT電路。
TW102138309A 2013-07-05 2013-10-23 半導體裝置 TWI525788B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201361843184P 2013-07-05 2013-07-05

Publications (2)

Publication Number Publication Date
TW201503316A TW201503316A (zh) 2015-01-16
TWI525788B true TWI525788B (zh) 2016-03-11

Family

ID=52132242

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102138309A TWI525788B (zh) 2013-07-05 2013-10-23 半導體裝置

Country Status (3)

Country Link
US (1) US9401324B2 (zh)
CN (1) CN104282654B (zh)
TW (1) TWI525788B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6921085B2 (ja) * 2015-12-22 2021-08-18 サーマツール コーポレイション ワークピース加熱用の微調整された出力を有する高周波電源システム
US11121363B2 (en) * 2016-08-31 2021-09-14 Panasonic Intellectual Property Management Co., Ltd. Positive electrode active material for non-aqueous electrolyte secondary batteries, and non-aqueous electrolyte secondary battery

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07152461A (ja) 1993-12-01 1995-06-16 Hitachi Ltd 半導体装置
JP3415499B2 (ja) * 1999-07-16 2003-06-09 エヌイーシーマイクロシステム株式会社 半導体集積回路
JP3808026B2 (ja) 2002-10-23 2006-08-09 株式会社ルネサステクノロジ 半導体装置
JP4583725B2 (ja) 2003-05-16 2010-11-17 ルネサスエレクトロニクス株式会社 半導体装置
JP5053579B2 (ja) 2006-06-28 2012-10-17 寛治 大塚 静電気放電保護回路
JP2011082450A (ja) * 2009-10-09 2011-04-21 Elpida Memory Inc 半導体装置及びこれを備える情報処理システム
JP5714280B2 (ja) * 2010-09-17 2015-05-07 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置
JP2012203807A (ja) 2011-03-28 2012-10-22 Elpida Memory Inc メモリモジュール

Also Published As

Publication number Publication date
US9401324B2 (en) 2016-07-26
US20150008582A1 (en) 2015-01-08
TW201503316A (zh) 2015-01-16
CN104282654A (zh) 2015-01-14
CN104282654B (zh) 2017-12-19

Similar Documents

Publication Publication Date Title
TWI496225B (zh) Semiconductor integrated circuit device
TWI712051B (zh) 半導體裝置及其製造方法
TWI514517B (zh) 積體電路
US9443860B1 (en) Semiconductor device having E-fuse and method for fabricating the same
US7863652B2 (en) Semiconductor integrated circuit device
KR20210152147A (ko) 수직형 구조를 갖는 메모리 장치
US9224488B2 (en) Semiconductor memory device
US20130228867A1 (en) Semiconductor device protected from electrostatic discharge
JP2016076536A (ja) 半導体装置
TWI525788B (zh) 半導體裝置
US11450611B2 (en) Semiconductor device and method of manufacturing the same
JP6970357B2 (ja) 半導体集積回路装置
TWI455292B (zh) 快閃記憶體與其製作方法
US11990475B2 (en) Semiconductor device
US11688726B2 (en) Semiconductor device
TWI712159B (zh) 半導體記憶裝置及其製造方法
TWI776487B (zh) 半導體記憶裝置
US8519467B2 (en) Semiconductor device
WO2014045989A1 (ja) 半導体ウェハ、半導体装置および半導体装置の製造方法
JP2016219655A (ja) 半導体装置
TWI740568B (zh) 半導體裝置
US20220302056A1 (en) Semiconductor storage device and method for fabricating semiconductor storage device
KR20220057044A (ko) 반도체 장치