TWI524501B - 發光二極體封裝結構及其製造方法 - Google Patents
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
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- 230000005611 electricity Effects 0.000 description 1
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- 150000004767 nitrides Chemical class 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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Description
本發明涉及一種發光二極體封裝結構及其製造方法。
相比於傳統之發光源,發光二極體(Light Emitting Diode,LED)具有重量輕、體積小、污染低、壽命長等優點,其作為一種新型之發光源,已經被越來越廣泛地應用。
在一般之發光二極體封裝結構中,通常會設置一齊納二極體(Zener diode),用於防止突波或靜電造成元件電路受損。然而,傳統之發光二極體封裝結構中,齊納二極體與發光二極體晶片通常是被設置在同一平面上,這樣之設置會造成發光二極體晶片發出之光線容易被齊納二極體吸收,從而減少了發光二極體封裝結構之出光亮度。
有鑑於此,有必要提供一種出光亮度較高之發光二極體封裝結構及其製造方法。
一種發光二極體封裝結構,其包括基板以及設置於該基板上之發光二極體晶片和齊納二極體。所述基板包括上表面以及與該上表面相對之下表面。所述基板之上表面朝下表面開設一凹槽。所述發光二極體晶片設置於基板之上表面上,所述齊納二極體設置於
所述凹槽中。所述凹槽中還形成有一覆蓋齊納二極體之反射層。
一種發光二極體封裝結構之製造方法,其包括以下幾個步驟:提供一基板,所述基板包括一上表面以及與該上表面相對之下表面,所述基板上表面朝下表面開設形成一凹槽;將一發光二極體晶片設置於所述基板之上表面上;將一齊納二極體設置於所述基板之凹槽中;在凹槽中形成覆蓋齊納二極體之反射層。
上述之發光二極體封裝結構及其製造方法中,齊納二極體設置在基板之凹槽中,並且其上覆蓋一層反射層,因此可以大大減少齊納二極體對發光二極體晶片所發出之光線之吸收,從而可以提高發光二極體封裝結構之出光亮度。
100‧‧‧發光二極體封裝結構
10‧‧‧基板
20‧‧‧發光二極體晶片
30‧‧‧齊納二極體
40‧‧‧封裝層
50‧‧‧反射層
11‧‧‧第一電極
12‧‧‧第二電極
13‧‧‧絕緣層
10a‧‧‧上表面
10b‧‧‧下表面
10c‧‧‧凹槽
圖1為本發明實施方式中之發光二極體封裝結構之俯視圖。
圖2為圖1中之發光二極體封裝結構之側視圖。
圖3至圖8為本發明實施方式中之發光二極體封裝結構之製造方法之各步驟示意圖。
請參閱圖1以及圖2,本發明實施方式提供之一種發光二極體封裝結構100包括基板10、設置於基板10上之發光二極體晶片20和齊納二極體30以及覆蓋發光二極體晶片20和齊納二極體30之封裝層40。
所述基板10包括第一電極11、第二電極12以及絕緣層13。所述第
二電極12大致呈一矩形之塊狀結構,其位於基板10之角落處;所述第一電極11大致呈一“L”形之塊狀結構,其與第二電極12相互間隔並部分圍繞所述第二電極12;所述絕緣層13充填於第一電極11與第二電極12之間之間隙內,其大致呈一“L”形,用於連接第一電極11與第二電極12並使兩者電絕緣。所述第一電極11、第二電極12以及絕緣層13共同構成之基板10大致呈一長方形之板狀結構。在本實施方式中,所述第一電極11為p型電極,所述第二電極12為n型電極。
所述基板10還包括一上表面10a以及與該上表面10a相對之下表面10b。所述基板10之一端由上表面10a朝下表面10b方向被開設形成一凹槽10c,該凹槽10c貫通基板10之側面,所述第二電極12之一部分、絕緣層13之一部分以及第一電極11之一部分由該凹槽10c之底面露出。具體之,在本實施方式中,所述凹槽10c位於第二電極12之一側並沿基板10之短邊方向開設(如圖1所示)。
所述發光二極體晶片20設置於基板10之上表面10a之第一電極11上,並且藉由導線分別電性連接上表面10a上之第一電極11和第二電極12。所述齊納二極體30設置於凹槽10c中之第二電極12上,並分別電性連接凹槽10c中之第一電極11和第二電極12。
所述凹槽10c中還形成有反射層50,該反射層50覆蓋齊納二極體30並填充於整個凹槽10c中。所述反射層50為矽膠等可固性不透明膠體,其內還包含有反射顆粒TiO2或SiO2。所述反射層50之頂面與所述基板10之上表面10a齊平。
所述封裝層40形成在基板10之上表面10a上,並覆蓋發光二極體晶片20以及反射層50。所述封裝層40為一透明結構,其材質可為
矽、環氧樹脂等。所述封裝層40中還可摻入螢光粉。所述螢光粉材質可選自石榴石(garnet)、矽酸鹽、氮化物、氮氧化物、磷化物、硫化物中之一或幾種組合之化合物。
在本發明之發光二極體封裝結構100中,因為齊納二極體30設置在基板10之凹槽10c中,並且其上覆蓋一層反射層50,所以可以大大減少齊納二極體30對發光二極體晶片20所發出之光線之吸收,從而可以提高發光二極體封裝結構100之出光亮度。
本發明實施方式提供之發光二極體封裝結構100之製造方法包括以下幾個步驟:
步驟一:請參閱圖3以及圖4,提供一基板10,所述基板10包括第一電極11、第二電極12以及位於第一電極11和第二電極12之間之絕緣層13。所述基板10還包括一上表面10a以及與該上表面10a相對之下表面10b。所述基板10之一端由上表面10a朝下表面10b方向被開設形成一凹槽10c,該凹槽10c貫通基板10之側面,並且所述第二電極12之一部分、絕緣層13之一部分以及第一電極11之一部分由該凹槽10c之底面露出。
步驟二:請參閱圖5以及圖6,將一發光二極體晶片20設置於基板10之上表面10a之第一電極11上,並且藉由導線分別電性連接上表面10a之第一電極11和第二電極12。
步驟三:將一齊納二極體30設置於基板10之凹槽10c中之第二電極12上,並分別電性連接凹槽10c中之第一電極11和第二電極12。
步驟四:請參閱圖7以及圖8,在凹槽10c中形成覆蓋齊納二極體
30之反射層50。所述反射層50之頂面與所述基板10之上表面10a齊平。
步驟五:請接著參閱圖1以及圖2,在所述基板10之上表面10a上形成一封裝層40。由此完成整個發光二極體封裝結構100之製作。
10‧‧‧基板
20‧‧‧發光二極體晶片
30‧‧‧齊納二極體
40‧‧‧封裝層
50‧‧‧反射層
11‧‧‧第一電極
12‧‧‧第二電極
13‧‧‧絕緣層
10a‧‧‧上表面
10b‧‧‧下表面
10c‧‧‧凹槽
Claims (8)
- 一種發光二極體封裝結構,其包括基板以及設置於該基板上之發光二極體晶片和齊納二極體,所述基板包括上表面以及與該上表面相對之下表面,其改進在於:所述基板之上表面朝下表面開設一凹槽,所述發光二極體晶片設置於基板之上表面上,所述齊納二極體設置於所述凹槽中,所述凹槽中還形成有一覆蓋齊納二極體之反射層,所述基板由第一電極、第二電極以及位於第一電極和第二電極之間之絕緣層構成,所述基板為長方形之板狀結構,所述第二電極呈一矩形之塊狀結構,位於所述基板之角落處,所述第一電極呈一“L”形之塊狀結構,與第二電極相互間隔並部分圍繞所述第二電極,所述絕緣層充填於第一電極與第二電極之間之間隙內,絕緣層呈一“L”形。
- 如申請專利範圍第1項所述之發光二極體封裝結構,其中:所述凹槽開設形成在所述基板之一端,並貫通所述基板之側面,所述第二電極之一部分、絕緣層之一部分以及第一電極之一部分由該凹槽之底面露出。
- 如申請專利範圍第1項所述之發光二極體封裝結構,其中:所述發光二極體晶片設置於所述基板上表面之第一電極上,並且藉由導線分別電性連接上表面上之第一電極和第二電極。
- 如申請專利範圍第1項所述之發光二極體封裝結構,其中:所述齊納二極體設置於所述凹槽中之第二電極上,並分別電性連接凹槽中之第一電極和第二電極。
- 如申請專利範圍第1項所述之發光二極體封裝結構,其中:所述反射層之頂面與所述基板之上表面齊平。
- 如申請專利範圍第1項所述之發光二極體封裝結構,其中:所述反射層為 可固性不透明膠體,內包含有反射顆粒。
- 如申請專利範圍第1項所述之發光二極體封裝結構,其中:所述發光二極體封裝結構還包括一封裝層,該封裝層形成在所述基板之上表面上,並覆蓋發光二極體晶片以及反射層。
- 一種發光二極體封裝結構之製造方法,其包括以下幾個步驟:提供一基板,所述基板包括一上表面以及與該上表面相對之下表面,所述基板上表面朝下表面開設形成一凹槽,所述基板由第一電極、第二電極以及位於第一電極和第二電極之間之絕緣層構成,所述基板為長方形之板狀結構,所述第二電極呈一矩形之塊狀結構,位於所述基板之角落處,所述第一電極呈一“L”形之塊狀結構,與第二電極相互間隔並部分圍繞所述第二電極,所述絕緣層充填於第一電極與第二電極之間之間隙內,絕緣層呈一“L”形;將一發光二極體晶片設置於所述基板之上表面上;將一齊納二極體設置於所述基板之凹槽中;在凹槽中形成覆蓋齊納二極體之反射層。
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US20150054009A1 (en) | 2015-02-26 |
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