TWI522770B - Bandgap reference circuit - Google Patents

Bandgap reference circuit Download PDF

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TWI522770B
TWI522770B TW103121846A TW103121846A TWI522770B TW I522770 B TWI522770 B TW I522770B TW 103121846 A TW103121846 A TW 103121846A TW 103121846 A TW103121846 A TW 103121846A TW I522770 B TWI522770 B TW I522770B
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voltage
current source
bipolar transistor
base
bandgap reference
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TW103121846A
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TW201600951A (en
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粘書瀚
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晶豪科技股份有限公司
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能隙參考電路 Bandgap reference circuit

本發明係關於一種參考電路;特別關於一種能隙參考電路。 The present invention relates to a reference circuit; and more particularly to a bandgap reference circuit.

能隙參考電路係用於產生準確的輸出電壓。能隙參考電路所產生的輸出電壓不會受製程、供應電源和溫度變化的影響。因此,能隙參考電路可廣泛使用於各種的類比電路和數位電路中,該些電路在運作時需要準確的參考電壓。 The bandgap reference circuit is used to generate an accurate output voltage. The output voltage generated by the bandgap reference circuit is not affected by process variations, power supply, and temperature variations. Therefore, the bandgap reference circuit can be widely used in various analog circuits and digital circuits, which require an accurate reference voltage during operation.

第1圖例示一常見的能隙參考電路100。參照第1圖,該能隙參考電路100包含PMOS電晶體M1、M2和M3,一運算放大器OP,電阻R1和R2以及雙極性電晶體(bipolar transistor)Q1、Q2和Q3。當忽略基極電流時,該能隙參考電路100的輸出電壓VOUT可以表示為:VOUT=VEB3+VT×lnN×R2/R1 (1) Figure 1 illustrates a conventional bandgap reference circuit 100. Referring to FIG. 1, the bandgap reference circuit 100 includes PMOS transistors M1, M2, and M3, an operational amplifier OP, resistors R1 and R2, and bipolar transistors Q1, Q2, and Q3. When the base current is ignored, the output voltage VOUT of the bandgap reference circuit 100 can be expressed as: VOUT = VEB3 + VT × lnN × R2/R1 (1)

其中,VEB3為雙極性電晶體Q3的射極-基極間電壓差,VT為室溫時的熱電壓(thermal voltage),N為雙極性電晶體Q2之電流密度和雙極性電晶體Q1之電流密度的比例。 Among them, VEB3 is the emitter-base voltage difference of bipolar transistor Q3, VT is the thermal voltage at room temperature, N is the current density of bipolar transistor Q2 and the current of bipolar transistor Q1. The ratio of density.

如方程式(1)所示,在調整電阻R2和R1的阻值比 例後,該能隙參考電路100可以提供具有零溫度係數的穩定輸出電壓VOUT。該電壓VOUT的電壓位準約為1.25V,接近於矽能隙(energy gap)的電子伏(electron volt),亦即,矽能隙參考電壓。 As shown in equation (1), adjust the resistance ratio of resistors R2 and R1 After the example, the bandgap reference circuit 100 can provide a stable output voltage VOUT having a zero temperature coefficient. The voltage level of the voltage VOUT is about 1.25V, which is close to the electron volt of the energy gap, that is, the 矽 energy gap reference voltage.

本發明的目的之一在於提供一種能隙參考電路,以提供具有溫度相依之斜率電流和具有零溫度係數的輸出電壓。 One of the objects of the present invention is to provide a bandgap reference circuit to provide a temperature dependent slope current and an output voltage having a zero temperature coefficient.

依據本發明一實施例,該能隙參考電路包含有一第一電流源、一第二電流源、一第三電流源、一運算放大器、一第一雙極性電晶體、一分壓電路、一第二雙極性電晶體、一第三雙極性電晶體及一第一電阻。該運算放大器電氣連接至該等第一至第三電流源。該第一雙極性電晶體具有電氣連接至該第一電流源的一射極,和具有電氣連接至一接地電壓的一基極和一集極。該分壓電路電氣連接於該第一雙極性電晶體之該射極和該基極之間,該分壓電路提供比例於該第一雙極性電晶體之射極-基極間電壓差的一第一電壓和一第二電壓。該第二雙極性電晶體具有用以接收該第一電壓的一基極,具有電氣連接至該第二電流源的一射極,具有電氣連接至該接地電壓的一集極。該第三雙極性電晶體具有用以接收該第二電壓的一基極,和具有電氣連接至該接地電壓的一集極。該第一電阻電氣連接於該第三電流源和該第三雙極性電 晶體的一射極之間。 According to an embodiment of the invention, the gap reference circuit includes a first current source, a second current source, a third current source, an operational amplifier, a first bipolar transistor, a voltage dividing circuit, and a a second bipolar transistor, a third bipolar transistor, and a first resistor. The operational amplifier is electrically coupled to the first to third current sources. The first bipolar transistor has an emitter electrically coupled to the first current source and a base and a collector electrically coupled to a ground voltage. The voltage dividing circuit is electrically connected between the emitter of the first bipolar transistor and the base, and the voltage dividing circuit provides a ratio of an emitter-base voltage difference of the first bipolar transistor a first voltage and a second voltage. The second bipolar transistor has a base for receiving the first voltage, an emitter electrically coupled to the second current source, and a collector electrically coupled to the ground voltage. The third bipolar transistor has a base for receiving the second voltage and a collector having an electrical connection to the ground voltage. The first resistor is electrically connected to the third current source and the third bipolar Between one emitter of the crystal.

100‧‧‧能隙參考電路 100‧‧‧Gap reference circuit

200,200’,200”‧‧‧能隙參考電路 200,200’,200”‧‧‧Gap Reference Circuit

22,22’‧‧‧電流源單元 22,22’‧‧‧ Current source unit

24‧‧‧分壓電路 24‧‧‧voltage circuit

M1,M2,M3,M4‧‧‧PMOS電晶體 M1, M2, M3, M4‧‧‧ PMOS transistors

OP‧‧‧運算放大器 OP‧‧‧Operational Amplifier

Q1,Q2,Q3,Q4‧‧‧雙極性電晶體 Q1, Q2, Q3, Q4‧‧‧ bipolar transistor

R1,R2,R3,R4 R5‧‧‧電阻 R1, R2, R3, R4 R5‧‧‧ resistance

第1圖例示一常見的能隙參考電路。 Figure 1 illustrates a common bandgap reference circuit.

第2圖顯示結合本發明一實施例之能隙參考電路之電路圖。 Figure 2 is a circuit diagram showing a bandgap reference circuit incorporating an embodiment of the present invention.

第3圖顯示結合本發明另一實施例之能隙參考電路之電路圖。 Figure 3 is a circuit diagram showing a bandgap reference circuit incorporating another embodiment of the present invention.

第4圖顯示結合本發明又一實施例之能隙參考電路之電路圖。 Figure 4 is a circuit diagram showing a bandgap reference circuit incorporating yet another embodiment of the present invention.

第2圖顯示結合本發明一實施例之能隙參考電路200之電路圖。如第2圖所示,該能隙參考電路200包含一電流源單元22,一分壓電路24,一運算放大器OP,一電阻R1和複數個雙極性電晶體Q1、Q2和Q3。在本實施例中,該電流源單元22是由三個PMOS電晶體M1、M2和M3所組成。該些電晶體M1、M2和M3電性連接至一供應電源VDD以提供電流I1、I2和I3。由於PMOS電晶體M1、M2和M3的閘極彼此相連,流過PMOS電晶體M1,M2,和M3的電流會正比於電晶體的寬長比(W/L ratio)。 Figure 2 shows a circuit diagram of a bandgap reference circuit 200 incorporating an embodiment of the present invention. As shown in FIG. 2, the bandgap reference circuit 200 includes a current source unit 22, a voltage dividing circuit 24, an operational amplifier OP, a resistor R1 and a plurality of bipolar transistors Q1, Q2 and Q3. In the present embodiment, the current source unit 22 is composed of three PMOS transistors M1, M2, and M3. The transistors M1, M2 and M3 are electrically connected to a supply source VDD to provide currents I1, I2 and I3. Since the gates of the PMOS transistors M1, M2, and M3 are connected to each other, the current flowing through the PMOS transistors M1, M2, and M3 is proportional to the width to length ratio (W/L ratio) of the transistor.

在本實施例中,電流源單元22中的PMOS電晶體M1、M2和M3的尺寸比例設定為2:1:1。因此,電流I1、I2和I3 的電流值比例為2:1:1。 In the present embodiment, the size ratio of the PMOS transistors M1, M2, and M3 in the current source unit 22 is set to 2:1:1. Therefore, currents I1, I2 and I3 The current value ratio is 2:1:1.

如第2圖所示,該雙極性電晶體Q1具有電氣連接至該PMOS電晶體M1之汲極的一射極,和具有電氣連接至一接地端的一基極和一集極。該雙極性電晶體Q2具有電氣連接至該PMOS電晶體M2之汲極的一射極,具有電氣連接至來自該分壓電路24之一電壓VB3的一基極,和具有電氣連接至一接地端的一集極。該雙極性電晶體Q3具有電氣連接至來自該分壓電路24之一電壓VB1的一基極,和具有電氣連接至一接地端的一集極。該電阻R1電氣連接於該PMOS電晶體M3的一汲極和該雙極性電晶體Q3的一射極之間。 As shown in FIG. 2, the bipolar transistor Q1 has an emitter electrically connected to the drain of the PMOS transistor M1, and a base and a collector electrically connected to a ground. The bipolar transistor Q2 has an emitter electrically connected to the drain of the PMOS transistor M2, has a base electrically connected to a voltage VB3 from the voltage dividing circuit 24, and has an electrical connection to a ground. One episode of the end. The bipolar transistor Q3 has a base electrically connected to a voltage VB1 from the voltage dividing circuit 24, and a collector electrically connected to a ground. The resistor R1 is electrically connected between a drain of the PMOS transistor M3 and an emitter of the bipolar transistor Q3.

如第2圖所示,該運算放大器OP具有電氣連接至該PMOS電晶體M3之該汲極的一正輸入端,具有電氣連接至該PMOS電晶體M2之該汲極的一負輸入端,和具有電氣連接至該等PMOS電晶體M1,M2和M3之閘極的一輸出端。該放大器OP和該等PMOS電晶體M2和M3構成一負回授迴路,使得輸入端電壓VD1和VD3實質上相同。因此,電壓VD1和VD3可表示為:VD1=VD3=VB3+VEB2=VB1+VEB3+I3×R1 (2) As shown in FIG. 2, the operational amplifier OP has a positive input terminal electrically connected to the drain of the PMOS transistor M3, and has a negative input terminal electrically connected to the drain of the PMOS transistor M2, and An output having a gate electrically connected to the PMOS transistors M1, M2 and M3. The amplifier OP and the PMOS transistors M2 and M3 form a negative feedback loop such that the input voltages VD1 and VD3 are substantially identical. Therefore, the voltages VD1 and VD3 can be expressed as: VD1 = VD3 = VB3 + VEB2 = VB1 + VEB3 + I3 × R1 (2)

其中,VEB2為該雙極性電晶體Q2的射極-基極間電壓差,VEB3為雙極性電晶體Q3的射極-基極間電壓差。 Wherein, VEB2 is the emitter-base voltage difference of the bipolar transistor Q2, and VEB3 is the emitter-base voltage difference of the bipolar transistor Q3.

如第2圖所示,該分壓電路24電氣連接至該雙極性電晶體Q1之該射極。在本實施例中,該分壓電路24是由三 個串聯連接的電阻R3,R4,和R5所組成。因此,該分壓電路24提供之電壓VB1和VB3比例於該雙極性電晶體Q1的射極-基極間電壓差。因此,電壓VB1和VB3可以表示為:VB3=VEB1×R5/(R3+R4+R5) (3) As shown in Fig. 2, the voltage dividing circuit 24 is electrically connected to the emitter of the bipolar transistor Q1. In the present embodiment, the voltage dividing circuit 24 is composed of three resistors R3, R4, and R5 connected in series. Therefore, the voltages VB1 and VB3 supplied from the voltage dividing circuit 24 are proportional to the emitter-base voltage difference of the bipolar transistor Q1. Therefore, the voltages VB1 and VB3 can be expressed as: VB3 = VEB1 × R5/(R3 + R4 + R5) (3)

VB1=VEB1×(R4+R5)/(R3+R4+R5) (4) VB1 = VEB1 × (R4 + R5) / (R3 + R4 + R5) (4)

其中,VEB1為該雙極性電晶體Q1的射極-基極間電壓差。 Wherein, VEB1 is the emitter-base voltage difference of the bipolar transistor Q1.

據此,方程式(2)可重新整理為:I3×R1=VEB2-VEB3+VB3-VB1=VT×lnN-VEB1×R4/(R3+R4+R5) (5) Accordingly, equation (2) can be rearranged as: I3 × R1 = VEB2 - VEB3 + VB3 - VB1 = VT × lnN - VEB1 × R4/(R3 + R4 + R5) (5)

其中,VT為室溫時的熱電壓(thermal voltage),N為雙極性電晶體Q2之電流密度和雙極性電晶體Q1之電流密度的比例。在本實施例中,流過該雙極性電晶體Q1的電流,流過該雙極性電晶體Q2的電流,和流過該雙極性電晶體Q3的電流會調整為實質上相同。 Wherein VT is a thermal voltage at room temperature, and N is a ratio of a current density of the bipolar transistor Q2 to a current density of the bipolar transistor Q1. In the present embodiment, the current flowing through the bipolar transistor Q1, the current flowing through the bipolar transistor Q2, and the current flowing through the bipolar transistor Q3 are adjusted to be substantially the same.

因此,流過該電阻R1的電流I3可表示為:I3=VT×lnN/R1-VEB1×R4/(R1×(R3+R4+R5)) (6) Therefore, the current I3 flowing through the resistor R1 can be expressed as: I3 = VT × lnN/R1 - VEB1 × R4/(R1 × (R3 + R4 + R5)) (6)

由於熱電壓VT具有值為0.085mV/℃的正溫度係數,而該雙極性電晶體Q1的射極-基極間電壓差具有值為-2mV/℃的負溫度係數,故電流I3具有溫度相依的斜率。由於一次項-VEB1×(R4/R3+R4+R5)),該電流I3的溫度相依斜率與先前技術相比隨溫度的變化會增加較快。 Since the thermal voltage VT has a positive temperature coefficient of 0.085 mV/° C., and the emitter-base voltage difference of the bipolar transistor Q1 has a negative temperature coefficient of -2 mV/° C., the current I3 has temperature dependence. The slope of. Due to the primary term -VEB1 x (R4/R3+R4+R5), the temperature dependent slope of this current I3 increases rapidly with temperature compared to the prior art.

如方程式(6)所示,電流I3的淨溫度係數可藉由選擇電阻R1,R3,R4,和R5的阻值和雙極性電晶體Q2之電流密度和雙極性電晶體Q1之電流密度的比例N來調整。此外,如第3圖所示,該雙極性電晶體Q2的該基極可電氣連接至來自該分壓電路24的該電壓VB1,而該電晶體Q3的該基極可電氣連接至該分壓電路24的該電壓VB3。在此架構中該電流I3的淨溫度係數會較第2圖中的電路結構來的小。 As shown in equation (6), the net temperature coefficient of current I3 can be determined by selecting the resistances of resistors R1, R3, R4, and R5 and the current density of bipolar transistor Q2 and the current density of bipolar transistor Q1. N to adjust. Furthermore, as shown in FIG. 3, the base of the bipolar transistor Q2 can be electrically connected to the voltage VB1 from the voltage dividing circuit 24, and the base of the transistor Q3 can be electrically connected to the point. This voltage VB3 of the voltage circuit 24. The net temperature coefficient of this current I3 in this architecture will be smaller than that of the circuit configuration in Figure 2.

為了提供具有零溫度係數的穩定輸出電壓,該能隙參考電路200”更包含一電阻R2和一雙極性電晶體Q4,如第4圖所示。參考第4圖,該電流源單元22’是由PMOS電晶體M1,M2,M3和M4所組成,該些電晶體的閘極是由放大器OP的輸出端所驅動。在本實施例中,該PMOS電晶體M4和該PMOS電晶體M3具有相同的尺寸。因此,流過電阻R2的電流I4會與電流I3相同,且可表示為:I4=I3=VT×lnN/R1-VEB1×R4/(R1×(R3+R4+R5)) (7) In order to provide a stable output voltage having a zero temperature coefficient, the bandgap reference circuit 200" further includes a resistor R2 and a bipolar transistor Q4, as shown in Fig. 4. Referring to Fig. 4, the current source unit 22' is It is composed of PMOS transistors M1, M2, M3 and M4, and the gates of the transistors are driven by the output terminal of the amplifier OP. In this embodiment, the PMOS transistor M4 and the PMOS transistor M3 have the same Therefore, the current I4 flowing through the resistor R2 is the same as the current I3 and can be expressed as: I4 = I3 = VT × lnN/R1 - VEB1 × R4/(R1 × (R3 + R4 + R5)) (7 )

依上述電路結構,電壓VREF可表示為:VREF=VEB4+I4×R2 (8) According to the above circuit structure, the voltage VREF can be expressed as: VREF = VEB4 + I4 × R2 (8)

其中,VEB4為該雙極性電晶體Q4的射極-基極間電壓差。 Wherein, VEB4 is the emitter-base voltage difference of the bipolar transistor Q4.

將方程式(7)代入方程式(8)中可得:VREF=VEB4+VT×lnN×R2/R1-VEB1×R2×R4/(R1×(R3+R4+R5)) (9) Substituting equation (7) into equation (8) yields : VREF = VEB4 + VT × lnN × R2/R1 - VEB1 × R2 × R4/(R1 × (R3 + R4 + R5)) (9)

因此,適當的選擇電阻R1,R2,R3,R4,和R5的阻 值,該能隙參考電路200”可獲得具有零溫度係數和對溫度之低敏感度的輸出電壓。 Therefore, the appropriate resistance of resistors R1, R2, R3, R4, and R5 is selected. Value, the bandgap reference circuit 200" can obtain an output voltage having a zero temperature coefficient and low sensitivity to temperature.

此外,與先前技術相比,第4圖的該能隙參考電路200”可工作在較低的供應電源電壓位準。回到方程式(1):VOUT=VEB3+VT×lnN×R2/R1 (1) Furthermore, the bandgap reference circuit 200" of Figure 4 can operate at a lower supply voltage level than the prior art. Return to equation (1): VOUT = VEB3 + VT × lnN × R2/R1 ( 1)

從方程式(1)可發現為獲得零溫度係數,習知的能隙參考電路的輸出電壓位準會限制在1.25V。然而,參照方程式(9),本發明所揭示之能隙參考電路的輸出電壓位準可減少一比例於VEB1的一電壓。在一範例中,如果比例N選擇為32,電阻R1,R2,R3,R4,和R5的阻值分別選擇為39KΩ,225KΩ,114KΩ,4KΩ和84KΩ,,本發明所揭示之能隙參考電路的輸出電壓位準可低至1.11V左右。因此,在本發明中能隙參考電路的供應電源電壓位準可低至1.35V。 From equation (1), it can be found that to obtain a zero temperature coefficient, the output voltage level of a conventional bandgap reference circuit is limited to 1.25V. However, referring to equation (9), the output voltage level of the bandgap reference circuit disclosed in the present invention can be reduced by a ratio of a voltage of VEB1. In an example, if the ratio N is selected to be 32, the resistances of the resistors R1, R2, R3, R4, and R5 are selected to be 39KΩ, 225KΩ, 114KΩ, 4KΩ, and 84KΩ, respectively, and the gap reference circuit disclosed in the present invention The output voltage level can be as low as 1.11V. Therefore, in the present invention, the supply voltage level of the bandgap reference circuit can be as low as 1.35V.

此外,本發明所揭示之能隙參考電路可有效地減少由於運算放大器的輸入偏移所產生的直流偏移量(DC offset)VOS。考量第1圖中的運算放大器OP的輸入偏移VOS,方程式(1)將重寫為:VOUT=VEB3+VT×lnN×R2/R1+VOS×R2/R1 (10) In addition, the bandgap reference circuit disclosed in the present invention can effectively reduce the DC offset VOS due to the input offset of the operational amplifier. Considering the input offset VOS of the op amp OP in Figure 1, equation (1) will be rewritten as: VOUT = VEB3 + VT × lnN × R2/R1 + VOS × R2/R1 (10)

因此,第1圖中的運算放大器OP的輸入偏移VOS會放大R2/R1的比例。參考第2圖,在考量運算放大器OP的輸入偏移VOS,方程式(9)將重寫為:VREF=VEB4+VT×lnN×R2/R1-VEB1×R2×R4/(R1×(R3+R4+R5)) +VOS×R2/R1 (11) Therefore, the input offset VOS of the operational amplifier OP in Fig. 1 amplifies the ratio of R2/R1. Referring to Figure 2, considering the input offset VOS of the op amp OP, equation (9) will be rewritten as: VREF = VEB4 + VT × lnN × R2/R1 - VEB1 × R2 × R4/(R1 × (R3 + R4 + R5)) + VOS × R2/R1 (11)

由於加入一次項-VEB1×R2×R4/(R1×(R3+R4+R5))至方程式(11)中,藉以獲得零溫度係數的電壓VREF。因此,在本發明中運算放大器OP的輸入偏移VOS的放大因子相較先前技術可減少。 Since the term -VEB1 × R2 × R4 / (R1 × (R3 + R4 + R5)) is added to the equation (11), the voltage VREF of zero temperature coefficient is obtained. Therefore, the amplification factor of the input offset VOS of the operational amplifier OP in the present invention can be reduced as compared with the prior art.

本發明之技術內容及技術特點已揭示如上,然而熟悉本項技術之人士仍可能基於本發明之教示及揭示而作種種不背離本發明精神之替換及修飾。因此,本發明之保護範圍應不限於實施例所揭示者,而應包括各種不背離本發明之替換及修飾,並為隨後之申請專利範圍所涵蓋。 The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be construed as not limited by the scope of the invention, and the invention is intended to be

200‧‧‧能隙參考電路 200‧‧‧Gap reference circuit

22‧‧‧電流源單元 22‧‧‧current source unit

24‧‧‧分壓電路 24‧‧‧voltage circuit

M1,M2,M3‧‧‧PMOS電晶體 M1, M2, M3‧‧‧ PMOS transistor

OP‧‧‧運算放大器 OP‧‧‧Operational Amplifier

Q1,Q2,Q3‧‧‧雙極性電晶體 Q1, Q2, Q3‧‧‧ bipolar transistor

R1,R3,R4,R5‧‧‧電阻 R1, R3, R4, R5‧‧‧ resistance

Claims (7)

一種能隙參考電路,包括:一第一電流源;一第二電流源;一第三電流源;一運算放大器,電氣連接至該等第一至第三電流源;一第一雙極性電晶體,其具有電氣連接至該第一電流源的一射極,和具有電氣連接至一接地電壓的一基極和一集極;一分壓電路,電氣連接於該第一雙極性電晶體之該射極和該基極之間,該分壓電路提供比例於該第一雙極性電晶體之射極-基極間電壓差的一第一電壓和一第二電壓;一第二雙極性電晶體,其具有用以接收該第一電壓的一基極,具有電氣連接至該第二電流源的一射極,具有電氣連接至該接地電壓的一集極;一第三雙極性電晶體,其具有用以接收該第二電壓的一基極,和具有電氣連接至該接地電壓的一集極;以及一第一電阻,其電氣連接於該第三電流源和該第三雙極性電晶體的一射極之間。 A bandgap reference circuit comprising: a first current source; a second current source; a third current source; an operational amplifier electrically connected to the first to third current sources; and a first bipolar transistor An electric pole connected to the first current source, and a base and a collector electrically connected to a ground voltage; a voltage dividing circuit electrically connected to the first bipolar transistor Between the emitter and the base, the voltage dividing circuit provides a first voltage and a second voltage proportional to an emitter-base voltage difference of the first bipolar transistor; a second bipolar a transistor having a base for receiving the first voltage, having an emitter electrically connected to the second current source, having a collector electrically connected to the ground voltage; and a third bipolar transistor Having a base for receiving the second voltage, and a collector having an electrical connection to the ground voltage; and a first resistor electrically coupled to the third current source and the third bipolar Between one emitter of the crystal. 根據申請專利範圍第1項之能隙參考電路,更包括:一第四電流源,電氣連接至該運算放大器; 一第四雙極性電晶體,其具有電氣連接至該接地電壓的一基極和一集極;以及一第二電阻,其電氣連接於該第四電流源和該第四雙極性電晶體的一射極之間;其中,該第四電流源和該第二電阻的一交叉點提供一能隙參考電壓。 According to the energy gap reference circuit of claim 1, further comprising: a fourth current source electrically connected to the operational amplifier; a fourth bipolar transistor having a base and a collector electrically connected to the ground voltage; and a second resistor electrically coupled to the fourth current source and one of the fourth bipolar transistor Between the emitters; wherein an intersection of the fourth current source and the second resistor provides a bandgap reference voltage. 根據申請專利範圍第1項之能隙參考電路,其中該分壓電路包括:複數個電阻,串聯連接於該第一雙極性電晶體的該射極和該基極之間,以提供該第一電壓和該第二電壓;其中,該第一電壓的電壓位準高於該第二電壓的電壓位準。 The bandgap reference circuit of claim 1, wherein the voltage dividing circuit comprises: a plurality of resistors connected in series between the emitter of the first bipolar transistor and the base to provide the a voltage and the second voltage; wherein the voltage level of the first voltage is higher than the voltage level of the second voltage. 根據申請專利範圍第1項之能隙參考電路,其中該分壓電路包括:複數個電阻,串聯連接於該第一雙極性電晶體的該射極和該基極之間,以提供該第一電壓和該第二電壓;其中,該第一電壓的電壓位準低於該第二電壓的電壓位準。 The bandgap reference circuit of claim 1, wherein the voltage dividing circuit comprises: a plurality of resistors connected in series between the emitter of the first bipolar transistor and the base to provide the a voltage and the second voltage; wherein the voltage level of the first voltage is lower than the voltage level of the second voltage. 根據申請專利範圍第3項之能隙參考電路,其中該分壓電路之該等電阻的阻值和該第一電阻之阻值係調整以改變該第一電流源、該第二電流源和該第三電流源之電流的溫度係數。 According to the gap reference circuit of claim 3, wherein the resistance of the resistor of the voltage dividing circuit and the resistance of the first resistor are adjusted to change the first current source, the second current source, and The temperature coefficient of the current of the third current source. 根據申請專利範圍第4項之能隙參考電路,其中該分壓電路之該等電阻的阻值和該第一電阻之阻值係調整以改變該第一電流源、該第二電流源和該第三電流源之電流的溫度係數。 According to the energy gap reference circuit of claim 4, wherein the resistance of the resistors of the voltage dividing circuit and the resistance of the first resistor are adjusted to change the first current source, the second current source, and The temperature coefficient of the current of the third current source. 根據申請專利範圍第2項之能隙參考電路,其中該分壓電路包括:複數個電阻,串聯連接於該第一雙極性電晶體的該射極和該基極之間,以提供該第一電壓和該第二電壓;其中,該第一電壓的電壓位準低於該第二電壓的電壓位準;且其中該分壓電路之該等電阻之阻值、該第一電阻之阻值和該第二電阻之阻值係選擇以使該能隙參考電壓的電壓位準低於一矽能隙參考電壓的電壓位準。 The bandgap reference circuit of claim 2, wherein the voltage dividing circuit comprises: a plurality of resistors connected in series between the emitter of the first bipolar transistor and the base to provide the a voltage and the second voltage; wherein, the voltage level of the first voltage is lower than the voltage level of the second voltage; and wherein the resistance of the resistor of the voltage dividing circuit, the resistance of the first resistor The value and the resistance of the second resistor are selected such that the voltage level of the bandgap reference voltage is lower than the voltage level of a bandgap reference voltage.
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