TWI520291B - 積體電路裝置 - Google Patents

積體電路裝置 Download PDF

Info

Publication number
TWI520291B
TWI520291B TW102111363A TW102111363A TWI520291B TW I520291 B TWI520291 B TW I520291B TW 102111363 A TW102111363 A TW 102111363A TW 102111363 A TW102111363 A TW 102111363A TW I520291 B TWI520291 B TW I520291B
Authority
TW
Taiwan
Prior art keywords
metal
layer
opening
ubm
length
Prior art date
Application number
TW102111363A
Other languages
English (en)
Other versions
TW201340275A (zh
Inventor
林彥良
陳承先
郭庭豪
吳勝郁
林宗澍
黃昶嘉
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201340275A publication Critical patent/TW201340275A/zh
Application granted granted Critical
Publication of TWI520291B publication Critical patent/TWI520291B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05012—Shape in top view
    • H01L2224/05015—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05555—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

積體電路裝置
本發明係有關於積體電路裝置，特別是有關於一種具有加長凸塊(elongated bumps)的積體電路裝置。
積體電路是由數百萬的主動裝置所組成，例如電晶體和電容器。這些裝置起初與彼此相互隔離，之後再藉由內連線以形成功能電路。典型的內連線結構包括橫向內連線，像是金屬線(導線)，以及垂直內連線，像是導孔(vias)和接點(contacts)。
連接(connector)結構形成在內連線結構的上方，連接結構包括形成並曝露在個別晶片表面上的接合墊(bond pads)或金屬凸塊。透過接合墊(bond pads)/金屬凸塊將晶片與封裝體表面或其他晶粒連接而達到電性連接。也可透過導線接合或覆晶接合製程(flip-chip bonding)而達到電性連接。
連接(connector)結構的其中一種類型包括一鋁墊，此鋁墊與底下個別的內連線結構電性連接。形成一鈍化層及一聚合物層，使部分的鈍化層及部分的聚合物層覆蓋住鋁墊的邊緣部份。形成一凸塊下金屬層(Under-Bump Metallurgy；UBM)延伸至鈍化層及聚合物層中的開口內。一銅柱及一焊帽(solder cap)可形成於凸塊下金屬層(UBM)上。
根據一些實施例，本發明提供一積體電路裝置，包括一基板；一金屬墊，位於基板上方；以及一鈍化層，覆蓋住金屬墊的多個邊緣部份，鈍化層包括與金屬墊重疊的一第一開口，且其中第一開口具有一第一橫向尺寸，其係由平行於基板之一主要表面的一方向所量測；一聚合物層，位於鈍化層上方且覆蓋住金屬墊的邊緣部份，聚合物層包括與金屬墊重疊的一第二開口，第二開口具有由上述方向量測的一第二橫向尺寸，第一橫向尺寸大於第二橫向尺寸約7微米以上；一凸塊下金屬層(Under-Bump metallurgy；UBM)，位於第二開口中的一第一部分，以及位於部分聚合物層的之上的一第二部分。
根據其他實施例，本發明提供一種積體電路裝置，包括一基板；一金屬墊，位於基板上方；以及一鈍化層，覆蓋住金屬墊的多個邊緣部份，鈍化層包括與金屬墊重疊的一第一開口，第一開口具有一第一橫向尺寸，其係由平行於基板之一主要表面的一方向所量測；一聚合物層，位於鈍化層上方且覆蓋住金屬墊的邊緣部份，聚合物層包括與金屬墊重疊的一第二開口；一凸塊下金屬層(Under-Bump metallurgy；UBM)，包括位於第二開口中的一第一部分，以及位於部分聚合物層之上的一第二部分，凸塊下金屬層(UBM)具有由上述方向量測的一第二橫向尺寸，且其中第一橫向尺寸小於第二橫向尺寸約2微米以上。
又根據其他實施例，本發明提供一種積體電路裝置，包括一基板；一金屬墊，位於基板上方；一鈍化層，覆蓋住金屬墊的多個邊緣部份，鈍化層包括位於金屬墊之上的一第 一開口，其中一部分金屬墊設置於第一開口之下，第一開口具有由一第一方向及一第二方向量測的一第一長度及一第一寬度，而第一及第二方向平行於基板的一主要表面；一聚合物層，位於鈍化層上方且覆蓋住鈍化層，其中聚合物層具有一第二開口，其中部分金屬墊設置在第二開口之下，第二開口具有各自從一第一方向及一第二方向量測的一第二長度及一第二寬度。第一長度大於第二長度約7微米以上，且第一寬度大於第二寬度約7微米以上。一凸塊下金屬層(Under-Bump metallurgy；UBM)，包括位於第二開口中的一第一部分，以及位於部分聚合物層上方的一第二部分。凸塊下金屬層(UBM)具有各自從一第一方向及一第二方向量測的一第三長度及一第三寬度。第一長度小於第三長度約2微米以上，且第一寬度小於第三寬度約2微米以上。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
1-8‧‧‧樣品晶粒
20、60‧‧‧封裝元件
30‧‧‧半導體基板
30A、62A‧‧‧表面
32‧‧‧積體電路
33‧‧‧內層介電層(ILD)
34‧‧‧金屬層
35‧‧‧金屬線
36‧‧‧導孔
38‧‧‧介電層
39‧‧‧鈍化層(pass1)
40‧‧‧金屬墊
42‧‧‧鈍化層(pass2)
46‧‧‧聚合物層
46A、50A‧‧‧頂表面
48‧‧‧凸塊下金屬層
50‧‧‧金屬柱
52‧‧‧金屬層
54‧‧‧焊帽、焊接區域
62‧‧‧金屬導線
62B‧‧‧側壁表面
142、146‧‧‧開口
DAP、Dpass2、DPIO、DUBM‧‧‧橫向尺寸
LAP、LUBM、Lpass2、LPIO‧‧‧長度
WAP、WUBM、Wpass2、WPIO‧‧‧寬度
第1圖為根據本發明實施例顯示一封裝元件之剖面圖。
第2圖顯示一封裝體，包括位於兩封裝元件之間的凸塊導線直連(bump-on-trace)結合。
第3圖顯示第1圖中各個元件的俯視圖。
以下將詳細的討論本發明較佳實施例的製造及使 用。然而，應了解的是，本發明提供許多可應用的發明概念，其可應用至各種特定的內容。特定的實施例僅為說明，而非用以限定本發明之範疇。
第1圖為根據本發明實施例顯示一封裝元件20之剖面圖。在一些實施例中，封裝元件20為一裝置晶粒。根據本發明之實施例，半導體基板30可為一塊狀矽(bulk silicon)基板或一絕緣體上覆矽(silicon-on-insulator)基板。或者，半導體基板30也可包括其他半導體材料，此半導體材料包括第Ⅲ族、第Ⅳ族、以及第V族元素。積體電路32形成於半導體基板30的表面30A上。積體電路32可包括互補式金氧半導體(Complementary Metal-Oxide-Semiconductor；CMOS)裝置。在其他的實施例中，封裝元件20可為一中介片(interposer)晶粒、封裝體基板、封裝體、或其類似的元件。在封裝元件20為一中介片(interposer)晶粒的實施例中，封裝元件20不包括主動裝置，像是電晶體。在這些實施例中，封裝元件20可包括或是不包括被動裝置，像是電阻器及電容器。
封裝元件20尚可包括位於半導體基板30上方的內層介電層(Inter-Layer Dielectric；ILD)33以及位於ILD33上方的金屬層34。金屬層34包括形成於介電層38中的金屬線35及導孔36。在一些實施例中，介電層38是由低介電常數(low-k)介電材料所形成。低介電常數(low-k)介電材料的介電常數(k值)可例如小於約2.8，或是小於約2.5。金屬線35和導孔36可由銅、銅合金、或其他金屬所形成。
金屬墊40形成於金屬層34上方，且可透過金屬線 35與導孔36與電路32在金屬層34中電性耦合。金屬墊40可為一鋁墊或一鋁-銅墊。金屬墊40的橫向尺寸被標記為DAP。橫向尺寸DAP可為由平行於基板30的主要表面(像是頂表面30A)的方向量測而得的一長度或一寬度。
形成鈍化層42以覆蓋住金屬墊40的多個邊緣部份。金屬墊40的中央部份透過鈍化層42中的開口142曝露出來(且金屬墊40的中央部份位於鈍化層42中的開口142底下)。開口142具有由平行於基板30的主要表面30A的方向量測而得的橫向尺寸Dpass2，此橫向尺寸可為一長度或一寬度。鈍化層42可為一單層或複合層，且可由一非多孔(non-porous)材料形成。在一些實施例中，鈍化層42為一複合層，包括一氧化矽層(未顯示)，以及位於氧化矽層上方的一氮化矽層(未顯示)。在其他實施例中，鈍化層42包括未摻雜矽玻璃(Un-doped Silicate Glass；USG)、氮氧化矽、及/或其類似的材料。雖然實施例中僅顯示一層鈍化層42，實際上可有多於一層的鈍化層。例如，在金屬墊40底下可有一鈍化層39。在所述實施例中，鈍化層39及鈍化層42在整份說明書中也被稱作鈍化-1(或pass1)39及鈍化-2(或pass2)42。
聚合物層46形成於鈍化層42上方且覆蓋住鈍化層42。聚合物層46可包括一聚合物，像是一環氧樹脂(epoxy)、聚亞醯胺(polyimide)、苯環丁烯(benzocyclobutene；BCB)、聚苯並噁唑(polybenzoxazole；PBO)、或其類似物。將聚合物層46圖案化以形成開口146，金屬墊40透過開口146而曝露出來。開口146具有由平行於基板30的主要表面30A的方向量測而得的 一橫向尺寸DPIO。
凸塊下金屬層(Under-Bump Metallurgy；UBM)48形成於金屬墊40上方。UBM 48包括位於聚合物層46上方的一第一部分，以及延伸至開口146與金屬墊40接觸的一第二部分。UBM 48的橫向尺寸被標記為DUBM，其由平行於基板30的主要表面30A的方向量測而得。在一些實施例中，UBM 48包括一鈦層以及由銅或銅合金形成的一晶種層(seed layer)。
金屬柱50形成於UBM 48上方，且與UBM 48具有共同的終點(co-terminus)。舉例來說，金屬柱50的每一個邊緣與UBM 48相應的邊緣對準。因此，金屬柱50的橫向尺寸各自與UBM 48的橫向尺寸相同。UBM 48與金屬墊40和金屬柱50可有物理上的接觸。在一些實施例中，金屬柱50由不會在回焊製程中(reflow processes)熔化的不可回焊金屬(non-reflowable metal(s))所形成。例如，金屬柱50可由銅或銅合金所形成。金屬柱50的頂表面50A高於聚合物層46的頂表面46A。
除了金屬柱50之外，可有其他金屬層形成於金屬柱50上，像是金屬層52。其中，金屬層52可包括一鎳層、鈀層、金層、或前述組合之多層。焊帽54也可形成在金屬層52上，其中焊帽54可由錫-銀(Sn-Ag)合金、錫-銅(Sn-Cu)合金、錫-銀-銅(Sn-Ag-Cu)合金、或其類似的材料所形成，也可由無鉛(lead-free)或含鉛(lead-containing)材料所形成。
根據一些實施例，為了減少低介電常數(low-k)介電層38中的應力以及施加於pass2 42和聚合物層46的應力，UBM 48的橫向尺寸DUBM、pass2 42中的開口142的橫向尺寸 Dpass2、以及聚合物層46中的開口146的橫向尺寸DPIO可具有以下關係：(DPIO+7μm)<Dpass2<(DUBM-2μm) [方程式1]
當滿足上述關係時，在低介電常數(low-k)介電層38、pass2 42、聚合物層46中的應力夠小，使得封裝元件20得以通過可靠性試驗(reliability tests)。
第2圖顯示金屬柱50與封裝元件60之金屬導線(trace)62之間透過一凸塊導線直連(Bump-On-Trace；BOT)之結合方式。在一些實施例中，封裝元件60為一封裝基板，其可為一層疊(laminate)基板。封裝元件60包括多個層壓(laminated)介電層，且金屬線及導孔(未顯示)內埋(embedded)在該些層疊(laminated)介電層中。在其他實施例中，封裝元件60為一裝置晶粒、封裝體、中介片(interposer)晶粒、或其類似的裝置。在凸塊導線直連(Bump-On-Trace；BOT)之結合方式中，焊接區域(solder region)54與表面62A及金屬導線62的側壁表面62B結合。
第3圖顯示實施例中金屬墊40、UBM 48、pass2開口142、以及聚合物開口146的俯視圖。示意圖中也顯示了封裝元件60(第2圖)的金屬導線62。在一些實施例中，金屬墊40、UBM 48、pass2開口142、以及聚合物開口146具有加長的俯視形狀，並具有由各自的縱向方向量測的長度及由各自的橫向方向量測的寬度。金屬導線62的縱向方向與金屬墊40、UBM 48、pass2開口142、以及聚合物開口146的縱向方向平行。方程式1中UBM 48、pass2開口142、及聚合物開口146的橫向尺寸 DUBM、Dpass2、及DPIO，可分別為長度LUBM、Lpass2、及LPIO。因此，方程式1可以下列方式重新表達：(LPIO+7μm)<Lpass2<(LUBM-2μm) [方程式2]
另外，UBM 48、pass2開口142、及聚合物開口146的橫向尺寸DUBM、Dpass2、及DPIO也可分別為寬度WUBM、Wpass2、及WPIO。因此，方程式1也可以下列方式重新表達：(WPIO+7μm)<Wpass2<(WUBM-2μm) [方程式3]
當參照第1圖及第3圖形成封裝元件20時，方程式2或方程式3可在一些實施例中成立。此外，方程式2和方程式3可同時成立。
方程式2和3不包括金屬墊40的長度LAP及寬度WAP之間的關係。實驗結果指出，金屬墊40的形狀和尺寸對於減少第1圖所示結構之應力不具有顯著的功效。因此，可以在不犧牲封裝元件20的可靠性下，有彈性的選擇金屬墊40的尺寸及形狀。
在具有不同尺寸LAP/WAP、LUBM/WUBM、Lpass2/Wpass2、及LPIO/WPIO的不同樣本晶粒20(第1圖)上進行模擬。部分的模擬結果列於表1。
在表1中，對八個具有如第1圖所示結構的樣本晶粒進行模擬，顯示各自在低介電常數(low-k)介電層38中相應的應力。測試出的應力結果以相對數值顯示在表1的最後一行，其係以樣本晶粒6中的低介電常數(low-k)介電層38中的應力為基準。樣本晶粒6除了被拿來做模擬測試之外，也形成於一物理矽基板上。結果指出，樣本晶粒6的結構在有充足安全邊際(margin)的情況下，可通過可靠性測試(reliability tests)。將一些安全邊際(margin)考慮進去，分別具有1.1、1.03、1.00、0.98、和0.97的正規化(normalized)應力的樣品4、5、6、7、和8為通過模擬的樣品；而分別具有1.19、1.19、和1.20的正規化(normalized)應力的樣品1、2、和3為失敗的樣品。另外，樣品晶粒1也形成於一物理矽基板上，結果指出是因為在各自的低介電常數(low-k)介電層38中低介電常數(low-k)分層(delamination)而導致失敗。
第二、第三、第四及第五行為橫向尺寸(長度及寬度，請參照第3圖)。表1中第二到第五行的每個表格單元格包括一個或兩個以符號“/”所分隔的數值。符號“/”前的數值為長度(微米)，符號“/”後的數值為寬度(微米)。若表格單元格只有一數值，則該數值同時代表相等的長度及寬度。對樣品晶粒1和2的LAP/WAP數值進行比較，可發現將金屬墊40(第1圖)的形狀從直徑為79微米的圓形到LAP/WAP為56/101的長型 並不會降低應力，其中樣品晶粒1和2的應力皆為1.19。這樣的結果指出，金屬墊40的尺寸和形狀並不會對應力造成影響。對樣品晶粒2和3的Lpass2/Wpass2數值進行比較，結果也顯示pass2開口142的形狀對降低應力不具有顯著性的影響。
樣品晶粒2的Lpass2及LUBM數值分別為69微米及50微米。樣品晶粒3的Lpass2及LUBM數值分別為50微米及50微米。可發現降低Lpass2及LUBM數值之間的差異並未使應力從樣品晶粒3的1.20降低到樣品晶粒4的1.1。如樣品晶粒5到8所示，當滿足Lpass2≦(LUBM-2μm)的關係時，其個別的應力低，且落入可接受的範圍內。再對樣品晶粒3到8的Lpass2及LPIO數值進行比較，可發現在滿足(LPIO+7μm)<Lpass2的關係時可獲得可接受的低應力。
表1顯示長度LAP/Lpass2/LUBM/LPIO及其個別應力之間的關係。寬度WAP/Wpass2/WUBM/WPIO及其個別的應力也具有相似的關係(請參照方程式3)。例如，表2顯示模擬的結果，其中當樣品晶粒的寬度WAP/Wpass2/WUBM/WPIO在改變時，長度LAP/Lpass2/LUBM/LPIO維持常數。應力也隨著寬度WAP/Wpass2/WUBM/WPIO的改變而改變。
表2所示的模擬結果指出當方程式3成立時，應力較低。例如，樣品晶粒1和2未滿足Wpass2<(WUBM-2μm)的關係，樣品晶粒1和2的相應應力高。樣品晶粒4到7滿足Wpass2<(WUBM-2μm)的關係，樣品晶粒4到7的相應應力則低。樣品3位於安全邊際(margin)，其應力為一從高到低的過渡應力。
在一些實施例中，藉由將凸塊(bumps)結構的尺寸最佳化，可降低低介電常數(low-k)介電層、鈍化層、及聚合物層中的應力。這樣的改良不需要額外的微影製程步驟及生產成本。此外，由於對金屬墊40的形狀及尺寸不要求，因此對金屬墊40的佈線(routing)彈性不會有不利的影響。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
20‧‧‧封裝元件
30‧‧‧半導體基板
30A‧‧‧表面
32‧‧‧積體電路
33‧‧‧內層介電層(ILD)
34‧‧‧金屬層
35‧‧‧金屬線
36‧‧‧導孔
38‧‧‧介電層
39‧‧‧鈍化層(pass1)
40‧‧‧金屬墊
42‧‧‧鈍化層(pass2)
46‧‧‧聚合物層
46A、50A‧‧‧頂表面
48‧‧‧凸塊下金屬層
50‧‧‧金屬柱
52‧‧‧金屬層
54‧‧‧焊帽
142、146‧‧‧開口
DAP、Dpass2、DPIO、DUBM‧‧‧橫向尺寸

Claims (10)

  1. 一種積體電路裝置，包括：一基板；一金屬墊，位於該基板上方；一鈍化層，覆蓋住該金屬墊的多個邊緣部份，其中該鈍化層包括與該金屬墊重疊的一第一開口，且其中該第一開口具有一第一橫向尺寸，其係由平行於該基板之一主要表面的一方向所量測；一聚合物層，位於該鈍化層上方且覆蓋住該金屬墊的該些邊緣部份，其中該聚合物層包括與該金屬墊重疊的一第二開口，其中該第二開口具有由該方向量測的一第二橫向尺寸，且其中該第一橫向尺寸大於該第二橫向尺寸約7微米以上；以及一凸塊下金屬層(Under-Bump metallurgy；UBM)，包括位於該第二開口中的一第一部分，以及位於部分該聚合物層之上的一第二部分。
  2. 如申請專利範圍第1項所述之積體電路裝置，其中該凸塊下金屬層(UBM)具有由該方向量測的一第三橫向尺寸，且其中該第一橫向尺寸小於該第三橫向尺寸約2微米以上。
  3. 如申請專利範圍第1項所述之積體電路裝置，尚包括位於該凸塊下金屬層(UBM)上方的一金屬柱。
  4. 如申請專利範圍第3項所述之積體電路裝置，其中該金屬墊、該鈍化層、該聚合物層、以及該凸塊下金屬層(UBM)包括在一裝置晶粒中，且其中該金屬柱透過凸塊導線直連 結合(bump-on-trace bond)與一封裝基板之一金屬導線接合。
  5. 如申請專利範圍第1項所述之積體電路裝置，其中該凸塊下金屬層(UBM)具有一加長的俯視形狀，並包括一長度及一小於該長度的一寬度，且其中該方向平行於該凸塊下金屬層(UBM)的一縱向方向。
  6. 如申請專利範圍第1項所述之積體電路裝置，其中該凸塊下金屬層(UBM)具有一加長的俯視形狀，並包括一長度及一小於該長度的一寬度，且其中該方向平行於該凸塊下金屬層(UBM)的一橫向方向。
  7. 如申請專利範圍第1項所述之積體電路裝置，其中該第一開口、該第二開口、以及該凸塊下金屬層(UBM)具有多個加長的俯視形狀。
  8. 一種積體電路裝置，包括：一基板；一金屬墊，位於該基板上方；一鈍化層，覆蓋住該金屬墊的多個邊緣部份，其中該鈍化層包括一第一開口，其中一部分該金屬墊設置於該第一開口之下，且其中該第一開口具有從一第一方向及一第二方向量測的一第一長度及一第一寬度，而該第一及第二方向平行於該基板的一主要表面；一聚合物層，位於該鈍化層上方且覆蓋住該鈍化層，其中該聚合物層包括一第二開口，其中該部分該金屬墊設置於該第二開口之下，其中該第二開口具有各自從一第一方向 及一第二方向量測的一第二長度及一第二寬度，且其中該第一長度大於該第二長度約7微米以上，且該第一寬度大於該第二寬度約7微米以上；以及一凸塊下金屬層(Under-Bump metallurgy；UBM)，包括位於該第二開口中的一第一部分，以及位於一部分該聚合物層上方的一第二部分，其中該凸塊下金屬層(UBM)具有各自從一第一方向及一第二方向量測的一第三長度及一第三寬度，且其中該第一長度小於該第三長度約2微米以上，且該第一寬度小於該第三寬度約2微米以上。
  9. 如申請專利範圍第8項所述之積體電路裝置，其中該第一、該第二、及該第三長度分別大於該第一、該第二、及該第三寬度。
  10. 如申請專利範圍第8項所述之積體電路裝置，尚包括位於該凸塊下金屬層(UBM)上方的一金屬柱，其中該金屬柱的多個邊緣各自對準該凸塊下金屬層(UBM)的多個邊緣。
TW102111363A 2012-03-29 2013-03-29 積體電路裝置 TWI520291B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201261617480P 2012-03-29 2012-03-29
US13/559,840 US8922006B2 (en) 2012-03-29 2012-07-27 Elongated bumps in integrated circuit devices

Publications (2)

Publication Number Publication Date
TW201340275A TW201340275A (zh) 2013-10-01
TWI520291B true TWI520291B (zh) 2016-02-01

Family

ID=49154894

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102111363A TWI520291B (zh) 2012-03-29 2013-03-29 積體電路裝置

Country Status (5)

Country Link
US (1) US8922006B2 (zh)
KR (1) KR101464069B1 (zh)
CN (1) CN103367301B (zh)
DE (1) DE102013103465B4 (zh)
TW (1) TWI520291B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI622147B (zh) * 2016-12-12 2018-04-21 南亞科技股份有限公司 半導體封裝

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9105588B2 (en) * 2010-10-21 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor component having a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer
US8802556B2 (en) * 2012-11-14 2014-08-12 Qualcomm Incorporated Barrier layer on bump and non-wettable coating on trace
US9224688B2 (en) * 2013-01-04 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Metal routing architecture for integrated circuits
US20150022987A1 (en) * 2013-07-18 2015-01-22 Stmicroelectronics (Crolles 2) Sas Electronic device comprising an integrated circuit chip provided with projecting electrical connection pads
US10269752B2 (en) * 2014-09-15 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package with UBM and methods of forming
US10141288B2 (en) 2015-07-31 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Surface mount device/integrated passive device on package or device structure and methods of forming
US20170141041A1 (en) * 2015-11-12 2017-05-18 Mediatek Inc. Semiconductor package assembly
KR102678759B1 (ko) * 2016-10-14 2024-06-27 삼성전자주식회사 반도체 소자
TWI652776B (zh) * 2016-10-31 2019-03-01 聯發科技股份有限公司 半導體封裝結構
US11217557B2 (en) * 2019-05-14 2022-01-04 Innolux Corporation Electronic device having conductive particle between pads
CN116387270A (zh) 2019-06-11 2023-07-04 群创光电股份有限公司 电子装置
CN113471159A (zh) * 2021-07-02 2021-10-01 颀中科技（苏州）有限公司 一种金属凸块结构的制备方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3208470B2 (ja) 1994-05-26 2001-09-10 株式会社日立製作所 Ｂｇａ型半導体装置とそれを実装する基板
JP3351355B2 (ja) * 1998-09-29 2002-11-25 株式会社デンソー 電子部品の実装構造
US7973418B2 (en) 2007-04-23 2011-07-05 Flipchip International, Llc Solder bump interconnect for improved mechanical and thermo-mechanical performance
DE102008054054A1 (de) 2008-10-31 2010-05-12 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit einem Aufbau für reduzierte Verspannung von Metallsäulen
US8759949B2 (en) 2009-04-30 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside structures having copper pillars
CN101877336B (zh) * 2009-04-30 2012-07-25 台湾积体电路制造股份有限公司 集成电路结构与形成集成电路结构的方法
US8169076B2 (en) * 2009-06-16 2012-05-01 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structures having lead-free solder bumps
US8476759B2 (en) * 2011-11-30 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI622147B (zh) * 2016-12-12 2018-04-21 南亞科技股份有限公司 半導體封裝

Also Published As

Publication number Publication date
CN103367301A (zh) 2013-10-23
US8922006B2 (en) 2014-12-30
TW201340275A (zh) 2013-10-01
DE102013103465A1 (de) 2013-10-02
KR20130111265A (ko) 2013-10-10
KR101464069B1 (ko) 2014-11-21
US20130256874A1 (en) 2013-10-03
DE102013103465B4 (de) 2015-04-30
CN103367301B (zh) 2017-04-26

Similar Documents

Publication Publication Date Title
TWI520291B (zh) 積體電路裝置
US9659903B2 (en) Method of manufacturing connector structures of integrated circuits
US11658143B2 (en) Bump-on-trace design for enlarge bump-to-trace distance
KR101449789B1 (ko) 응력을 줄이기 위한 더미 플립 칩 범프
US9570368B2 (en) Method of manufacturing semiconductor package including forming a recessed region in a substrate
KR101564138B1 (ko) 집적회로용 메탈 라우팅 아키텍처
US8970035B2 (en) Bump structures for semiconductor package
US9406632B2 (en) Semiconductor package including a substrate with a stepped sidewall structure
US10050000B2 (en) Bump-on-trace structures with high assembly yield
US8659123B2 (en) Metal pad structures in dies
US8987605B2 (en) Formation of connectors without UBM