TWI519219B - Printed circuit board and method of manufacturing for printed circuit board - Google Patents
Printed circuit board and method of manufacturing for printed circuit board Download PDFInfo
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Description
本發明係關於一種印刷電路板及印刷電路板製造方法。 The present invention relates to a printed circuit board and a method of manufacturing a printed circuit board.
最近電子產品的發展趨勢,正以多功能化及高速化加速進行。為因應此一趨勢,半導體晶片及用以封裝半導體晶片之印刷電路板亦正迅速發展。如此,一般對印刷電路板之需求包含:輕薄短小化、微細電路化、優異之電氣特性、可靠性及高速訊號傳遞等功能。 Recently, the development trend of electronic products is accelerating with multi-functionalization and high-speed. In response to this trend, semiconductor wafers and printed circuit boards for packaging semiconductor wafers are also rapidly developing. As such, the demand for printed circuit boards generally includes: thin and light, fine circuit, excellent electrical characteristics, reliability, and high-speed signal transmission.
印刷電路板包含形成於電路圖案之電路區域,與電路區域以外之虛擬區域。其中,電路區域為藉由電鍍等形成電路圖案;反觀虛擬區域則不予執行電鍍。因此,電路區域與虛擬區域間之電鍍偏差,導致印刷電路板發生翹曲現象(Warpage)。傳統主要使用線圈基板,在其內部插入線圈層,藉以防止印刷電路板之翹曲現象。然而,上述線圈基板具有厚度較厚且訊號處理時 間冗長之問題。(美國公開專利第20040058136號)。 The printed circuit board includes a circuit region formed in the circuit pattern and a virtual region outside the circuit region. Wherein, the circuit area is formed by electroplating or the like; in the reverse view, the dummy area is not subjected to electroplating. Therefore, the plating deviation between the circuit area and the dummy area causes warpage of the printed circuit board. Conventionally, a coil substrate is mainly used, and a coil layer is inserted inside to prevent warpage of the printed circuit board. However, the above coil substrate has a thick thickness and is processed by a signal The lengthy problem. (US Published Patent No. 20040058136).
有鑑於上述問題,本發明之主要目的在於提供一種可有效提升強度之印刷電路板及印刷電路板製造方法。 In view of the above problems, it is a primary object of the present invention to provide a printed circuit board and a method of manufacturing a printed circuit board which can effectively improve the strength.
本發明之另一目的,在於提供一種可有效防止翹曲現象之印刷電路板及印刷電路板製造方法。 Another object of the present invention is to provide a printed circuit board and a method of manufacturing a printed circuit board which can effectively prevent warpage.
為解決上述問題,本發明提供一種印刷電路板,其包含:一絕緣層,包含電路區域與虛擬區域;一虛擬圖案,形成於該虛擬區域絕緣層上部;及一電路圖案,形成於該電路區域之絕緣層上部,以使其具有比該虛擬圖案較薄之厚度。 In order to solve the above problems, the present invention provides a printed circuit board comprising: an insulating layer including a circuit region and a dummy region; a dummy pattern formed on an upper portion of the dummy region insulating layer; and a circuit pattern formed in the circuit region The upper portion of the insulating layer is such that it has a thickness thinner than the dummy pattern.
本發明印刷電路板,其中該虛擬區域可包含:一銅箔層,形成於該虛擬區域之該絕緣層上部;一晶種層,形成於該銅箔層上部,及一電鍍層,形成於該晶種層上部。 In the printed circuit board of the present invention, the dummy region may include: a copper foil layer formed on the upper portion of the insulating layer of the dummy region; a seed layer formed on the upper portion of the copper foil layer, and a plating layer formed on the printed circuit board Upper part of the seed layer.
本發明印刷電路板,其中該電路圖樣,可包含:一晶種層,形成於該電路區域之該絕緣層上部,及一電鍍層,形成於該晶種層上部。 In the printed circuit board of the present invention, the circuit pattern may include: a seed layer formed on the upper portion of the insulating layer in the circuit region, and a plating layer formed on the upper portion of the seed layer.
本發明刷電路板,其中該絕緣層之下部,可進一步形成虛擬圖案及電路圖案。 The brush circuit board of the present invention, wherein the lower portion of the insulating layer, can further form a dummy pattern and a circuit pattern.
本發明印刷電路板,其中該絕緣層上部及下部至少一端可進一步形成增大(build up)層,包含一種以上用以增大之絕緣層、虛擬圖案及電路圖案。 In the printed circuit board of the present invention, at least one end of the upper and lower portions of the insulating layer may further form a build up layer, including one or more insulating layers, dummy patterns and circuit patterns for increasing.
又,為解決上述問題,本發明提供一種印刷電路板製造方法,其包含:步驟1,提供基板,其包含電路區域與虛擬區域,並於絕緣層及該絕緣層上部形成有銅箔層;步驟2,去除該電路區域上部之銅箔層;及步驟3,於該基板上部形成虛擬圖案及電路圖案。 Moreover, in order to solve the above problems, the present invention provides a method of manufacturing a printed circuit board, comprising: step 1, providing a substrate comprising a circuit region and a dummy region, and forming a copper foil layer on the insulating layer and the upper portion of the insulating layer; 2, removing the copper foil layer on the upper portion of the circuit region; and step 3, forming a dummy pattern and a circuit pattern on the upper portion of the substrate.
本發明印刷電路板製造方法,其中步驟2可包含:步驟2-1,於該虛擬區域之該銅箔層上部形成蝕刻阻劑;步驟2-2,藉由該蝕刻阻劑對外露之該電路區域之該銅箔層進行蝕刻;及步驟2-3,去除該蝕刻阻劑。 The method for manufacturing a printed circuit board according to the present invention, wherein the step 2 may include: step 2-1, forming an etch resist on the upper portion of the copper foil layer of the dummy region; and step 2-2, exposing the circuit to the circuit by the etch resist The copper foil layer of the region is etched; and in steps 2-3, the etch resist is removed.
本發明印刷電路板製造方法,其中步驟3,可包含:步驟3-1,於該基板上部形成晶種層;步驟3-2,於該晶種層上部形成電鍍阻劑,其具有對應於該電路圖案及該虛擬圖案之開口部;步驟3-3,透過該電鍍阻劑之開口部形成電鍍層;步驟3-4,去除該電鍍阻劑;及步驟3-5,藉由去除該電鍍阻劑,進而去除外露之晶種層。 The method for manufacturing a printed circuit board according to the present invention, wherein the step 3 may include: step 3-1, forming a seed layer on the upper portion of the substrate; and step 3-2, forming a plating resist on the upper portion of the seed layer, which has a corresponding a circuit pattern and an opening of the dummy pattern; a step 3-3, forming a plating layer through the opening portion of the plating resist; a step 3-4, removing the plating resist; and steps 3-5, removing the plating resist The agent further removes the exposed seed layer.
本發明印刷電路板製造方法,其中在該步驟2-1,該晶種層可形成去除該銅箔層之。 The method of manufacturing a printed circuit board according to the present invention, wherein in the step 2-1, the seed layer is formed to remove the copper foil layer.
電路區域之絕緣層上部,及該虛擬區域之銅箔層上部。 The upper portion of the insulating layer of the circuit region and the upper portion of the copper foil layer of the dummy region.
本發明印刷電路板製造方法,其中在該步驟2-1,該晶種層可藉由乾式電鍍法或濕式電鍍法加以形成。 In the method of manufacturing a printed circuit board of the present invention, in the step 2-1, the seed layer can be formed by dry plating or wet plating.
本發明印刷電路板製造方法,其中在該步驟2-3,該 電鍍層可由電解電鍍法加以形成。 A printed circuit board manufacturing method of the present invention, wherein in the step 2-3, the The plating layer can be formed by electrolytic plating.
本發明印刷電路板製造方法,其中該步驟3之後,可進一步在該基板下部形成虛擬圖案及電路圖案。 In the method for manufacturing a printed circuit board of the present invention, after the step 3, a dummy pattern and a circuit pattern can be further formed on the lower portion of the substrate.
本發明印刷電路板製造方法,其中該步驟3之後,該絕緣層上部及下部至少一端,可進一步形成增大(build up)層,其包含一種以上用以增大之絕緣層、虛擬圖案及電路圖案。 The method for manufacturing a printed circuit board according to the present invention, wherein after the step 3, at least one end of the upper portion and the lower portion of the insulating layer may further form a build up layer including more than one insulating layer, dummy pattern and circuit for increasing pattern.
因此,本發明較佳實施例之印刷電路板及印刷電路板製造方法,藉由在虛擬區域形成虛擬圖案,可提升印刷電路板之強度。 Therefore, in the printed circuit board and the printed circuit board manufacturing method of the preferred embodiment of the present invention, the strength of the printed circuit board can be improved by forming a dummy pattern in the dummy area.
又,本發明較佳實施例之印刷電路板及印刷電路板製造方法,可有效防止翹曲現象。 Moreover, the printed circuit board and the printed circuit board manufacturing method of the preferred embodiment of the present invention can effectively prevent the warpage phenomenon.
本發明之特徵及優點由以下詳細說明當可更加明白。 The features and advantages of the present invention are apparent from the following detailed description.
在此先聲明,本說明書其申請專利範圍所使用之名詞,不得以通常及辭典之意義加以解釋,且發明人為了用最佳的方法說明其發明,得以適當界定名詞概念之原則下,以符合本發明技術思想之意義與概念加以解釋之。 It is hereby stated that the terms used in the scope of application of this specification are not to be interpreted in the ordinary and the meaning of the dictionary, and that the inventors have been able to properly define the concept of the nouns in order to best understand the invention. The meaning and concept of the technical idea of the present invention are explained.
100‧‧‧印刷電路板 100‧‧‧Printed circuit board
110‧‧‧基板 110‧‧‧Substrate
111‧‧‧絕緣層 111‧‧‧Insulation
112‧‧‧銅箔層 112‧‧‧copper layer
120‧‧‧晶種層 120‧‧‧ seed layer
130‧‧‧電鍍層 130‧‧‧Electroplating
150‧‧‧電路區域 150‧‧‧Circuit area
151‧‧‧電路圖案 151‧‧‧ circuit pattern
160‧‧‧虛擬區域 160‧‧‧virtual area
161‧‧‧虛擬圖案 161‧‧‧virtual pattern
210‧‧‧蝕刻阻劑 210‧‧‧etching resist
220‧‧‧電鍍阻劑 220‧‧‧ plating resist
221‧‧‧開口部 221‧‧‧ openings
第1圖為本發明較佳實施例之印刷電路板示意圖。 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic view of a printed circuit board in accordance with a preferred embodiment of the present invention.
第2圖至第9圖為本發明較佳實施例之印刷電路板製造方法示 意圖。 2 to 9 are diagrams showing a method of manufacturing a printed circuit board according to a preferred embodiment of the present invention; intention.
有關本發明之目的、優點及新穎特徵,在以下數個實施例之詳細說明及圖式中,將可清楚呈現。該等實施例係作為實施方式之舉例說明,其目的是為方便詳加說明本發明,而非用以限定本發明。 The objects, advantages and novel features of the invention are set forth in the <RTIgt; The embodiments are intended to be illustrative of the invention, and are not intended to limit the invention.
本發明被詳細描述之前,要注意的是,在以下說明中,類似的元件是以相同的編號來表示。 Before the present invention has been described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals.
又,在本發明中,〝第一〞、〝第二〞、〝一面〞、〝他面〞等名詞係為了在其他構成要素中區分構成要素而使用者,故構成要素不得被上述名詞加以限制。以下在說明本發明之際,若認為相關習知技術之具體說明對本發明之主旨有混淆視聽之情形時,則省略其詳細說明。 Further, in the present invention, the terms "first", "second", "〝", "〝面", etc. are used to distinguish the constituent elements among other constituent elements, and thus the constituent elements may not be restricted by the above nouns. . In the following description of the present invention, if a detailed description of the related art is considered to be confusing to the gist of the present invention, the detailed description thereof will be omitted.
為使 貴審查委員能進一步瞭解本發明之架構、特徵及功能,茲附以圖式及其具體實施方式詳細說明如後。 In order that the review board members can further understand the structure, features and functions of the present invention, the drawings and their specific embodiments are described in detail below.
第1圖為本發明較佳實施例之印刷電路板示意圖 1 is a schematic view of a printed circuit board according to a preferred embodiment of the present invention
請參閱第1圖,本發明印刷電路板100,可包含:一絕緣層111、一虛擬圖案161及一電路圖案151。 Referring to FIG. 1 , the printed circuit board 100 of the present invention may include an insulating layer 111 , a dummy pattern 161 , and a circuit pattern 151 .
該絕緣層111通常可由作為層間絕緣素材之複合高 分子樹脂形成。舉例而言,該絕緣層111可由預浸布、ABF(Ajinomoto Build up Film)、及FR-4、BT(Bismaleimide Triazine,雙馬來醯亞胺-三氮雜苯)等環氧系列樹脂所形成。但,在本發明之實施例中,該絕緣層111之材質並不限定於此。該絕緣層111可包含電路區域150及虛擬區域160。該電路區域150可形成電路圖案151。該虛擬區域160可為該電路區域150以外之區域。又,該虛擬區域160可形成虛擬圖案161。 The insulating layer 111 can generally be used as a composite high of interlayer insulating material. Molecular resin formation. For example, the insulating layer 111 may be formed of a prepreg, ABF (Ajinomoto Build up Film), and an epoxy series resin such as FR-4, BT (Bismaleimide Triazine, Bismaleimide Triazine). . However, in the embodiment of the present invention, the material of the insulating layer 111 is not limited thereto. The insulating layer 111 may include a circuit region 150 and a dummy region 160. The circuit region 150 may form a circuit pattern 151. The virtual area 160 can be an area other than the circuit area 150. Also, the virtual area 160 may form a dummy pattern 161.
虛擬圖案161形成於該虛擬區域160,可包含一銅箔層112、一晶種層120及一電鍍層130。該銅箔層112可形成在該絕緣層111上部。又,該銅箔層112可形成在該虛擬區域160。該虛擬圖案161之晶種層120可形成在該銅箔層112上部。又,該虛擬圖案161之電鍍層130可形成在該虛擬圖案161之晶種層120上部。如此,形成於該虛擬區域160之圖案,即該虛擬圖案161,可以包含該銅箔層112、晶種層120及電鍍層130之三層結構方式加以形成。 The dummy pattern 161 is formed on the dummy region 160 and may include a copper foil layer 112, a seed layer 120, and a plating layer 130. The copper foil layer 112 may be formed on the upper portion of the insulating layer 111. Also, the copper foil layer 112 may be formed in the dummy region 160. The seed layer 120 of the dummy pattern 161 may be formed on the upper portion of the copper foil layer 112. Moreover, the plating layer 130 of the dummy pattern 161 may be formed on the upper portion of the seed layer 120 of the dummy pattern 161. Thus, the pattern formed in the dummy region 160, that is, the dummy pattern 161 may be formed by a three-layer structure including the copper foil layer 112, the seed layer 120, and the plating layer 130.
電路圖案151形成於該電路區域150,可包含一晶種層120及一電鍍層130。該電路區域150之晶種層120,可形成在該電路區域150之絕緣層111上部。又,該電路圖案151之電鍍層130可形成於該電路區域150之晶種層120上部。如此,形成於該電路區域150之圖案,即該電路圖案151,可以包含該晶種層120及電鍍層130之雙層結構方式加以形成。 The circuit pattern 151 is formed on the circuit region 150 and may include a seed layer 120 and a plating layer 130. A seed layer 120 of the circuit region 150 may be formed on an upper portion of the insulating layer 111 of the circuit region 150. Moreover, the plating layer 130 of the circuit pattern 151 may be formed on the upper portion of the seed layer 120 of the circuit region 150. Thus, the pattern formed in the circuit region 150, that is, the circuit pattern 151, may be formed by a two-layer structure of the seed layer 120 and the plating layer 130.
如本實施例所示,該印刷電路板100係由單一絕緣層111所構成,但不限定於此。該印刷電路板100可由包含多層或單 層之該絕緣層111及電路圖案151之增大(Build up)結構所形成。 As shown in this embodiment, the printed circuit board 100 is composed of a single insulating layer 111, but is not limited thereto. The printed circuit board 100 can be comprised of multiple layers or single The insulating layer 111 of the layer and the build-up structure of the circuit pattern 151 are formed.
本發明較佳實施例之該印刷電路板100係在該虛擬區域160形成該虛擬圖案161,藉此可提升該印刷電路板100之強度,進而能夠防止印刷電路板100因該電路區域150之電路圖案151發生翹曲現象。又,本發明較佳實施例之印刷電路板100係藉由三層結構之該虛擬圖案161與雙層結構之該電路圖案151,使該虛擬區域160與該電路區域150之間具有不同厚度。即,本發明較佳實施例之印刷電路板100,可由該虛擬區域160之厚度高於該電路區域150之結構所形成。 In the preferred embodiment of the present invention, the printed circuit board 100 forms the dummy pattern 161 in the dummy region 160, thereby enhancing the strength of the printed circuit board 100, thereby preventing the printed circuit board 100 from being circuited by the circuit region 150. The pattern 151 is warped. Moreover, the printed circuit board 100 of the preferred embodiment of the present invention has a different thickness between the dummy region 160 and the circuit region 150 by the dummy pattern 161 of the three-layer structure and the circuit pattern 151 of the two-layer structure. That is, the printed circuit board 100 of the preferred embodiment of the present invention can be formed by a structure in which the thickness of the dummy region 160 is higher than that of the circuit region 150.
第2圖至第9圖為本發明較佳實施例之印刷電路板製造方法示意圖。 2 to 9 are schematic views showing a method of manufacturing a printed circuit board according to a preferred embodiment of the present invention.
請參閱第2圖,提供一基板110。該基板100可由絕緣層111及銅箔層112所形成。即,該基板100可為該絕緣層111上部及下部形成有銅箔層112之銅箔疊層板。其中,該絕緣層111通常可由作為層間絕緣素材之複合高分子樹脂形成。舉例而言,該絕緣層111,可由預浸布、ABF(Ajinomoto Build up Film)、及FR-4、BT(Bismaleimide Triazine,雙馬來醯亞胺-三氮雜苯)等環氧系列樹脂所形成。但,在本發明之實施例中,該絕緣層111之材質並不限定於此。該基板110可包含電路區域150與虛擬區域160。其中,該虛擬區域160可為該電路區域150以外之區域。 Referring to FIG. 2, a substrate 110 is provided. The substrate 100 may be formed of an insulating layer 111 and a copper foil layer 112. That is, the substrate 100 may be a copper foil laminate in which the copper foil layer 112 is formed on the upper and lower portions of the insulating layer 111. Here, the insulating layer 111 is usually formed of a composite polymer resin as an interlayer insulating material. For example, the insulating layer 111 may be made of a prepreg, an ABF (Ajinomoto Build up Film), and an epoxy series resin such as FR-4, BT (Bismaleimide Triazine, Bismaleimide Triazine). form. However, in the embodiment of the present invention, the material of the insulating layer 111 is not limited thereto. The substrate 110 can include a circuit region 150 and a dummy region 160. The virtual area 160 may be an area other than the circuit area 150.
請參閱第3圖,基板110上部可形成蝕刻阻劑210。該蝕刻阻劑210可形成在該基板110之虛擬區域160上部。如此,藉由該蝕刻阻劑210,可形成相當於該基板110之電路區域150之銅箔層112外露之結構。舉例而言,該蝕刻阻劑210可為乾式薄膜(Dry Film)。即,在該銅箔層112上部形成乾式薄膜後,透過曝光及顯像,可製作僅有該電路區域150之銅箔層112外露之佈線圖案(Patterning)。然而,該蝕刻阻劑210之材質及該蝕刻阻劑210之佈線圖案方法,並不受限於此。即,該蝕刻阻劑210可由該技術領域習知方法及材質所形成。 Referring to FIG. 3, an etch resist 210 may be formed on the upper portion of the substrate 110. The etch resist 210 may be formed on an upper portion of the dummy region 160 of the substrate 110. Thus, the etching resist 210 can form a structure in which the copper foil layer 112 corresponding to the circuit region 150 of the substrate 110 is exposed. For example, the etch resist 210 can be a dry film. That is, after a dry film is formed on the upper portion of the copper foil layer 112, a wiring pattern in which only the copper foil layer 112 of the circuit region 150 is exposed can be formed by exposure and development. However, the material of the etch resist 210 and the wiring pattern method of the etch resist 210 are not limited thereto. That is, the etch resist 210 can be formed by methods and materials known in the art.
請參閱第4圖,可在基板110執行蝕刻(Etching)。藉由執行蝕刻,外露之該電路區域150之銅箔層112可被去除。又,執行蝕刻時,該虛擬區域160之銅箔層112可受到該蝕刻阻劑210之保護。 Referring to FIG. 4, etching (Etching) can be performed on the substrate 110. The copper foil layer 112 of the exposed circuit region 150 can be removed by performing etching. Moreover, the copper foil layer 112 of the dummy region 160 may be protected by the etch resist 210 when etching is performed.
請參閱第5圖,可去除形成於基板110之蝕刻阻劑210。當去除該蝕刻阻劑210時,便可形成僅在該基板110之虛擬區域160殘存該銅箔層112之結構。又,因該銅箔層112被去除,該基板110之電路區域150進而可具有該絕緣層111外露之結構。 Referring to FIG. 5, the etch resist 210 formed on the substrate 110 can be removed. When the etch resist 210 is removed, a structure in which the copper foil layer 112 remains only in the dummy region 160 of the substrate 110 can be formed. Moreover, since the copper foil layer 112 is removed, the circuit region 150 of the substrate 110 may further have a structure in which the insulating layer 111 is exposed.
請參閱第6圖,基板110上部可形成晶種層120。該晶種層120可形成在該虛擬區域160之銅箔層112上部及該電路區域150之絕緣層111上部。該晶種層120可以作為用以電解電鍍之引入線角色。然而,形成該晶種層120之方法,並不受限於此。舉例而言,該晶種層120可由濕式電鍍法所形成,如無電解電鍍法;或可 藉由乾式電鍍法加以形成,如濺鍍(Sputtering)。 Referring to FIG. 6, a seed layer 120 may be formed on the upper portion of the substrate 110. The seed layer 120 may be formed on an upper portion of the copper foil layer 112 of the dummy region 160 and an upper portion of the insulating layer 111 of the circuit region 150. The seed layer 120 can serve as a lead-in role for electrolytic plating. However, the method of forming the seed layer 120 is not limited thereto. For example, the seed layer 120 may be formed by wet plating, such as electroless plating; or It is formed by dry plating, such as sputtering.
請參閱第7圖,可在晶種層120上部形成電鍍阻劑220。該電鍍阻劑220,可以具有對應於電路圖案151及虛擬圖案161之開口部221方式加以形成。即,該電鍍阻劑220可以在形成有該電路圖案151及該虛擬圖案161之部位形成該開口部221方式製作佈線圖案。因此,藉由該電鍍阻劑220,可使形成有該電路圖案151及該虛擬圖案161部分之該晶種層120呈外露狀態。 Referring to FIG. 7, a plating resist 220 may be formed on the upper portion of the seed layer 120. The plating resist 220 may be formed to have an opening portion 221 corresponding to the circuit pattern 151 and the dummy pattern 161. In other words, the plating resist 220 can form the wiring pattern by forming the opening portion 221 at a portion where the circuit pattern 151 and the dummy pattern 161 are formed. Therefore, the seed layer 120 on which the circuit pattern 151 and the dummy pattern 161 are formed can be exposed in an exposed state by the plating resist 220.
請參閱第8圖,可形成電鍍層130。在藉由電鍍阻劑220之開口部221外露之晶種層120上部,形成該電鍍層130。該電鍍層130可利用將該晶種層120作為引入線,藉由電解電鍍法加以形成。 Referring to FIG. 8, a plating layer 130 may be formed. The plating layer 130 is formed on the upper portion of the seed layer 120 exposed by the opening portion 221 of the plating resist 220. The plating layer 130 can be formed by electrolytic plating using the seed layer 120 as a lead-in wire.
如本實施例所示,該晶種層120及該電鍍層130可由導電性金屬所形成。舉例而言,該晶種層120及該電鍍層130可包含:銅、金、銀、鉛、鈀、釕、錫、鋰其中至少一種。 As shown in this embodiment, the seed layer 120 and the plating layer 130 may be formed of a conductive metal. For example, the seed layer 120 and the plating layer 130 may include at least one of copper, gold, silver, lead, palladium, rhodium, tin, and lithium.
請參閱第9圖,可去除電鍍阻劑220及該電鍍阻劑220下部之晶種層120。該電鍍層130形成後,可去除該電鍍阻劑220。藉由去除該電鍍阻劑220,進而亦可去除外露之該晶種層120。此時,該晶種層120可使用強鹽基(如NaOH或KOH等)之快速蝕刻法(Quick Etching)加以去除。又,該晶種層120可利用H2O2/H2SO4之閃蝕法(Flash Etching)加以去除。在此,去除該晶種層120之方法,並不受限於快速蝕刻法或閃蝕法,可藉由該技術領域習知方法加以去除。 Referring to FIG. 9, the plating resist 220 and the seed layer 120 under the plating resist 220 may be removed. After the plating layer 130 is formed, the plating resist 220 can be removed. The exposed seed layer 120 can also be removed by removing the plating resist 220. At this time, the seed layer 120 can be removed by rapid etching using a strong salt group such as NaOH or KOH. Further, the seed layer 120 can be removed by flash etching using H 2 O 2 /H 2 SO 4 . Here, the method of removing the seed layer 120 is not limited to the rapid etching method or the flash etching method, and can be removed by a conventional method in the art.
如此,當去除該電鍍阻劑220及該電鍍阻劑220下部之該晶種層120時,如第9圖所示,可形成虛擬圖案161及電路圖案151。該電路圖案151形成於電路區域150,可為由該晶種層120及該電鍍層130所構成之雙層結構。又,該虛擬圖案161形成於虛擬區域161,可為由銅箔層112、晶種層120及電鍍層130所構成之三層結構。即,如本實施例所示,可形成該虛擬區域160與該電路區域150彼此具有不同厚度之印刷電路板100。如本實施例所示,該虛擬區域160可具有其厚度高於該電路區域150之結構。 Thus, when the plating resist 220 and the seed layer 120 under the plating resist 220 are removed, as shown in FIG. 9, the dummy pattern 161 and the circuit pattern 151 can be formed. The circuit pattern 151 is formed in the circuit region 150 and may be a two-layer structure composed of the seed layer 120 and the plating layer 130. Further, the dummy pattern 161 is formed in the dummy region 161, and may have a three-layer structure composed of the copper foil layer 112, the seed layer 120, and the plating layer 130. That is, as shown in this embodiment, the printed circuit board 100 having the different thicknesses of the dummy region 160 and the circuit region 150 can be formed. As shown in this embodiment, the dummy region 160 may have a structure having a thickness higher than that of the circuit region 150.
如本發明較佳實施例之印刷電路板製造方法所示,該印刷電路板100係由單一絕緣層111所構成,但不限定於此。本發明較佳實施例之印刷電路板製造方法,可形成增大(Build up)結構之印刷電路板100,其包含多層或單層之絕緣層111及電路圖案151。 As shown in the method of manufacturing a printed circuit board according to a preferred embodiment of the present invention, the printed circuit board 100 is composed of a single insulating layer 111, but is not limited thereto. In the printed circuit board manufacturing method of the preferred embodiment of the present invention, a printed circuit board 100 having a build-up structure including a plurality of layers or a single layer of the insulating layer 111 and the circuit pattern 151 can be formed.
本發明較佳實施例之印刷電路板及印刷電路板製造方法,由於其在虛擬區域形成虛擬圖案,故可提升印刷電路板之強度,進而可有效防止藉由電路區域之電路圖案所產生之印刷電路板之翹曲現象。 In the printed circuit board and the printed circuit board manufacturing method of the preferred embodiment of the present invention, since the dummy pattern is formed in the dummy area, the strength of the printed circuit board can be improved, and the printing by the circuit pattern of the circuit area can be effectively prevented. The warpage of the board.
以上所述者僅為本發明之較佳實施型態,舉凡應用本發明說明書、申請專利範圍或圖式所為之等效變化,仍屬本發明所保護之技術範疇,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 The above is only the preferred embodiment of the present invention, and the equivalent changes of the specification, the patent scope or the drawings of the present invention are still within the technical scope of the present invention, and therefore the scope of protection of the present invention is This is subject to the definition of the scope of the patent application.
100‧‧‧印刷電路板 100‧‧‧Printed circuit board
111‧‧‧絕緣層 111‧‧‧Insulation
112‧‧‧銅箔層 112‧‧‧copper layer
120‧‧‧晶種層 120‧‧‧ seed layer
130‧‧‧電鍍層 130‧‧‧Electroplating
150‧‧‧電路區域 150‧‧‧Circuit area
151‧‧‧電路圖案 151‧‧‧ circuit pattern
160‧‧‧虛擬區域 160‧‧‧virtual area
161‧‧‧虛擬圖案 161‧‧‧virtual pattern
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