TWI518787B - Fabricating method of igzo amorphous oxide semiconductor film and fabricating method of field effect transistor using the method - Google Patents

Fabricating method of igzo amorphous oxide semiconductor film and fabricating method of field effect transistor using the method Download PDF

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TWI518787B
TWI518787B TW100104911A TW100104911A TWI518787B TW I518787 B TWI518787 B TW I518787B TW 100104911 A TW100104911 A TW 100104911A TW 100104911 A TW100104911 A TW 100104911A TW I518787 B TWI518787 B TW I518787B
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TW201135853A (en
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望月文彥
梅田賢一
田中淳
鈴木真之
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富士軟片股份有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous

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Description

IGZO系非晶氧化物半導體膜的製造方法以及使用該方法的場效電晶體的製造方法Method for producing IGZO-based amorphous oxide semiconductor film and method for producing field effect transistor using the same

本發明是有關於一種IGZO(銦鎵鋅氧化物,InGaZnO)系非晶氧化物半導體膜的製造方法以及使用該製造方法的場效電晶體的製造方法。The present invention relates to a method for producing an IGZO (InGaGaN Indium Oxide, InGaZnO)-based amorphous oxide semiconductor film, and a method for producing a field effect transistor using the same.

場效電晶體可用於半導體記憶體用積體電路的單位元件、高頻訊號放大元件、液晶驅動用元件等,特別是經薄膜化的場效電晶體正作為薄膜電晶體(thin-film transistor,TFT)而用於廣泛領域。The field effect transistor can be used as a unit element of a semiconductor memory integrated circuit, a high frequency signal amplifying element, a liquid crystal driving element, etc., in particular, a thinned field effect transistor is being used as a thin film transistor (thin-film transistor, TFT) is used in a wide range of fields.

形成場效電晶體的半導體通道層(活性層)多使用矽半導體或其化合物,需要高速運作的高頻放大元件、積體電路等是使用單晶矽,而在雖然低速運作便足夠,但要求應對顯示器用途等大面積化的液晶驅動裝置用途中是使用非晶矽。The semiconductor channel layer (active layer) forming the field effect transistor mostly uses a germanium semiconductor or a compound thereof, and a high frequency amplifying element, an integrated circuit or the like which requires high speed operation is a single crystal germanium, and although it is sufficient at a low speed, it is required. Amorphous germanium is used for the use of a liquid crystal driving device having a large area such as a display use.

於顯示器領域中,近年來輕量且可彎曲的軟性顯示器(flexible display)備受矚目。上述軟性裝置主要使用可撓性高的樹脂基板,但樹脂基板的耐熱溫度通常為150~200℃,即便耐熱性高的聚醯亞胺系樹脂亦僅為300℃左右,低於玻璃基板等無機基板。於非晶矽的製程中,通常需要超過300℃的高溫加熱處理,因此非晶矽由於耐熱性低,故而難以用於目前顯示器中的軟性基板等支撐基板。In the field of displays, lightweight and flexible flexible displays have attracted attention in recent years. The flexible device mainly uses a resin substrate having high flexibility. However, the heat resistance temperature of the resin substrate is usually 150 to 200 ° C, and the polyimide resin having high heat resistance is only about 300 ° C, which is lower than inorganic materials such as glass substrates. Substrate. In the process of the amorphous germanium, a high-temperature heat treatment of more than 300 ° C is usually required. Therefore, since the amorphous germanium has low heat resistance, it is difficult to be used for a support substrate such as a flexible substrate in the conventional display.

另一方面,日本東京工業大學的細野等人發現In-Ga-Zn-O系(IGZO系)氧化物半導體於室溫下可成膜且即便為非晶態亦可表現出半導體的性能,認為有希望用作下一代顯示器用TFT材料(非專利文獻1、2)。On the other hand, Hirano et al. of the Tokyo Institute of Technology found that an In-Ga-Zn-O-based (IGZO-based) oxide semiconductor can form a film at room temperature and exhibits semiconductor performance even in an amorphous state. It is expected to be used as a TFT material for next-generation displays (Non-Patent Documents 1 and 2).

然而已知:於室溫成膜後未實施退火處理等穩定化處理的IGZO系非晶氧化物半導體雖然可作為TFT的活性層而發揮功能,但其臨界電壓(threshold voltage)容易因驅動時的電性應力(electrical stress)而發生偏移,在元件穩定性方面存在問題。However, it is known that an IGZO-based amorphous oxide semiconductor which is not subjected to a stabilization treatment such as annealing treatment after being formed at room temperature can function as an active layer of a TFT, but the threshold voltage is likely to be driven during driving. There is a problem in electrical stability due to electrical stress.

作為元件穩定性優異的活性層,如非專利文獻3或非專利文獻4等所記載,較佳為成膜後於350℃~400℃下實施退火處理的IGZO系非晶氧化物半導體。專利文獻1的圖4(本說明書的圖7)表明,若於室溫下的真空成膜後,於120℃~250℃下對作為半導體膜的非晶IGZO膜實施退火處理(加熱處理),則載子密度增大,使電阻降至1位數至3位數以上。即,採用樹脂基板的耐熱溫度範圍的退火處理時,難以獲得具有顯示出作為電晶體活性層的良好半導體特性的載子密度(1×1013~1×1016個/cm3)的半導體層。本發明者等人亦確認了上述傾向(參照下述實例圖6)。As an active layer which is excellent in element stability, as described in Non-Patent Document 3 or Non-Patent Document 4, an IGZO-based amorphous oxide semiconductor which is annealed at 350 ° C to 400 ° C after film formation is preferred. FIG. 4 of Patent Document 1 (FIG. 7 of the present specification) shows that an amorphous IGZO film as a semiconductor film is subjected to annealing treatment (heat treatment) at 120 ° C to 250 ° C after vacuum deposition at room temperature. The carrier density is increased to reduce the resistance to 1 digit to more than 3 digits. In other words, in the annealing treatment in the heat resistant temperature range of the resin substrate, it is difficult to obtain a semiconductor layer having a carrier density (1 × 10 13 to 1 × 10 16 /cm 3 ) exhibiting good semiconductor characteristics as the active layer of the transistor. . The inventors of the present invention have also confirmed the above tendency (see Fig. 6 of the following example).

專利文獻2中揭示有具備包含IGZO系非晶氧化物薄膜的半導體層與閘極絕緣膜的電晶體,並揭示有將濺鍍成膜時的濺鍍氣體中的氧氣流量比率設為10%以下而形成半導體膜,並將該氧氣流量比率設為20%以上而形成閘極絕緣膜。然而,專利文獻2中任一膜均為不實施退火處理而直接使用室溫成膜後的膜,認為後續步驟中的加熱處理可能會導致電阻值發生變化,並且如上述般在元件穩定性方面存在問題。Patent Document 2 discloses a transistor including a semiconductor layer including an IGZO-based amorphous oxide film and a gate insulating film, and discloses that an oxygen flow rate ratio in a sputtering gas when sputtering is formed into a film is 10% or less. On the other hand, a semiconductor film is formed, and the oxygen flow rate ratio is set to 20% or more to form a gate insulating film. However, any of the films of Patent Document 2 is a film which is formed by directly forming a film at room temperature without performing an annealing treatment, and it is considered that the heat treatment in the subsequent step may cause a change in the resistance value, and in terms of element stability as described above. There is a problem.

另外,專利文獻3中揭示有:對於具備非晶氧化物膜作為半導體層的場效電晶體,其為了使元件穩定性變得良好,而對電極部以及半導體層添加氫或氘。Further, Patent Document 3 discloses that a field effect transistor including an amorphous oxide film as a semiconductor layer is provided with hydrogen or germanium to the electrode portion and the semiconductor layer in order to improve the element stability.

[先前技術文獻][Previous Technical Literature]

[專利文獻][Patent Literature]

[專利文獻1]日本專利特開2009-99847號公報[Patent Document 1] Japanese Patent Laid-Open Publication No. 2009-99847

[專利文獻2]日本專利特開2007-109918號公報[Patent Document 2] Japanese Patent Laid-Open Publication No. 2007-109918

[專利文獻3]日本專利第4332545號公報[Patent Document 3] Japanese Patent No. 4332545

[非專利文獻][Non-patent literature]

[非專利文獻1]K. Nomura et al,Science,300(2003) 1269.[Non-Patent Document 1] K. Nomura et al, Science, 300 (2003) 1269.

[非專利文獻2]K. Nomura et al,Nature,432(2004) 488[Non-Patent Document 2] K. Nomura et al, Nature, 432 (2004) 488

[非專利文獻3]K. Nomura et al,Applied Physics Letters 93(2008) 192107[Non-Patent Document 3] K. Nomura et al, Applied Physics Letters 93 (2008) 192107

[非專利文獻4]D. Kang et al,Applied Physics Letters 90(2008) 192101[Non-Patent Document 4] D. Kang et al, Applied Physics Letters 90 (2008) 192101

然而,由於氫或氘的導入需要新的設備以及製程,所以在製程的簡便性以及成本方面存在問題。However, since the introduction of hydrogen or helium requires new equipment and processes, there are problems in terms of process simplicity and cost.

本發明是鑒於上述情況研究而成者,其目的在於提供:一種IGZO系非晶氧化物半導體膜的製造方法,其是可在樹脂基板上製造的IGZO系非晶氧化物半導體膜的製造方法,其藉由簡便且低成本的製程,而製造具有適合作為TFT的活性層的載子密度且對電性應力以及熱的穩定性良好的IGZO系非晶氧化物半導體膜;以及使用該方法製造元件穩定性優異的IGZO系場效電晶體的方法。The present invention has been made in view of the above circumstances, and an object of the invention is to provide a method for producing an IGZO-based amorphous oxide semiconductor film, which is a method for producing an IGZO-based amorphous oxide semiconductor film which can be produced on a resin substrate. An IGZO-based amorphous oxide semiconductor film having a carrier density suitable as an active layer of a TFT and having good electrical stress and heat stability by a simple and low-cost process; and manufacturing of the device using the method A method of IGZO-based field effect transistor having excellent stability.

本發明者發現:在基板上將IGZO系非晶氧化物薄膜濺鍍成膜時,藉由優化濺鍍成膜時的背壓與濺鍍成膜後的退火處理溫度,可製造具有任意電阻值且熱穩定性良好的IGZO系非晶氧化物絕緣體薄膜。The present inventors have found that when an IGZO-based amorphous oxide film is sputter-deposited on a substrate, it is possible to manufacture an arbitrary resistance value by optimizing the back pressure at the time of sputtering film formation and the annealing treatment temperature after sputtering deposition. An IGZO-based amorphous oxide insulator film having good thermal stability.

進而,本發明者基於上述見解發現一種簡便且低成本地製造可在樹脂基板上製造,具有適合作為TFT的活性層的載子密度,且對電性應力以及熱的穩定性良好的IGZO系非晶氧化物半導體膜的方法。Further, based on the above findings, the inventors have found that a simple and low-cost production of an IGZO system which can be produced on a resin substrate and has a carrier density suitable as an active layer of a TFT and which is excellent in electrical stress and heat stability. A method of crystal oxide semiconductor film.

即,本發明提供一種IGZO系非晶氧化物半導體膜的製造方法,其是藉由將IGZO系非晶氧化物層濺鍍成膜後實施退火處理而製造包含IGZO系非晶氧化物的半導體膜的方法,其特徵在於:於滿足下述式(1)以及(2)的條件下成膜。在本發明的IGZO系非晶氧化物半導體膜的製造方法中,較佳為進而於滿足下述式(3)的條件下成膜。In other words, the present invention provides a method for producing an IGZO-based amorphous oxide semiconductor film by sputtering an IGZO-based amorphous oxide layer into a film and then performing annealing treatment to produce a semiconductor film containing an IGZO-based amorphous oxide. The method is characterized in that a film is formed under the conditions satisfying the following formulas (1) and (2). In the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention, it is preferred to form a film under conditions satisfying the following formula (3).

1×10-5≦P(Pa)≦5×10-4 (1)、1×10 -5 ≦P(Pa)≦5×10 -4 (1),

100≦T(℃)≦300 (2)、100≦T(°C)≦300 (2),

2×10-5≦P(Pa)≦1×10-4 (3)2×10 -5 ≦P(Pa)≦1×10 -4 (3)

(式中,P為上述濺鍍成膜中的背壓,T為上述退火處理中的退火溫度)(wherein P is the back pressure in the above-described sputtering film formation, and T is the annealing temperature in the above annealing treatment)

此處,所謂「濺鍍成膜中的背壓」,是濺鍍成膜時設置有基板的真空容器(成膜裝置)內的極限真空度,是指成膜開始前、即向成膜裝置中導入成膜氣體前的成膜裝置內的真空度。Here, the "back pressure in the sputtering film formation" is the ultimate vacuum in the vacuum container (film forming apparatus) in which the substrate is provided during the sputtering film formation, and means the film forming apparatus before the film formation starts. The degree of vacuum in the film forming apparatus before introducing the film forming gas.

於本說明書中,極限真空度(背壓)是讀取設置於濺鍍成膜裝置中的離子真空計(ion gauge)的值。成膜裝置內的極限真空度(背壓)大致等同於成膜裝置內的含水量(水分壓),因而亦可採用由使用質量分析計(例如ULVAC公司的Qulee CGM系列等)測得的水分壓所求得的值。In the present specification, the ultimate vacuum (back pressure) is a value for reading an ion gauge provided in a sputtering film forming apparatus. The ultimate vacuum (back pressure) in the film forming apparatus is roughly equivalent to the water content (water pressure) in the film forming apparatus, and thus the moisture measured by using a mass spectrometer (for example, ULVAC company's Qulee CGM series, etc.) can also be used. Press the value obtained.

於本說明書中,所謂IGZO系非晶氧化物薄膜,是指包含In、Ga的非晶氧化物薄膜,較佳為更包含Zn的非晶氧化物薄膜。除此等金屬元素以外,亦可包含摻雜劑或取代元素等其他元素。In the present specification, the IGZO-based amorphous oxide film refers to an amorphous oxide film containing In and Ga, and preferably an amorphous oxide film further containing Zn. In addition to these metal elements, other elements such as dopants or substitution elements may be contained.

於本說明書中,所謂退火處理,不僅包括濺鍍成膜後的退火處理,還包括加熱經濺鍍成膜的薄膜的全部處理,例如包括光微影等圖案化步驟、或所積層的膜的成膜步驟中的加熱處理等。In the present specification, the annealing treatment includes not only the annealing treatment after the sputtering film formation but also the entire processing of heating the film which is sputter-deposited, for example, a patterning step including photolithography or a film of the laminated layer. Heat treatment or the like in the film forming step.

於本說明書中,「導體」是指電阻率為100 Ω‧cm以下者。In the present specification, "conductor" means a resistivity of 100 Ω‧cm or less.

另外,「半導體」是指電阻率在103~106 Ω‧cm範圍內者。另外,「絕緣體」是指電阻率為107 Ω‧cm以上者。In addition, "semiconductor" means a resistivity in the range of 10 3 to 10 6 Ω ‧ cm. In addition, "insulator" means a resistivity of 10 7 Ω ‧ cm or more.

上述退火溫度較佳為150℃以上、250℃以下。The annealing temperature is preferably 150 ° C or higher and 250 ° C or lower.

本發明的IGZO系非晶氧化物半導體膜的製造方法較佳為:於滿足下述式(4)以及(5)的條件下,或滿足(6)以及(7)的條件下,或滿足(8)以及(9)的條件下,或者滿足(10)以及(11)的條件下成膜。The method for producing an IGZO-based amorphous oxide semiconductor film of the present invention preferably satisfies the conditions of the following formulas (4) and (5), or satisfies the conditions of (6) and (7), or satisfies ( Film formation under conditions of 8) and (9) or under the conditions of (10) and (11).

P(Pa)=2×10-5 (4)、P(Pa)=2×10 -5 (4),

200≦T(℃)≦300 (5)、200≦T(°C)≦300 (5),

P(Pa)=5×10-5 (6)、P(Pa)=5×10 -5 (6),

120≦T(℃)≦270 (7)、120≦T(°C)≦270 (7),

P(Pa)=6.5×10-5 (8)、P(Pa)=6.5×10 -5 (8),

100≦T(℃)≦240 (9)、100≦T(°C)≦240 (9),

P(Pa)=1×10-4 (10)、P(Pa)=1×10 -4 (10),

100≦T(℃)≦195 (11)100≦T(°C)≦195 (11)

此外,上述式(4)、(6)、(8)、(10)的背壓P的值具±10%的幅度。Further, the values of the back pressure P of the above formulas (4), (6), (8), and (10) have a magnitude of ±10%.

於本發明的IGZO系非晶氧化物半導體膜的製造方法中,上述濺鍍成膜的成膜壓力較佳為10 Pa以下。In the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention, the film formation pressure of the sputtering film formation is preferably 10 Pa or less.

另外,較佳為將上述濺鍍成膜的成膜氣體設為含有Ar與O2的氣體,將該成膜氣體中的Ar與O2的流量比例設為O2/Ar≦1/15。Further, it is preferable that the film forming gas to be sputtered into a film is a gas containing Ar and O 2 , and the flow rate ratio of Ar to O 2 in the film forming gas is set to O 2 /Ar≦1/15.

本發明提供一種場效電晶體的製造方法,其是於基板上具備包含IGZO系非晶氧化物的半導體層、源電極、汲電極、閘電極以及閘極絕緣膜而成的薄膜電晶體的製造方法,其特徵在於:藉由上述本發明的IGZO系非晶氧化物半導體膜的製造方法而形成上述半導體層。The present invention provides a method for producing a field effect transistor, which is characterized in that a thin film transistor including a semiconductor layer including an IGZO-based amorphous oxide, a source electrode, a germanium electrode, a gate electrode, and a gate insulating film is provided on a substrate. The method of forming the semiconductor layer by the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention.

於本發明的場效電晶體的製造方法中,較佳為使用可撓性基板作為上述基板。In the method for producing a field effect transistor of the present invention, it is preferred to use a flexible substrate as the substrate.

於日本專利特開2007-73697號公報中記載有:藉由於成膜時的環境氣體中以5.0×105 Pa~10 Pa的分壓含有水,可穩定地製造常關型TFT。然而本發明者確認:於上述水分壓範圍內形成的IGZO系氧化物薄膜若實施樹脂基板的耐熱溫度以下的退火處理,則其電阻值根據成膜時的水分壓的差異而不同,由於此電阻值範圍遍及絕緣體區域至導體區域,故而於上述水分壓下無法穩定地製造TFT。詳細情況見下文。In the ambient gas at the time of film formation, water is contained in a partial pressure of 5.0 × 10 5 Pa to 10 Pa, and it is described that the normally-off type TFT can be stably produced. However, the inventors of the present invention have confirmed that the IGZO-based oxide thin film formed in the above-described water-pressure range is subjected to annealing treatment at a temperature lower than the heat-resistant temperature of the resin substrate, and the electric resistance value varies depending on the difference in water-pressure at the time of film formation. Since the value range extends from the insulator region to the conductor region, the TFT cannot be stably produced under the above-described water pressure. See below for details.

於日本專利特開2007-73697號公報中雖然未記載退火處理,但實質上本發明者針對藉由日本專利特開2007-73697號公報所記載的背壓(通常的高真空)以及水分壓而獲得的活性層追加進行了TFT運作特性的試驗,結果未能確認作為TFT的運作,鑒於上述情況可認為日本專利特開2007-73697號公報中是在400℃以上的溫度下實施退火處理。In the case of the back pressure (normal high vacuum) and the water pressure described in Japanese Laid-Open Patent Publication No. 2007-73697, the inventors of the present invention have not described the annealing process. In the obtained active layer, the test of the operating characteristics of the TFT was carried out, and as a result, the operation of the TFT was not confirmed. In view of the above, it is considered that the annealing treatment is performed at a temperature of 400 ° C or higher in Japanese Patent Laid-Open Publication No. 2007-73697.

因此,本發明首次能夠製造藉由在樹脂基板的耐熱溫度以下的溫度進行退火處理而獲得穩定化,具有1×1013~1×1016個/cm3的載子密度,且適合作為TFT的活性層的IGZO系非晶氧化物半導體膜。根據本發明,僅藉由對應於其後的退火處理溫度(樹脂基板的耐熱溫度以下)將濺鍍成膜的背壓控制在1×10-5以上5×10-4以下的範圍內的簡便方法,而無需新設備投入等,便可簡便且低成本地製造IGZO系非晶氧化物半導體膜。Therefore, the present invention can be stabilized for the first time by annealing at a temperature lower than the heat resistant temperature of the resin substrate, has a carrier density of 1 × 10 13 to 1 × 10 16 /cm 3 , and is suitable as a TFT. An IGZO-based amorphous oxide semiconductor film of an active layer. According to the present invention, it is easy to control the back pressure of the sputtering film formation in the range of 1 × 10 -5 or more and 5 × 10 -4 or less only by the annealing treatment temperature (below the heat-resistant temperature of the resin substrate). In the method, the IGZO-based amorphous oxide semiconductor film can be easily and inexpensively manufactured without requiring a new device or the like.

本發明是藉由1×10-5以上、5×10-4以下的背壓將IGZO系非晶氧化物層濺鍍成膜後,在100℃以上、300℃以下的溫度下進行退火處理,而製造包含IGZO系非晶氧化物的半導體膜。根據該方法,可在樹脂基板的耐熱溫度以下的溫度下簡便且低成本地製造具有適合作為TFT的活性層的載子密度且對電性應力以及熱的穩定性良好的IGZO系非晶氧化物半導體膜。In the present invention, the IGZO-based amorphous oxide layer is sputter-deposited by a back pressure of 1 × 10 -5 or more and 5 × 10 -4 or less, and then annealed at a temperature of 100 ° C or more and 300 ° C or less. A semiconductor film containing an IGZO-based amorphous oxide was produced. According to this method, it is possible to easily and inexpensively produce an IGZO-based amorphous oxide having a carrier density suitable as an active layer of a TFT and having good electrical stress and heat stability at a temperature lower than the heat-resistant temperature of the resin substrate. Semiconductor film.

因此,於IGZO系場效電晶體的製造方法中,藉由利用本發明的IGZO系非晶氧化物半導體膜的製造方法製造活性層(半導體層),可憑藉簡便的製程低成本地製造具備對電性應力以及熱的穩定性良好的IGZO系非晶氧化物絕緣層且元件穩定性優異的IGZO系場效電晶體。Therefore, in the method for producing an IGZO-based field effect transistor, the active layer (semiconductor layer) can be produced by the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention, and it can be manufactured at a low cost by a simple process. An IGZO-based field effect transistor having an IGZO-based amorphous oxide insulating layer having excellent electrical stress and thermal stability and excellent element stability.

「IGZO系非晶氧化物半導體膜的製造方法」"Method for producing IGZO amorphous oxide semiconductor film"

本發明者對製造對電性應力或熱的穩定性良好的IGZO系非晶氧化物薄膜的方法進行潛心研究。結果發現:所形成的IGZO系非晶氧化物薄膜的電阻值根據成膜裝置內的含水量而改變,進而電阻值根據濺鍍成膜後的退火處理溫度而改變,即藉由優化成膜裝置內的含水量與濺鍍成膜後的退火處理溫度的組合,可製造出具有導體區域至絕緣體區域範圍內的任意電阻值且對電性應力以及熱的穩定性良好的IGZO系非晶氧化物薄膜(參照下述實例1、圖4)。The present inventors conducted intensive studies on a method of producing an IGZO-based amorphous oxide film having good electrical stress or heat stability. As a result, it was found that the resistance value of the formed IGZO-based amorphous oxide film changes depending on the water content in the film forming apparatus, and the resistance value changes depending on the annealing treatment temperature after the sputtering film formation, that is, by optimizing the film forming apparatus. The combination of the water content in the inside and the annealing treatment temperature after the sputtering film formation can produce an IGZO-based amorphous oxide having an arbitrary resistance value in the range from the conductor region to the insulator region and having good electrical stress and heat stability. Film (refer to Example 1, Figure 4 below).

於本說明書中,「導體」是指電阻率為100 Ω‧cm以下者。In the present specification, "conductor" means a resistivity of 100 Ω‧cm or less.

另外,「半導體」是指電阻率為103~106Ω‧cm範圍內者。另外,於本說明書中,「絕緣體」是指電阻率為107 Ω‧cm以上者。In addition, "semiconductor" means a resistivity of 10 3 to 10 6 Ω ‧ cm. In addition, in the present specification, the term "insulator" means a resistivity of 10 7 Ω ‧ cm or more.

已知於濺鍍成膜中成膜裝置內的含水量(水分壓)與濺鍍成膜的背壓相關,已知背壓越低即越為高真空,水分壓越低。本發明者改變濺鍍成膜時的背壓,藉由FT-IR(fourier transform infrared radiation,傅立葉轉換紅外線光譜)測定來分析所形成的電阻值不同的各IGZO系非晶氧化物薄膜實施的組成,結果確認:於各非晶氧化物薄膜中,OH基的波峰面積不同,若提高背壓,則OH基的量增加,即含水量增加(參照下述實例、圖5)。It is known that the water content (water pressure) in the film formation apparatus in the sputtering film formation is related to the back pressure of the sputtering film formation, and it is known that the lower the back pressure, the higher the vacuum, and the lower the water pressure. The present inventors changed the back pressure at the time of sputtering film formation, and analyzed the composition of each IGZO-based amorphous oxide film having different resistance values by FT-IR (fourier transform infrared spectroscopy) measurement. As a result, it was confirmed that the peak area of the OH group differs in each of the amorphous oxide films, and when the back pressure is increased, the amount of the OH group increases, that is, the water content increases (see the following example, FIG. 5).

圖1是表示改變背壓(成膜裝置內的極限真空度)時成膜裝置內的含水量與所形成的IGZO系非晶氧化物薄膜內的含水量的關係的示意圖。如圖所示,背壓越高,成膜裝置內的含水量越多。因此,可認為滲入膜中的水分增多會對薄膜的電阻值產生影響。FIG. 1 is a schematic view showing the relationship between the water content in the film forming apparatus and the water content in the formed IGZO-based amorphous oxide film when the back pressure (the ultimate vacuum degree in the film forming apparatus) is changed. As shown, the higher the back pressure, the greater the water content in the film forming apparatus. Therefore, it is considered that an increase in the amount of moisture permeating into the film affects the resistance value of the film.

由圖1以及下述實例的圖5可確認:剛濺鍍成膜後的IGZO系非晶氧化物薄膜中的含水量(OH基量)根據濺鍍成膜時的背壓而變化。並且,圖4顯示,根據濺鍍成膜時的背壓的差異與濺鍍成膜後的退火溫度,可製造出具有導體區域至絕緣體區域的區域中的各種電阻值的IGZO系非晶氧化物薄膜。From FIG. 1 and FIG. 5 of the following example, it was confirmed that the water content (the amount of OH groups) in the IGZO-based amorphous oxide film immediately after the sputtering film formation changes depending on the back pressure at the time of sputtering film formation. Further, FIG. 4 shows that an IGZO-based amorphous oxide having various resistance values in a region from a conductor region to an insulator region can be produced according to the difference in back pressure at the time of sputtering film formation and the annealing temperature after sputtering deposition. film.

成膜裝置內的含水量的控制方法並不限定於藉由上述濺鍍成膜中的背壓來控制,例如亦可藉由於成膜過程中直接導入水分的方法等來加以控制。如「解決問題之技術手段」項所述,背壓為導入成膜氣體前的成膜裝置內的真空度,是可容易地變更設定的因素,因此較佳為藉由背壓控制氧化物薄膜中的含水量。以下,舉例說明控制背壓而控制含水量的方法。The method of controlling the water content in the film forming apparatus is not limited to being controlled by the back pressure in the sputtering film formation, and may be controlled, for example, by a method of directly introducing moisture during film formation. As described in the "Technical means for solving the problem", the back pressure is a factor that can be easily changed in the degree of vacuum in the film forming apparatus before the film forming gas is introduced. Therefore, it is preferable to control the oxide film by back pressure. The water content in the water. Hereinafter, a method of controlling the back pressure to control the water content will be exemplified.

圖4顯示,對於未實施退火處理狀態的剛濺鍍成膜後的IGZO系非晶氧化物薄膜,亦可形成根據背壓的差異而具有不同電阻值的IGZO系非晶氧化物薄膜,但是如「先前技術」項所述,未實施任何穩定化處理僅實施濺鍍成膜的絕緣膜在對電性應力或熱的穩定性方面存在問題。因此,於本發明的IGZO系非晶氧化物半導體膜的製造方法中,是在濺鍍成膜後實施退火處理作為穩定化處理。4 shows that an IGZO-based amorphous oxide film having a different resistance value depending on the difference in back pressure can be formed for the IGZO-based amorphous oxide film which has not been subjected to the annealing treatment. As described in the "Prior Art", the insulating film which is not subjected to any stabilization treatment and is only subjected to sputtering film formation has problems in terms of stability against electrical stress or heat. Therefore, in the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention, an annealing treatment is performed as a stabilization treatment after sputtering and film formation.

即,本發明的IGZO系非晶氧化物半導體膜的製造方法是在1×10-5以上、5×10-4以下的背壓下將IGZO系非晶氧化物層濺鍍成膜後,在100℃以上、300℃以下的溫度下進行退火處理。In the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention, the IGZO-based amorphous oxide layer is sputter-deposited under a back pressure of 1 × 10 -5 or more and 5 × 10 -4 or less, and then The annealing treatment is performed at a temperature of 100 ° C or more and 300 ° C or less.

退火處理的方法並無特別限定,因為常壓下的退火便足夠,所以較容易的方法是使用加熱板等進行加熱處理。除此以外,亦可使用潔淨烘箱或真空腔室。The annealing treatment method is not particularly limited, and annealing at normal pressure is sufficient, so that it is easy to heat-treat using a hot plate or the like. In addition to this, a clean oven or a vacuum chamber can also be used.

如上所述,於本發明的IGZO系非晶氧化物半導體膜的製造方法中,在濺鍍成膜時僅改變其背壓,成膜裝置內的含水量在使用任一濺鍍成膜方法時均根據背壓而改變。因此,於本發明的IGZO系非晶氧化物半導體膜的製造方法中,濺鍍成膜的方法並無特別限定,可應用任意方法。As described above, in the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention, only the back pressure is changed at the time of sputtering, and the water content in the film forming apparatus is used when any of the sputtering film forming methods is used. Both change according to back pressure. Therefore, in the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention, the method of sputtering the film formation is not particularly limited, and any method can be applied.

作為濺鍍成膜方法,例如可舉出:二極濺鍍法、三極濺鍍法、直流濺鍍法、高頻濺鍍法(radio frequency sputtering)、電子迴旋共振離子束濺鍍法(electron coupling resonance sputtering)、磁控濺鍍法(magnetron sputtering)、對向靶濺鍍法(facing target sputtering)、脈衝濺鍍法、以及離子束濺鍍法等。Examples of the sputtering film formation method include a two-pole sputtering method, a three-pole sputtering method, a DC sputtering method, a radio frequency sputtering method, and an electron cyclotron resonance ion beam sputtering method (electron). Coupling resonance sputtering, magnetron sputtering, facing target sputtering, pulse sputtering, and ion beam sputtering.

另外,進行成膜的基板並無特別限定,於本實施形態中,基板並無特別限定,只要根據用途適當選擇Si基板、玻璃基板、各種軟性基板等即可。本發明的IGZO系非晶氧化物絕緣膜的製造方法可藉由300℃以下的低溫製程而實施,因此耐熱性低的樹脂基板亦適用。因此,本發明的IGZO系非晶氧化物半導體膜的製造方法亦可應用於軟性顯示器等所使用的薄膜電晶體(TFT,thin-film transistor)的製造。In addition, the substrate to be formed is not particularly limited. In the present embodiment, the substrate is not particularly limited, and a Si substrate, a glass substrate, various flexible substrates, and the like may be appropriately selected depending on the application. The method for producing an IGZO-based amorphous oxide insulating film of the present invention can be carried out by a low-temperature process of 300 ° C or lower. Therefore, a resin substrate having low heat resistance is also applicable. Therefore, the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention can also be applied to the production of a thin film transistor (TFT) used for a flexible display or the like.

作為軟性基板,可舉出:聚乙烯醇系樹脂、聚碳酸酯衍生物(帝人(股):WRF)、纖維素衍生物(纖維素三乙酸酯、纖維素二乙酸酯)、聚烯烴系樹脂(Nippon Zeon(股):ZEONOR、ZEONEX)、聚碸系樹脂(聚醚碸、聚碸)、降冰片烯系樹脂(JSR(股):ARTON)、聚酯系樹脂(PET(聚對苯二甲酸乙二酯,polyethylene terephthalate)、PEN(聚萘二甲酸乙二酯,polyethylene naphthalene)、交聯反丁烯二酸二酯)、聚醯亞胺系樹脂、聚醯胺系樹脂、聚醯胺醯亞胺系樹脂、聚芳酯系樹脂、丙烯酸系樹脂、環氧系樹脂、環硫系樹脂、氟系樹脂、聚矽氧系樹脂膜、聚苯并唑系樹脂、氰酸酯系樹脂、芳香族醚系樹脂(聚醚酮)、順丁烯二醯亞胺-烯烴系樹脂等的樹脂基板、液晶聚合物基板;另外,於此等樹脂基板中含有氧化矽粒子、金屬奈米粒子、無機氧化物奈米粒子、無機氮化物奈米粒子、金屬系/無機系奈米纖維或微纖維、碳纖維、碳奈米管、玻璃碎片、玻璃纖維、玻璃珠、黏土礦物、雲母衍生結晶構造的複合樹脂基板;以及於薄玻璃與上述單獨有機材料之間至少具有1個接合界面的積層塑膠材料、藉由將無機層(ex.SiO2、Al2O3、SiOxNy)與有機層(上述)交替積層而至少具有1個以上接合界面的具有阻隔性能的複合材料;不鏽鋼基板、將不鏽鋼與不同種金屬積層而成的金屬多層基板、鋁基板、或藉由對表面實施氧化處理(例如陽極氧化處理)而提昇表面的絕緣性的附有氧化被膜的鋁基板等。Examples of the flexible substrate include a polyvinyl alcohol-based resin, a polycarbonate derivative (Teijin: WRF), a cellulose derivative (cellulose triacetate, cellulose diacetate), and a polyolefin. Resin (Nippon Zeon: ZEONOR, ZEONEX), polyfluorene-based resin (polyether oxime, polyfluorene), norbornene-based resin (JSR (stock): ARTON), polyester resin (PET (poly) Ethylene terephthalate, PEN (polyethylene naphthalene), cross-linked fumaric acid diester, polyimide resin, polyamine resin, poly Amidoxime resin, polyarylate resin, acrylic resin, epoxy resin, episulfide resin, fluorine resin, polyoxyn resin film, polybenzoxazole resin, cyanate ester system a resin substrate such as a resin, an aromatic ether resin (polyether ketone) or a maleimide-olefin resin, or a liquid crystal polymer substrate; and the resin substrate contains cerium oxide particles or a metal nanoparticle. Particles, inorganic oxide nanoparticles, inorganic nitride nanoparticles, metal/inorganic nanofibers a composite resin substrate of microfibers, carbon fibers, carbon nanotubes, glass cullet, glass fiber, glass beads, clay mineral, mica-derived crystal structure; and a laminate having at least one joint interface between the thin glass and the above-mentioned individual organic material a plastic material, a composite material having barrier properties having at least one bonding interface by alternately laminating inorganic layers (ex. SiO 2 , Al 2 O 3 , SiO x N y ) and an organic layer (described above); stainless steel substrate A metal multilayer substrate in which stainless steel is laminated with different kinds of metals, an aluminum substrate, or an aluminum substrate with an oxide film which is provided with an oxidation treatment (for example, anodizing treatment) to enhance the surface insulation property.

作為IGZO系非晶氧化物的一例,可舉出下述通式(P1)所表示的InGaZnO4(IGZO)等同系化合物。An example of the IGZO-based amorphous oxide is an InGaZnO 4 (IGZO) equivalent compound represented by the following formula (P1).

(ln2-xGax)O3‧(ZnO)m (P1) (ln 2-x Ga x) O 3 ‧ (ZnO) m (P1)

(式中0≦x≦2且m為自然數)(where 0≦x≦2 and m is a natural number)

成膜時的成膜壓力並無特別限定,但若成膜壓力過高,則成膜速度下降,生產性變差,因此較佳為10 Pa以下,更佳為5 Pa以下,更佳為1 Pa以下。The film formation pressure at the time of film formation is not particularly limited. However, if the film formation pressure is too high, the film formation rate is lowered and the productivity is deteriorated. Therefore, the film formation pressure is preferably 10 Pa or less, more preferably 5 Pa or less, and still more preferably 1 Pa below.

濺鍍成膜時的成膜氣體並無特別限定,可舉出包含Ar與O2者。The film forming gas at the time of sputtering film formation is not particularly limited, and examples thereof include Ar and O 2 .

如「先前技術」項所述,濺鍍形成的膜的電阻值根據上述成膜氣體中的Ar與O2的流量比而改變,於本發明的成膜方法中,不僅可改變背壓來控制電阻值,亦可改變成膜氣體的流量比來控制電阻值,但是有提高氧氣分壓而導致成膜速度下降的傾向,如下述比較例1的圖6所示,亦存在於某些背壓以及退火處理溫度下,成膜時的氧氣分壓幾乎不對電阻值產生影響的情況。本發明可藉由僅優化背壓與退火處理溫度而製造出具有絕緣體區域的電阻值的IGZO系非晶氧化物薄膜,因此氧氣分壓O2/Ar較佳為設為1/15以下的固定值。As described in the "Prior Art", the resistance value of the film formed by sputtering changes according to the flow ratio of Ar to O 2 in the film forming gas, and in the film forming method of the present invention, not only the back pressure can be changed to control The resistance value may also change the flow ratio of the film forming gas to control the resistance value, but there is a tendency to increase the partial pressure of oxygen to cause a decrease in the film forming speed, as shown in Fig. 6 of Comparative Example 1 below, and also in some back pressure. At the annealing treatment temperature, the partial pressure of oxygen at the time of film formation hardly affects the resistance value. According to the present invention, the IGZO-based amorphous oxide film having the electric resistance value of the insulator region can be produced by optimizing only the back pressure and the annealing treatment temperature. Therefore, the oxygen partial pressure O 2 /Ar is preferably set to be 1/15 or less. value.

本發明者確認電阻值與載子密度相關(圖2)。通常,可獲得良好的開關特性的電晶體的活性層的載子密度為1×1013~1×1016個/cm3,因此可獲得良好的開關特性的半導體區域的電阻值是圖2的虛線框內的電阻值範圍(103~106Ω‧cm的範圍)內的值。因此,藉由設為上述背壓條件以及退火處理溫度範圍,可製造出膜面內的載子密度的均勻性高,開關特性良好,可靠性優異的IGZO系非晶氧化物半導體膜。The inventors confirmed that the resistance value is related to the carrier density (Fig. 2). In general, the active layer of a transistor which can obtain good switching characteristics has a carrier density of 1 × 10 13 to 1 × 10 16 /cm 3 , so that the resistance value of the semiconductor region in which good switching characteristics can be obtained is the value of FIG. The value in the range of resistance values in the dotted line frame (range of 10 3 to 10 6 Ω‧cm). Therefore, by setting the above-described back pressure conditions and the annealing treatment temperature range, it is possible to produce an IGZO-based amorphous oxide semiconductor film having high uniformity of carrier density in the film surface, excellent switching characteristics, and excellent reliability.

於下述實例1中,於成膜壓力0.8 Pa、輸入電力DC 50 W、Ar:30 sccm、O2:0.25 sccm的條件下,改變背壓以及退火處理溫度而製造顯示各種電阻值的IGZO系非晶氧化物薄膜。如圖4所示,於背壓較高的範圍、較低的範圍、以及其中間區域,電阻值(電阻率)相對於退火處理溫度而變化方式不同。In the following Example 1, an IGZO system exhibiting various resistance values was produced under conditions of a film formation pressure of 0.8 Pa, an input power of DC 50 W, Ar: 30 sccm, and O 2 : 0.25 sccm by changing the back pressure and the annealing treatment temperature. Amorphous oxide film. As shown in FIG. 4, in a range in which the back pressure is high, a lower range, and a middle portion thereof, the resistance value (resistivity) varies depending on the annealing treatment temperature.

在圖4的■、□、◆、△的線圖(背壓1×10-4 Pa、6.5×10-5 Pa、5×10-5 Pa、2×10-5 Pa)中,藉由提昇退火溫度,電阻值在300℃以下的區域持續增大。另外,關於◆的線圖,於150℃~250℃的退火處理溫度範圍,斜率變得非常平緩並成為表示104~105 Ω‧cm範圍內的大致固定值的形狀。In the line diagram of ■, □, ◆, △ of Fig. 4 (back pressure 1 × 10 -4 Pa, 6.5 × 10 -5 Pa, 5 × 10 -5 Pa, 2 × 10 -5 Pa), by lifting The annealing temperature and the resistance value continue to increase in the region below 300 °C. Further, regarding the graph of ◆, in the annealing treatment temperature range of 150 ° C to 250 ° C, the slope becomes very gentle and becomes a shape having a substantially constant value in the range of 10 4 to 10 5 Ω ‧ cm.

圖4顯示,藉由在背壓1×10-5 Pa以上、5×10-4 Pa以下,退火處理溫度100℃~300℃的範圍,選擇適宜的背壓與退火處理溫度的組合,可製造出可獲得電阻值103~106 Ω‧cm範圍內的良好開關特性的半導體膜。4 shows that by selecting a suitable combination of back pressure and annealing temperature at a back pressure of 1×10 −5 Pa or more and 5×10 −4 Pa or less, and an annealing treatment temperature of 100° C. to 300° C. A semiconductor film having good switching characteristics in a range of resistance values of 10 3 to 10 6 Ω ‧ cm can be obtained.

另外顯示,當將背壓設為5×10-5 Pa時,於150℃~250℃的退火處理溫度範圍內,退火處理溫度的面內均勻性對電阻值造成的影響較小,並可減小退火處理中的薄膜的膜面內的溫度分佈等對膜面內的電阻值的均勻性產生的影響。In addition, when the back pressure is set to 5×10 -5 Pa, the in-plane uniformity of the annealing treatment temperature has less influence on the resistance value in the annealing treatment temperature range of 150 ° C to 250 ° C, and can be reduced. The influence of the temperature distribution in the film surface of the film in the small annealing treatment on the uniformity of the resistance value in the film surface.

進而圖4顯示,若將退火處理溫度設為400℃以上,則無論濺鍍成膜時的背壓如何,均可製造出具有可獲得良好開關特性的半導體區域的電阻值,膜面內的載子密度的均勻性高,可靠性優異的IGZO系非晶氧化物薄膜。Further, in Fig. 4, when the annealing treatment temperature is 400 ° C or higher, the resistance value of the semiconductor region having good switching characteristics can be produced regardless of the back pressure at the time of sputtering film formation, and the film surface can be loaded. An IGZO-based amorphous oxide film having high sub-density uniformity and excellent reliability.

如圖4所示,並非在滿足下述式(1)以及(2)、或(3)以及(2)的全部範圍內均可獲得具有電阻值103~106 Ω‧cm範圍內的良好開關特性的半導體膜。圖4顯示如下傾向:於滿足下述式(1)的範圍內背壓越低(越接近高真空),可製造可獲得良好開關特性的半導體膜的退火溫度於滿足下述式(2)的範圍內變得越高。As shown in FIG. 4, it is not preferable to obtain a resistance value in the range of 10 3 to 10 6 Ω ‧cm in all the ranges satisfying the following formulas (1) and (2), or (3) and (2) A semiconductor film with switching characteristics. 4 shows a tendency that the annealing temperature at which the semiconductor film which can obtain good switching characteristics can be manufactured to satisfy the following formula (2), the lower the back pressure (close to the high vacuum) in the range satisfying the following formula (1) The higher the range becomes.

例如,作為可形成上述半導體膜的條件,可舉出滿足下述式(4)以及(5)的條件、或滿足(6)以及(7)的條件、或滿足(8)以及(9)的條件、或者滿足(10)以及(11)的條件(P為上述背壓,T為上述退火處理的溫度)。此外,下述式(4)、(6)、(8)、(10)的背壓P的值具有±10%的幅度。For example, as conditions for forming the semiconductor film, conditions satisfying the following formulas (4) and (5), conditions satisfying (6) and (7), or (8) and (9) are satisfied. The conditions or the conditions of (10) and (11) are satisfied (P is the above-mentioned back pressure, and T is the temperature of the above annealing treatment). Further, the values of the back pressure P of the following formulas (4), (6), (8), and (10) have an amplitude of ±10%.

即便於下述式(4)~(11)所表示的範圍外,只要調查滿足下述式(1)的任意背壓下的滿足式(2)的退火溫度與電阻值的關係,所發現的背壓與退火溫度的組合亦可製造出可獲得良好開關特性的半導體膜。In other words, it is found that it is easy to investigate the relationship between the annealing temperature and the resistance value satisfying the formula (2) at any back pressure satisfying the following formula (1), except for the range represented by the following formulas (4) to (11). The combination of back pressure and annealing temperature can also produce a semiconductor film that can achieve good switching characteristics.

P(Pa)=2×10-5 (4)、P(Pa)=2×10 -5 (4),

200≦T(℃)≦300 (5)、200≦T(°C)≦300 (5),

P(Pa)=5×10-5 (6)、P(Pa)=5×10 -5 (6),

120≦T(℃)≦270 (7)、120≦T(°C)≦270 (7),

P(Pa)=6.5×10-5 (8)、P(Pa)=6.5×10 -5 (8),

100≦T(℃)≦240 (9)、100≦T(°C)≦240 (9),

P(Pa)=1×10-4 (10)、P(Pa)=1×10 -4 (10),

100≦T(℃)≦195 (11)100≦T(°C)≦195 (11)

另外,於上述本發明的IGZO系非晶氧化物半導體膜的製造方法中,退火處理溫度為100℃~300℃。因此,本發明的IGZO系非晶氧化物半導體膜的製造方法在樹脂基板等耐熱性低的可撓性基板上亦適用。Further, in the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention, the annealing treatment temperature is 100 to 300 °C. Therefore, the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention is also applicable to a flexible substrate having low heat resistance such as a resin substrate.

如上所述,根據本發明的IGZO系非晶氧化物絕緣膜的製造方法,可在樹脂基板的耐熱溫度以下的溫度下簡便且低成本地製造具有適合作為TFT的活性層的載子密度且對電性應力以及熱的穩定性良好的IGZO系非晶氧化物半導體膜。As described above, according to the method for producing an IGZO-based amorphous oxide insulating film of the present invention, the carrier density suitable for the active layer of the TFT can be easily and inexpensively produced at a temperature lower than the heat-resistant temperature of the resin substrate. An IGZO-based amorphous oxide semiconductor film having excellent electrical stress and thermal stability.

「場效電晶體(薄膜電晶體:TFT)」"Field Effect Transistor (Thin Film Transistor: TFT)"

參照圖3A至圖3D,對本發明的場效電晶體的製造方法進行說明。於本實施形態中,以底閘極型為例進行說明。圖3A~圖3D為場效電晶體(TFT)的製程圖(基板的厚度方向的截面圖)。為了容易目視確認,構成要素的縮尺與實際有適當不同。A method of manufacturing the field effect transistor of the present invention will be described with reference to Figs. 3A to 3D. In the present embodiment, the bottom gate type will be described as an example. 3A to 3D are process diagrams of a field effect transistor (TFT) (a cross-sectional view in the thickness direction of the substrate). In order to make it easy to visually confirm, the scale of the constituent elements is appropriately different from the actual one.

本實施形態的場效電晶體(TFT)2在基板B上具備包含藉由上述本發明的IGZO系非晶氧化物半導體膜的製造方法所製造的IGZO系非晶氧化物半導體膜1的活性層11。In the field effect transistor (TFT) 2 of the present embodiment, the active layer of the IGZO-based amorphous oxide semiconductor film 1 produced by the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention is provided on the substrate B. 11.

如圖4所示,於本發明的IGZO系非晶氧化物半導體膜的製造方法中,只要背壓為1×10-5 Pa以上、5×10-4 Pa以下,退火處理溫度在100℃以上300℃以下的範圍內,則可製造出具備具有良好開關特性的載子密度、對電性應力以及熱的穩定性良好的IGZO系半導體膜,因此場效電晶體可結合其他層的退火處理條件等選擇退火處理溫度,選擇於該退火處理溫度下實現開關特性良好的載子濃度的背壓。As shown in FIG. 4, in the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention, the annealing temperature is 100° C. or more as long as the back pressure is 1×10 −5 Pa or more and 5×10 −4 Pa or less. In the range of 300 ° C or lower, an IGZO-based semiconductor film having a carrier density with good switching characteristics and excellent electrical stress and thermal stability can be produced. Therefore, the field effect transistor can be combined with annealing treatment conditions of other layers. The annealing treatment temperature is selected, and the back pressure of the carrier concentration having a good switching characteristic is selected at the annealing treatment temperature.

因此,根據本發明,可藉由簡便的製程低成本地製造具備對電性應力以及熱的穩定性優異的活性層11,且元件穩定性優異的IGZO系TFT2。Therefore, according to the present invention, the IGZO-based TFT 2 having the active layer 11 excellent in electrical stress and heat stability and having excellent element stability can be manufactured at a low cost by a simple process.

以下,對TFT2的製造方法進行詳細說明。Hereinafter, a method of manufacturing the TFT 2 will be described in detail.

首先,如圖3A所示,準備基板B,形成包含n+Si等的閘電極21後,形成閘極絕緣膜31。First, as shown in FIG. 3A, the substrate B is prepared, and after forming the gate electrode 21 including n + Si or the like, the gate insulating film 31 is formed.

基板B並無特別限定,可使用與上述實施形態所述之基板相同的基板。於本發明的TFT的製造方法中,是藉由上述本發明的IGZO系非晶氧化物半導體膜的製造方法而製造活性層11,因此可在樹脂基板B的耐熱溫度以下的溫度下製造活性層11。因此,可應用樹脂製軟性基板作為基板B。The substrate B is not particularly limited, and the same substrate as the substrate described in the above embodiment can be used. In the method for producing a TFT of the present invention, the active layer 11 is produced by the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention. Therefore, the active layer can be produced at a temperature lower than the heat-resistant temperature of the resin substrate B. 11. Therefore, a resin-made flexible substrate can be applied as the substrate B.

閘極絕緣膜31並無特別限定,於基板B為樹脂基板之情形時,需為可在樹脂基板B的耐熱溫度以下的溫度下形成的閘極絕緣膜。The gate insulating film 31 is not particularly limited. When the substrate B is a resin substrate, it is necessary to form a gate insulating film which can be formed at a temperature lower than the heat resistant temperature of the resin substrate B.

其次,如圖3B所示,形成包含IGZO系非晶氧化物薄膜1的活性層11(亦可包含不可避免的雜質)。活性層11的形成方法如上述實施形態所述。例如在背壓為5×10-5 Pa的情況下,藉由150℃~220℃(因耐熱性為220℃)的退火處理可製造良好的活性層11。Next, as shown in FIG. 3B, the active layer 11 containing the IGZO-based amorphous oxide film 1 (which may contain unavoidable impurities) is formed. The method of forming the active layer 11 is as described in the above embodiment. For example, in the case where the back pressure is 5 × 10 -5 Pa, a good active layer 11 can be produced by an annealing treatment at 150 ° C to 220 ° C (heat resistance of 220 ° C).

繼而,如圖3C所示,於活性層11上形成源電極22以及汲電極23。Then, as shown in FIG. 3C, the source electrode 22 and the germanium electrode 23 are formed on the active layer 11.

最後,如圖3D所示,於活性層11、源電極22以及汲電極23上形成保護膜(絕緣膜)32。Finally, as shown in FIG. 3D, a protective film (insulating film) 32 is formed on the active layer 11, the source electrode 22, and the germanium electrode 23.

藉由以上步驟,可製造出本實施形態的TFT2。Through the above steps, the TFT 2 of the present embodiment can be manufactured.

本實施形態的場效電晶體(TFT)2是使用上述本發明的IGZO系非晶氧化物半導體膜的製造方法來製造活性層11。因此,根據IGZO系TFT的製造方法,可藉由簡便的製程低成本地製造具備對電性應力以及熱的穩定性良好的IGZO系活性層且元件穩定性優異的IGZO系場效電晶體。In the field effect transistor (TFT) 2 of the present embodiment, the active layer 11 is produced by using the above-described method for producing an IGZO-based amorphous oxide semiconductor film of the present invention. Therefore, according to the method for producing an IGZO-based TFT, an IGZO-based field effect transistor having an IGZO-based active layer excellent in electrical stress and heat stability and excellent in element stability can be manufactured at a low cost by a simple process.

如上所述,圖4顯示,對於導電膜以及絕緣膜,亦可同樣地藉由優化濺鍍成膜時的背壓與退火處理的溫度的組合,而製造具有任意電阻值且對電性應力以及熱的穩定性良好的IGZO系非晶氧化物薄膜。As described above, FIG. 4 shows that, for the conductive film and the insulating film, it is also possible to manufacture an arbitrary resistance value and electrical stress as well by optimizing the combination of the back pressure at the time of sputtering film formation and the temperature of the annealing treatment. An IGZO-based amorphous oxide film having good thermal stability.

例如,圖4的▲、◇的線圖(背壓6×10-6 Pa、1×10-5 Pa:背壓較低的區域(高真空))有如下傾向:在退火溫度100℃~300℃的範圍內具有極小值,其後在400℃附近電阻值上升至1×106附近,顯示大致固定值。此處,極小值附近的電阻值處於導體區域(電阻值為100 Ω‧cm以下,較佳為10 Ω‧cm以下),因此藉由在未達1×10-5 Pa的背壓(下述式(12))下,在100℃~300℃範圍內的適宜溫度(下述式(2))下進行退火處理,可製造出具有導體區域的電阻值的IGZO系非晶氧化物薄膜。For example, the line diagram of ▲ and ◇ in Fig. 4 (back pressure 6 × 10 -6 Pa, 1 × 10 -5 Pa: area with low back pressure (high vacuum)) has the following tendency: at an annealing temperature of 100 ° C to 300 There is a minimum value in the range of °C, and thereafter the resistance value rises to around 1 × 10 6 at around 400 ° C, showing a substantially fixed value. Here, the resistance value near the minimum value is in the conductor region (the resistance value is 100 Ω ‧ cm or less, preferably 10 Ω ‧ cm or less), and therefore, the back pressure is less than 1 × 10 -5 Pa (described below) In the formula (12)), an annealing treatment is carried out at a suitable temperature (the following formula (2)) in the range of 100 ° C to 300 ° C to produce an IGZO-based amorphous oxide film having a resistance value of a conductor region.

100≦T(℃)≦300(2)、100≦T(°C)≦300(2),

P(Pa)<1×10-5 (12)P(Pa)<1×10 -5 (12)

進而,與極大值同樣,極小值附近的溫度下的退火處理因退火處理溫度的面內均勻性對電阻值產生的影響減少,所以可獲得與上述相同的效果,故較佳。Further, similarly to the maximum value, the annealing treatment at a temperature near the minimum value is less affected by the in-plane uniformity of the annealing treatment temperature, so that the same effect as described above can be obtained, which is preferable.

如圖4所示,可認為顯示極小值的退火處理溫度根據背壓而不同。因此,於顯示極小值的退火處理溫度不明確的背壓條件下,較佳為將背壓設為未達1×10-5 Pa的特定值而將IGZO系非晶氧化物層濺鍍成膜,預先獲取在100℃以上、300℃以下的範圍內進行退火處理時IGZO系非晶氧化物層的電阻值對退火處理溫度的依存性,於電阻值的變化率成為0的溫度附近(±5℃)進行退火處理。As shown in FIG. 4, it can be considered that the annealing treatment temperature showing the minimum value differs depending on the back pressure. Therefore, under the back pressure condition in which the annealing temperature at which the minimum value is displayed is not clear, it is preferable to sputter the IGZO-based amorphous oxide layer into a film by setting the back pressure to a specific value of less than 1 × 10 -5 Pa. When the annealing treatment is performed in the range of 100 ° C or more and 300 ° C or less, the resistance value of the IGZO-based amorphous oxide layer depends on the annealing treatment temperature, and the temperature change rate of the resistance value becomes 0 (±5). °C) Annealing treatment.

與上述情況相反,圖4的○、●的圖形(背壓5×10-4 Pa、2×10-3 Pa)有如下傾向:在退火溫度100℃~300℃的範圍內具有極大值,其後在400℃附近電阻值減少至1×10-6附近,顯示大致固定值。極大值附近的電阻值處於絕緣體區域(電阻值107 Ω以上),因此藉由在5×10-4 Pa以上的背壓(下述式(13))下,在100℃~300℃的範圍內(下述式(2))的適宜溫度下進行退火處理,可製造出具有絕緣體區域的電阻值的IGZO系非晶氧化物薄膜。Contrary to the above, the pattern of ○ and ● in FIG. 4 (back pressure 5×10 −4 Pa, 2×10 −3 Pa) has a tendency to have a maximum value in the range of annealing temperature of 100° C. to 300° C. After that, the resistance value was reduced to around 1 × 10 -6 at around 400 ° C, showing a substantially fixed value. Since the resistance value in the vicinity of the maximum value is in the insulator region (resistance value is 107 Ω or more), it is in the range of 100 ° C to 300 ° C by a back pressure of 5 × 10 -4 Pa or more (the following formula (13)). The annealing treatment is carried out at a suitable temperature (the following formula (2)) to produce an IGZO-based amorphous oxide film having a resistance value of an insulator region.

100≦T(℃)≦300 (2)、100≦T(°C)≦300 (2),

5×10-4≦P(Pa) (13)5×10 -4 ≦P(Pa) (13)

與極小值同樣,極大值附近的溫度下的退火處理因退火處理溫度的面內均勻性對電阻值造成的影響變少,故較佳。根據基板的耐熱性,決定退火處理溫度,採用於該退火處理溫度附近具有極大值的背壓,藉此可製造出膜面內的絕緣性的均勻性高,可靠性優異的絕緣膜。Similarly to the minimum value, the annealing treatment at a temperature near the maximum value is preferable because the influence of the in-plane uniformity of the annealing treatment temperature on the resistance value is small. The annealing treatment temperature is determined in accordance with the heat resistance of the substrate, and a back pressure having a maximum value in the vicinity of the annealing treatment temperature is employed, whereby an insulating film having high insulation uniformity in the film surface and excellent reliability can be produced.

迄今為止,尚無電阻值相對於退火處理溫度的變化方式如此根據濺鍍成膜時的背壓而不同的報告。Heretofore, there has been no report on how the resistance value changes with respect to the annealing treatment temperature in accordance with the back pressure at the time of sputtering film formation.

根據上述本發明者等人的見解,藉由改變背壓及退火溫度的組合,不僅可製造具有半導體區域的電阻值的IGZO系非晶氧化物薄膜,還可一併製造具有導體區域以及絕緣體區域範圍內的任意電阻值的IGZO系非晶氧化物薄膜,因此可藉由於濺鍍成膜中僅改變背壓的簡便方法,於基板上形成IGZO系非晶氧化物半導體膜、以及具有絕緣體區域及導體區域的特定電阻值的多種IGZO系非晶氧化物薄膜,而製造場效電晶體,故較佳。According to the findings of the inventors of the present invention, by changing the combination of the back pressure and the annealing temperature, it is possible to manufacture not only an IGZO-based amorphous oxide film having a resistance value of a semiconductor region but also a conductor region and an insulator region. An IGZO-based amorphous oxide film having any resistance value in the range, so that an IGZO-based amorphous oxide semiconductor film can be formed on the substrate and an insulator region can be formed by a simple method of changing only the back pressure in the sputtering film formation. A variety of IGZO-based amorphous oxide thin films having specific resistance values in the conductor region are preferred, and field effect transistors are preferred.

例如,可在藉由上述製造方法於基板上製造具有絕緣體區域的特定電阻值的IGZO系非晶氧化物薄膜後,降低濺鍍成膜中的背壓,藉由上述本發明的IGZO系非晶矽半導體膜的製造方法而製造半導體層1,進一步降低背壓而製造源電極22及汲電極23、或此等的接觸層。此時,退火處理的溫度較佳為全部層採用相同溫度,或上層的退火溫度小於下層的退火溫度。For example, after the IGZO-based amorphous oxide film having a specific resistance value of the insulator region is formed on the substrate by the above-described manufacturing method, the back pressure in the sputtering film formation can be reduced, and the IGZO-based amorphous film of the present invention described above can be used. The semiconductor layer 1 is produced by the method for producing a germanium semiconductor film, and the back electrode is further reduced to produce the source electrode 22 and the germanium electrode 23, or the contact layers thereof. At this time, the annealing temperature is preferably such that the same temperature is used for all the layers, or the annealing temperature of the upper layer is smaller than the annealing temperature of the lower layer.

就簡化製程方面而言,較佳為藉由上述IGZO系非晶氧化物薄膜的製造方法製造儘可能多的層。In terms of simplifying the process, it is preferred to manufacture as many layers as possible by the above-described method for producing an IGZO-based amorphous oxide film.

如上所述,本發明的IGZO系非晶氧化物半導體膜的製造方法可藉由300℃以下的低溫製程而實施,因此耐熱性低的可撓性基板亦適用。因此,本發明的場效電晶體的製造方法可同樣地藉由300℃以下的低溫製程來製造構成TFT2的其他層,藉此亦可適用於軟性顯示器等所使用的薄膜電晶體(TFT)的製造。As described above, the method for producing the IGZO-based amorphous oxide semiconductor film of the present invention can be carried out by a low-temperature process of 300 ° C or lower. Therefore, a flexible substrate having low heat resistance is also applicable. Therefore, in the method of manufacturing the field effect transistor of the present invention, the other layers constituting the TFT 2 can be manufactured by a low temperature process of 300 ° C or lower, which is also applicable to a thin film transistor (TFT) used for a flexible display or the like. Manufacturing.

上述實施形態是對底閘極型場效電晶體進行說明,但亦可適用於高閘極型場效電晶體。In the above embodiment, the bottom gate type field effect transistor is described, but it can also be applied to a high gate type field effect transistor.

[實例][Example]

對本發明的實例以及比較例進行說明。Examples of the invention and comparative examples will be described.

(實例1)(Example 1)

使用InGaZnO4(at比)多結晶靶材,於約1 cm2見方的市售合成石英基板(厚度1 mm,T-4040合成石英基板)上形成膜厚50 nm的IGZO膜。An InGaZnO 4 (at ratio) polycrystalline target was used to form an IGZO film having a thickness of 50 nm on a commercially available synthetic quartz substrate (thickness 1 mm, T-4040 synthetic quartz substrate) of about 1 cm 2 square.

為了調查背壓以及退火處理溫度對IGZO膜的電阻值所產生的影響,將背壓(成膜前的極限真空度)分別設為6×10-6 Pa、1×10-5 Pa、2×10-5 Pa、5×10-5 Pa、6.5×10-5 Pa、1×10-4 Pa、5×10-4 Pa、2×10-3 Pa,分別準備樣品。此時背壓的設定是以如下方式進行:於大氣開放後開始對濺鍍裝置的成膜室真空排氣,利用設置於濺鍍裝置中的離子真空計確認到達所期望的背壓條件後開始成膜。其他成膜條件為:基板溫度Ts=常溫、Ar/O2混合環境(Ar流量:30 sccm,O2流量0.25 sccm)、成膜壓力0.8 Pa、基板-靶材的間距150 mm、靶材輸入電力DC 50 W(IGZO)、成膜時間約19分鐘。In order to investigate the influence of the back pressure and the annealing temperature on the resistance value of the IGZO film, the back pressure (the ultimate vacuum before film formation) was set to 6 × 10 -6 Pa, 1 × 10 -5 Pa, 2 ×, respectively. Samples were prepared for 10 -5 Pa, 5 × 10 -5 Pa, 6.5 × 10 -5 Pa, 1 × 10 -4 Pa, 5 × 10 -4 Pa, and 2 × 10 -3 Pa, respectively. At this time, the back pressure is set in such a manner that the film forming chamber of the sputtering apparatus is evacuated after the atmosphere is opened, and the ion vacuum gauge provided in the sputtering apparatus is used to confirm that the desired back pressure condition is reached. Film formation. Other film formation conditions were: substrate temperature Ts = normal temperature, Ar/O 2 mixed environment (Ar flow rate: 30 sccm, O 2 flow rate 0.25 sccm), film formation pressure 0.8 Pa, substrate-target spacing 150 mm, target input The power is DC 50 W (IGZO) and the film formation time is about 19 minutes.

濺鍍成膜後,利用XRF(X-ray Fluorescent Analyzer,X射線螢光分析儀)對退火處理前的5種樣品測定膜厚以及組成,結果確認任一樣品均為In:Ga:Zn=1:0.9:0.7,膜厚約50 nm。After sputter deposition, the film thickness and composition of the five samples before annealing were measured by XRF (X-ray Fluorescent Analyzer), and it was confirmed that any of the samples was In:Ga:Zn=1. : 0.9:0.7, film thickness is about 50 nm.

繼而,使用加熱板,在各種退火處理溫度(100℃、150℃、200℃、250℃、300℃、350℃、400℃、450℃、500℃、600℃)下對上述樣品實施5分鐘的退火,使用Hiresta (三菱化學製造,MCP-HT450(探針式URS))測定電阻值(電阻率)。將其結果示於圖4。Then, using a hot plate, the above samples were subjected to 5 minutes at various annealing treatment temperatures (100 ° C, 150 ° C, 200 ° C, 250 ° C, 300 ° C, 350 ° C, 400 ° C, 450 ° C, 500 ° C, 600 ° C). Annealing, resistance value (resistivity) was measured using Hiresta (manufactured by Mitsubishi Chemical Corporation, MCP-HT450 (probe type URS)). The result is shown in Fig. 4.

圖4顯示,例如於退火處理溫度為250℃時,電阻值根據背壓條件而有約9位數的變化。由圖4確認,藉由優化濺鍍成膜時的背壓與退火處理溫度,可製造具有導體區域至絕緣體區域中任意電阻值的IGZO系非晶氧化物薄膜。Fig. 4 shows that, for example, when the annealing treatment temperature is 250 ° C, the resistance value has a change of about 9 digits depending on the back pressure condition. It is confirmed from Fig. 4 that an IGZO-based amorphous oxide film having any resistance value in the conductor region to the insulator region can be produced by optimizing the back pressure at the time of sputtering film formation and the annealing treatment temperature.

為調查濺鍍成膜時的背壓對膜特性的影響,藉由ATR法(attenuated total reflectance method,減弱全反射法)對濺鍍成膜後未經退火處理的5種樣品以及用作參考的石英基板實施表面的FT-IR測定(ThermoFisher製造的Nicolet 4700)。將其結果示於圖5。如圖5所示,確認任一樣品均觀測到來自OH基的伸縮振動的波峰(2500 cm-1至4000 cm-1範圍的寬波峰),隨著背壓變高其波峰面積增大。In order to investigate the influence of the back pressure on the film characteristics during the film formation by sputtering, the ATR method (attenuated total reflectance method) was used to treat the five samples which were not annealed after sputtering and used as a reference. The quartz substrate was subjected to FT-IR measurement of the surface (Nicolet 4700 manufactured by ThermoFisher). The result is shown in Fig. 5. As shown in Fig. 5, it was confirmed that the peak of the stretching vibration from the OH group (the broad peak in the range of 2500 cm -1 to 4000 cm -1 ) was observed in any of the samples, and the peak area increased as the back pressure became higher.

此外,確認上述傾向即便於使用複數種靶材的共濺鍍時亦相同。Further, it was confirmed that the above tendency is the same even when co-sputtering using a plurality of kinds of targets.

(比較例1)(Comparative Example 1)

除將背壓設為1×10-6 Pa的固定條件,將成膜氣體的氧氣流量變為0.25 sccm、0.33 sccm、0.4 sccm以外,藉由與實例1相同的方式製造IGZO非晶氧化物薄膜的樣品,於與實例1相同的退火條件下進行退火,測定各自的電阻值。將其結果示於圖6。An IGZO amorphous oxide film was produced in the same manner as in Example 1 except that the back pressure was set to a fixed condition of 1 × 10 -6 Pa, and the oxygen flow rate of the film forming gas was changed to 0.25 sccm, 0.33 sccm, and 0.4 sccm. The samples were annealed under the same annealing conditions as in Example 1, and the respective resistance values were measured. The result is shown in Fig. 6.

如圖6所示,確認藉由增加氧氣流量,濺鍍成膜後的IGZO薄膜的電阻值增高,但藉由在250℃下進行退火處理,任一樣品的電阻值均成為極小值,電阻降至導體區域。As shown in Fig. 6, it was confirmed that the resistance value of the IGZO thin film after sputtering deposition was increased by increasing the oxygen flow rate, but the annealing value at 250 ° C caused the resistance value of any of the samples to be extremely small, and the resistance was lowered. To the conductor area.

1‧‧‧IGZO系非晶氧化物半導體膜(半導體膜) 1‧‧‧IGZO-based amorphous oxide semiconductor film (semiconductor film)

2‧‧‧場效電晶體(薄膜電晶體:TFT) 2‧‧‧ Field Effect Transistor (Thin Film Transistor: TFT)

11‧‧‧活性層 11‧‧‧Active layer

21‧‧‧閘電極 21‧‧‧ gate electrode

22‧‧‧源電極 22‧‧‧ source electrode

23‧‧‧汲電極 23‧‧‧汲 electrode

31‧‧‧閘極絕緣膜 31‧‧‧Gate insulation film

32‧‧‧保護膜 32‧‧‧Protective film

B‧‧‧成膜基板 B‧‧‧ film forming substrate

圖1是模式性地表示在濺鍍成膜時改變背壓時的成膜裝置中的含水量與所形成的IGZO系非晶氧化物薄膜中的含水量的關係的圖。FIG. 1 is a view schematically showing the relationship between the water content in the film forming apparatus when the back pressure is changed at the time of sputtering film formation and the water content in the formed IGZO-based amorphous oxide film.

圖2是表示半導體膜的載子密度與電阻率的關係的圖。2 is a view showing a relationship between a carrier density of a semiconductor film and a specific resistance.

圖3A是表示本發明的一實施形態的半導體裝置(薄膜元件)的製程的截面圖(1)。3A is a cross-sectional view (1) showing a process of a semiconductor device (thin film element) according to an embodiment of the present invention.

圖3B是表示本發明的一實施形態的半導體裝置的製程的截面圖(2)。3B is a cross-sectional view (2) showing a process of a semiconductor device according to an embodiment of the present invention.

圖3C是表示本發明的一實施形態的半導體裝置的製程的截面圖(3)。3C is a cross-sectional view (3) showing a process of a semiconductor device according to an embodiment of the present invention.

圖3D是表示本發明的一實施形態的半導體裝置的製程的截面圖(4)。3D is a cross-sectional view (4) showing a process of a semiconductor device according to an embodiment of the present invention.

圖4是表示實例1中於不同背壓下濺鍍成膜的IGZO系非晶氧化物薄膜的電阻值與退火處理溫度的關係的圖。4 is a graph showing the relationship between the electric resistance value and the annealing treatment temperature of the IGZO-based amorphous oxide film sputter-deposited under different back pressures in Example 1. FIG.

圖5是表示圖4所示的濺鍍成膜後的IGZO系非晶氧化物薄膜表面的OH基的峰值波長附近的IR光譜的圖。FIG. 5 is a view showing an IR spectrum in the vicinity of the peak wavelength of the OH group on the surface of the IGZO-based amorphous oxide film after the sputtering deposition shown in FIG. 4 .

圖6是表示比較例1中以不同氧氣流量濺鍍成膜的IGZO系非晶氧化物薄膜的電阻值與退火處理溫度的關係的圖。6 is a graph showing the relationship between the electric resistance value and the annealing treatment temperature of an IGZO-based amorphous oxide thin film which is sputter-deposited at different oxygen flow rates in Comparative Example 1. FIG.

圖7是專利文獻1的圖4。FIG. 7 is a diagram 4 of Patent Document 1.

2...場效電晶體(薄膜電晶體:TFT)2. . . Field effect transistor (thin film transistor: TFT)

11(1)...活性層11(1). . . Active layer

21...閘電極twenty one. . . Gate electrode

22...源電極twenty two. . . Source electrode

23...汲電極twenty three. . . Helium electrode

31...閘極絕緣膜31. . . Gate insulating film

32...保護膜32. . . Protective film

B...成膜基板B. . . Film forming substrate

Claims (12)

一種IGZO系非晶氧化物半導體膜的製造方法,其是藉由將IGZO系非晶氧化物層濺鍍成膜後,進行退火處理而製造包含IGZO系非晶氧化物的半導體膜的方法,其特徵在於:於滿足下述式(1)以及(2)的條件下成膜,2×10-5≦P(Pa)≦5×10-4 (1)、100≦T(℃)≦300 (2)(式中,P為上述濺鍍成膜中的背壓,T為上述退火處理中的退火溫度)。 A method for producing an IGZO-based amorphous oxide semiconductor film, which is obtained by sputtering an IGZO-based amorphous oxide layer and then performing annealing treatment to produce a semiconductor film including an IGZO-based amorphous oxide. characterized in that: in the film formation conditions satisfying the following formula (1) and (2), 2 × 10 -5 ≦ P ( Pa) ≦ 5 × 10 -4 (1), 100 ≦ T (℃) ≦ 300 ( 2) (wherein P is the back pressure in the above-described sputtering film formation, and T is the annealing temperature in the above annealing treatment). 如申請專利範圍第1項所述之IGZO系非晶氧化物半導體膜的製造方法,其中於滿足下述式(3)的條件下成膜,2×10-5≦P(Pa)≦1×10-4 (3)。 The method for producing an IGZO-based amorphous oxide semiconductor film according to the first aspect of the invention, wherein the film is formed under the condition that the following formula (3) is satisfied, 2 × 10 -5 ≦ P (Pa) ≦ 1 × 10 -4 (3). 如申請專利範圍第1項所述之IGZO系非晶氧化物半導體膜的製造方法,其中上述退火溫度為150℃以上、250℃以下。 The method for producing an IGZO-based amorphous oxide semiconductor film according to the first aspect of the invention, wherein the annealing temperature is 150° C. or higher and 250° C. or lower. 如申請專利範圍第2項所述之IGZO系非晶氧化物半導體膜的製造方法,其中於滿足下述式(4)以及(5)的條件下成膜,P(Pa)=2×10-5 (4)、200≦T(℃)≦300 (5)。 The method for producing an IGZO-based amorphous oxide semiconductor film according to the second aspect of the invention, wherein the film is formed under the conditions satisfying the following formulas (4) and (5), and P(Pa) = 2 × 10 - 5 (4), 200 ≦T (°C) ≦ 300 (5). 如申請專利範圍第2項所述之IGZO系非晶氧化物半導體膜的製造方法,其中於滿足下述式(6)以及(7) 的條件下成膜,P(Pa)=5×10-5 (6)、120≦T(℃)≦270 (7)。 The method for producing an IGZO-based amorphous oxide semiconductor film according to the second aspect of the invention, wherein the film is formed under the conditions satisfying the following formulas (6) and (7), and P(Pa) = 5 × 10 - 5 (6), 120≦T (°C) ≦ 270 (7). 如申請專利範圍第2項所述之IGZO系非晶氧化物半導體膜的製造方法,其中於滿足下述式(8)以及(9)的條件下成膜,P(Pa)=6.5×10-5 (8)、100≦T(℃)≦240 (9)。 The method for producing an IGZO-based amorphous oxide semiconductor film according to the second aspect of the invention, wherein the film is formed under the conditions satisfying the following formulas (8) and (9), and P(Pa) = 6.5 × 10 - 5 (8), 100 ≦T (°C) ≦ 240 (9). 如申請專利範圍第2項所述之IGZO系非晶氧化物半導體膜的製造方法,其中於滿足下述式(10)以及(11)的條件下成膜,P(Pa)=1×10-4 (10)、100≦T(℃)≦195 (11)。 The method for producing an IGZO-based amorphous oxide semiconductor film according to the second aspect of the invention, wherein the film is formed under the conditions of the following formulas (10) and (11), and P(Pa) = 1 × 10 - 4 (10), 100 ≦T (°C) ≦ 195 (11). 如申請專利範圍第1項至第7項中任一項所述之IGZO系非晶氧化物半導體膜的製造方法,其中上述濺鍍成膜中的成膜壓力為10Pa以下。 The method for producing an IGZO-based amorphous oxide semiconductor film according to any one of the first to seventh aspect, wherein the film formation pressure in the sputtering film formation is 10 Pa or less. 如申請專利範圍第1項至第7項中任一項所述之IGZO系非晶氧化物半導體膜的製造方法,其中上述濺鍍成膜中的成膜氣體包含Ar與O2,該成膜氣體中的Ar與O2的流量比例為O2/Ar≦1/15。 The method for producing an IGZO-based amorphous oxide semiconductor film according to any one of the preceding claims, wherein the film-forming gas in the sputtering film formation contains Ar and O 2 , and the film formation is performed. The flow ratio of Ar to O 2 in the gas is O 2 /Ar≦1/15. 如申請專利範圍第8項所述之IGZO系非晶氧化物半導體膜的製造方法,其中上述濺鍍成膜中的成膜氣體包含Ar與O2,該成膜氣體中的Ar與O2的流量比例為O2/Ar≦1/15。 The application method of producing an amorphous IGZO-based oxide semiconductor film of the patentable scope of item 8, wherein the film forming gas in the sputtering deposition contains O 2 and Ar, the deposition gas of Ar and O 2 The flow ratio is O 2 /Ar≦1/15. 一種場效電晶體的製造方法,其是於基板上具備包含IGZO系非晶氧化物的半導體層、源電極、汲電極、閘電極及閘極絕緣膜而成的薄膜電晶體的製造方法,其特徵在於:藉由如申請專利範圍第1項至第10項中任一項之非晶氧化物半導體膜的製造方法而形成上述半導體層。 A method for producing a field effect transistor, which is a method for producing a thin film transistor comprising a semiconductor layer including an IGZO-based amorphous oxide, a source electrode, a germanium electrode, a gate electrode, and a gate insulating film on a substrate, The semiconductor layer is formed by the method for producing an amorphous oxide semiconductor film according to any one of claims 1 to 10. 如申請專利範圍第11項所述之場效電晶體的製造方法,其中使用可撓性基板作為上述基板。 A method of producing a field effect transistor according to claim 11, wherein a flexible substrate is used as the substrate.
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