201135853 37524pif 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種IGZO(銦鎵鋅氧化物，inGaZnO ) 系非晶氧化物半導體膜的製造方法以及使用該製造方法的 場效電晶體的製造方法。 【先前技術】 場效電晶體可用於半導體記憶體用積體電路的單位 元件、高頻訊號放大元件、液晶驅動用元件等，特別是經 薄膜化的場效電晶體正作為薄膜電晶體（thin film transistor，TFT)而用於廣泛領域。 形成場效電晶體的半導體通道層（活性層）多使用矽 半導體或其化合物，需要高速運作的高頻放大元件、積體 電路等是使用單晶矽，而在雖然低速運作便足夠，但要求 應對顯示器用途等大面積化的液晶驅動裝置用途中是使用 非晶碎。 於顯示器領域中，近年來輕量且可彎曲的軟性顯示器 (flexible display)備受矚目。上述軟性裝置主要使用可撓 ，高的樹脂基板’但樹脂基板的耐熱溫度通常為15〇〜2⑽ °c，即便耐熱性高的聚醯亞胺系樹脂亦僅為3〇〇亡左右， 低於玻璃基板等無機基板。於非晶矽的製程中，通常需要 超過30G°C的高溫加熱處理，因此非晶料於耐熱性低， 故而難以用於目前顯示器中的軟性基板等支撐基板。· 另一方面，曰本東京工業大學的細野^等人發現 In-Ga-Zn-O系（IGZO系）氧化物半導體於室溫下可^膜 4 201135853 37524pif 且即便為非晶態亦可表現出半導體的性能，認為有希望用 作下一代顯示器用TFT材料（非專利文獻1、2)。 然而已知：於室溫成膜後未實施退火處理等穩定化處 理的IGZO系非晶氧化物半導體雖然可作為TFr的活性層 而發揮功能，但其臨界電壓（threshold voltage)容易因驅 動時的電性應力（electricalstress)而發生偏移，在元件穩 定性方面存在問題。 作為元件穩定性優異的活性層，如非專利文獻3或非 專利文獻4等所記載，較佳為成膜後於35〇。(：〜4〇〇。(：下實 施退火處理的IGZ0系非晶氧化物半導體。專利文獻1的 圖4 (本說明書的圖7)表明，若於室溫下的真空成膜後， 於120C〜25〇。(：下對作為半導體膜的非晶IGZ〇膜實施退 火處理（加熱處理）’則载子密度增大，使電阻降至1位數 至3位數以上。即，採用樹脂基板的_熱溫度範圍的退火 處理時’難以獲得具有顯示出作為電晶體活性層的良好半 導體特性賴子密度（lxl()13〜lxl()16^m3)的半導體 層。本發明者等人亦確認了上述傾向（參照下述實例圖6)。 專利文獻2中揭示有具備包含IGZ〇系非晶氧化物薄 導體層與閘極絕緣膜的電晶體，並揭示有將濺鍍成 =的_氣體中的氧氣流量比轉為⑽ ^ =膜==，比率設為2〇%以上而形成問= 能會導致電阻值發生變化，==== 201135853 i/DZ^pif 面存在問題。 另外，專利=獻3中揭示有：對於具備非晶氧化物膜 作為半導體層的場效電晶體，其為了使元件穩定性變得良 好，而對電極部以及半導體層添加氫或氘。 [先前技術文獻] [專利文獻] [專利文獻1]日本專利特開2009-99847號公報 [專利文獻2]日本專利特開2〇〇7_1〇9918號公報 [專利文獻3]日本專利第4332545號公報 [非專利文獻] [非專利文獻 1]K. Nomura et al，Science，300 (2003) 1269.201135853 37524pif 6. Technical Field of the Invention The present invention relates to a method for producing an IGZO (indium gallium zinc oxide, inGaZnO)-based amorphous oxide semiconductor film, and a field effect transistor using the same Manufacturing method. [Prior Art] The field effect transistor can be used as a unit element of a semiconductor memory integrated circuit, a high frequency signal amplifying element, a liquid crystal driving element, etc., in particular, a thinned field effect transistor is being used as a thin film transistor (thin Film transistor (TFT) is used in a wide range of fields. The semiconductor channel layer (active layer) forming the field effect transistor mostly uses a germanium semiconductor or a compound thereof, and a high frequency amplifying element, an integrated circuit or the like which requires high speed operation is a single crystal germanium, and although it is sufficient at a low speed, it is required. Amorphous shreds are used in applications for liquid crystal driving devices that have a large area such as display applications. In the field of displays, lightweight and flexible flexible displays have attracted attention in recent years. The flexible device mainly uses a flexible and high resin substrate. However, the heat resistance temperature of the resin substrate is usually 15 〇 to 2 (10) ° C. Even the heat-resistant polyimide resin is only about 3 dying, lower than An inorganic substrate such as a glass substrate. In the process of the amorphous germanium, a high-temperature heat treatment of more than 30 G ° C is usually required. Therefore, the amorphous material has low heat resistance, and thus it is difficult to be used for a support substrate such as a flexible substrate in the conventional display. · On the other hand, Hiroshi Esaka of Tokyo Institute of Technology found that In-Ga-Zn-O (IGZO-based) oxide semiconductors can be used at room temperature for 4 201135853 37524pif and can be expressed even in amorphous state. The semiconductor performance is expected to be used as a TFT material for next-generation displays (Non-Patent Documents 1 and 2). However, it is known that an IGZO-based amorphous oxide semiconductor which is not subjected to stabilization treatment such as annealing treatment after being formed at room temperature can function as an active layer of TFr, but its threshold voltage is easily driven by driving. Electrical stress is offset and there is a problem in element stability. As an active layer excellent in element stability, as described in Non-Patent Document 3 or Non-Patent Document 4, it is preferably 35 Å after film formation. (:~4〇〇. (: IGZ0-based amorphous oxide semiconductor subjected to annealing treatment. Figure 4 of Patent Document 1 (Fig. 7 of the present specification) shows that, after vacuum film formation at room temperature, at 120C 〜25〇. (: The annealing treatment (heat treatment) is performed on the amorphous IGZ ruthenium film as a semiconductor film', the carrier density is increased, and the resistance is reduced to 1 to 3 digits or more. That is, the resin substrate is used. In the annealing treatment of the thermal temperature range, it is difficult to obtain a semiconductor layer having a good semiconductor property as a dielectric active layer (lxl () 13 to lxl () 16 ^ m 3 ). The inventors have confirmed The above tendency (refer to the following example FIG. 6). Patent Document 2 discloses a transistor including a IGZ lanthanide-based amorphous oxide thin conductor layer and a gate insulating film, and discloses a gas which is sputtered to = The oxygen flow ratio in the conversion is (10) ^ = membrane ==, the ratio is set to 2% or more and the formation of the question = can cause the resistance value to change, ==== 201135853 i / DZ ^ pif surface problem. In addition, the patent = 献3 reveals: for a field with an amorphous oxide film as a semiconductor layer In the case of a transistor, a hydrogen or a ruthenium is added to the electrode portion and the semiconductor layer in order to improve the stability of the element. [Prior Art Document] [Patent Document] [Patent Document 1] Japanese Patent Laid-Open Publication No. 2009-99847 [Patent [Patent Document 3] Japanese Patent No. 4332545 [Non-Patent Document] [Non-Patent Document 1] K. Nomura et al, Science, 300 (2003) 1269 .
[非專利文獻 2]K. Nomura et al，Nature, 432 (2004) 488 [非專利文獻 3]K. Nomura et al, Applied Physics Letters 93 (2008) 192107 [非專利文獻 4]D. Kang et al，Applied Physics Letters 90(2008) 192101 【發明内容】 [發明所欲解決之問題] 然而，由於氫或氘的導入需要新的設備以及製程，所 以在製程的簡便性以及成本方面存在問題。 本發明是鑒於上述情況研究而成者，其目的在於提 供：一種IGZO系非晶氧化物半導體膜的製造方法，其是 可在樹脂基板上製造的IGZO系非晶氧化物半導體膜的製 6 201135853 37524pif =方法，其藉㈣便且低成本的製程，而製造I有適 層的載子密度且對電性應力以及熱的穩^性 良好的！GZO纟非絲化物㈣黯； 造元件穩定性«的IGZ0系場效電晶體的^ ^方法氣 [解決問題之技術手段] 本發明者發現：在基板上將IGZO系非晶氧化物薄膜 濺鑛成膜時，藉由優化_成断的背壓與難成膜後的 退火處理溫度，可製造具有任意t阻值且熱敎性良好的 IGZO系非晶氧化物絕緣體薄膜。 進而，本發明者基於上述見解發現一種簡便且低成本 地製造可在樹脂基板上製造，具有適合作為TFT的活性層 的載子密度’且對電性應力以及熱的穩定性良好的IGZ〇 系非晶氧化物半導體膜的方法。 即，本發明提供一種IGZO系非晶氧化物半導體膜的 製造方法’其是藉由將IGZ〇系祚晶氧化物層濺鍍成膜後 實施退火處理而製造包含IGZ0系#晶氧化物的半導體膜 的方法’其特徵在於：於滿足下述式（1)以及（2)的條 件下成膜。在本發明的IGZO系#晶氧化物半導體膜的製 造方法中，較佳為進而於滿足下述式（3)的條件下成膜。 lxl〇-5^P (Pa) ^5χ10*4 ⑴、 lOO^T (°〇 ^3〇〇 (2)、 2xl〇'5^p (pa) ^ΐχΐ〇*4 (3) (式中，P為上述濺鍍成膜中的背壓，T為上述退火 處理中的退火溫度） 201135853 •3 OZHpif 此慝，所謂 /锻成膜中的背厘」，是濺鑛成膜時·今 置有基板的真空容器（成膜裝置）内的極限真 # 即向成膜裝置中導入成膜氣體前的成膜;i 、於本說明書中，極限真空度（背壓）是讀取設置於滅 鑛成膜I置+的離子真空計（iGngauge)的值。成膜裝置 ^的極限真空度（龍）大財同於成膜裝置⑽含水量 (水分壓）’因而亦可採用由使用質量分析計（例如ulvac 公司的QuleeCGM系列等）測得的水分壓所求得的值。 於本說明書中’所謂IGZ0系非晶氧化物薄膜，是指 包含In、Ga的非晶氧化物薄膜，較佳為更包含Zn的非晶 氧化物薄膜。除此等金屬元素以外，亦可包含摻雜劑或取 代元素等其他元素。 、於本說明書中，所謂退火處理，不僅包括濺鍍成膜後 的退火處理，還包括加熱經濺鍍成膜的薄膜的全部處理， 例如包括光微影等圖案化步驟、或所積層的膜的成膜步驟 中的加熱處理等。 於本說明書中，「導體」是指電阻率為1〇〇 Ω· cm以 下者。 另外，「半導體」是指電阻率在1〇3〜1〇6 Ω · cm範圍 内者。另外，「絕緣體」是指電阻率為107Ω· cm以上者》 上述退火溫度較佳為150°C以上、250°C以下。 本發明的IGZ0系非晶氧化物半導體膜的製造方法較 佳為.於滿足下述式（4)以及（5)的條件下，或滿足（6) 8 201135853 37524pif 以及（7)的條件下，或滿足（8) 者滿足（10)以及（11)的條件下成^。9)的條件下，或 P (Pa) =2xl〇·5 (4)、 、 200^T (°C) ^300 (5)> P (Pa) =5xl0*5 (6)、 120^T (°C ) ^270 (7)、 P (Pa) =6.5xl0'5 ( 8) > lOO^T (°C) ^240 (9). P (Pa) =lxl〇'4 ( 10)、 lOO^T (°C ) ^195 (li) 的背壓P的值 此外，上述式（4)、（6)、（8)、（1〇) 具±10%的幅度。 於本發明的脱0系非晶氧化物半導體膜的 中，上述濺鍍成膜的成膜壓力較佳為1〇Pa以下；^々沄 另外，較佳為將上述濺鍍成膜的成膜氣體設為含 Ar與〇2的氣體’將該成膜氣體中的心與仏的 設為 02/Ar$l/15。 本發明提供一種場效電晶體的製造方法，其是於基板 上具備包含IGZO系非晶氧化物的半導體層、源電極、汲 電極、閘電極以及閘極絕緣膜而成的薄膜電晶體的製造方 法’其特徵在於：藉由上述本發明的IGZO系非晶氧化物 半導體膜的製造方法而形成上述半導體層。 於本發明的場效電晶體的製造方法中，較佳為使用可 撓性基板作為上述基板。 201135853 37524pif 於曰本專利特開2007-73697號公報中記載有：藉由於 成膜時的環境氣體中以5.〇xl〇5 Pa〜1〇 pa的分壓含有水， 可穩定地製造常_ TFT。“轉财顧：於上述水 分壓範_職的IGZO系氧化物_若實_脂基板的 耐熱溫度以下的退火處理’職電阻值根據賴時的水分 麼的差異而不同’由於此電阻值範圍遍及絕緣體區域至導 體區域，故而於上述水分壓下無法穩定地製造τρΓ。詳細 情況見下文。 ' 於日本專利特開2007-73697號公報中雖然未記載退 火處理’但實質上本發明者針對藉由日本專利特開 2007-73697號公報所記载的麵（通常的高真幻以及水 分壓而獲得雜性層追加進行了 TFT運作·的試驗，结 果未能輕作為TFT的運作，鑒於上述情況可認為日本專 利特開2GG7-73697號公報中是在働。c以上的溫度下 退火虑:理。 因此’本發明首次能夠製造藉由在樹脂基板的耐轨溫 度以工的溫，進行退域理峨得穩定化，具有ΐχΐ〇ΐ3〜 ㈣+妓，域合作為TFT騎性層的 於二1 物半導體膜。根據本發明，僅藉由對應 二L退火處理溫度（樹脂基板的耐熱溫度以下）將濺 =的=r：rxi〜_= [發明之效果] 201135853 37524pif 本發明是藉由lxl(T5以上、5xl〇-4以下的背壓將IGZO 系非晶氧化物層濺鍍成膜後，在loot：以上、300°C以下的 溫度下進行退火處理，而製造包含IGZO系非晶氧化物的 半導體膜。根據該方法，可在樹脂基板的耐熱溫度以下的 溫度下簡便且低成本地製造具有適合作為TFT的活性層的 載子密度且對電性應力以及熱的穩定性良好的IGZ〇系非 晶氧化物半導體膜。 因此，於IGZO系場效電晶體的製造方法中，藉由利 用本發明的IGZO系非晶氧化物半導體膜的製造方法製造 活性層（半導體層）’可憑藉簡便的製程低成本地製造具備 對電性應力以及熱的穩定性良好的IGZ〇系非晶氧化物絕 緣層且元件穩定性優異的IGZO系場效電晶體。 【實施方式】 「IGZO系非晶氧化物半導體膜的製造方法」 本發明者對製造對電性應力或熱的穩定性良好的 IGZO系非晶氧化物薄膜的方法進行潛心研究。結果發現： 所形成的IGZO轉晶氧化物薄_電阻值根據成膜裝置 内的含水量而改變’㈣電阻值根據崎成膜後的退火處 而改變，即藉由優化成膜裝置内的含 火處理溫度的組合，可製造出具有導體區域至絕 域範圍内的任意電阻值且對電性應力以及熱的穩定 性良好的IGZO糸非晶氧化物薄膜（參照下述實例卜 於本說明書中，「導體」是指電阻率為ι〇〇ω·_ 下者。 11 201135853 37524pif 另外，「半導體」是指電阻率為l〇3〜l〇6 Ω · cm範圍 内者。另外，於本說明書中，「絕緣體」是指電阻率為1〇7 Ω · cm以上者。 已知於濺鍍成膜中成膜裝置内的含水量（水分壓）與 濺鍍成膜的背壓相關，已知背壓越低即越為高真空，水分 壓越低。本發明者改變濺鍍成膜時的背壓，藉由fT_ir (fourier transform infrared radiation，傅立葉轉換紅外線光 譜）測定來分析所形成的電阻值不同的各IGZ〇系非晶氧 化物薄膜實施的組成，結果確認：於各非晶氧化物薄膜中， OH基的波峰面積不同，若提高背壓，則〇H基的量增加， 即含水量增加（參照下述實例、圖5)。 圖1是表示改變背壓（成膜裝置内的極限真空度）時 成膜裝置内的含水量與所形成的；[GZ0系非晶氧化物薄膜 内的含水量的關係的示意圖。如圖所示，背壓越高，成膜 裝置内的含水量越多。因此，可認為滲入膜中的水分增多 會對薄膜的電阻值產生影響。 由圖1以及下述實例的圖5可確認：剛濺鍍成膜後的 IGZO系非晶氧化物薄膜中的含水量（〇H基量）根據濺鍍 成膜時的背壓而變化。並且，圖4顯示，根據濺鍍成膜時 的背壓的差異與激鑛成膜後的退火溫度，可製造出具有導 體區域至絕緣體區域的區域中的各種電阻值的系非 晶氧化物薄膜。 7 成膜裝置内的含水量的控制方法並不限定於藉由上 述減錄成膜中的背壓來控制，例如亦可藉由於成膜過程中 12 201135853 37524pif 直接導入水分的方法等來加以控制。如「解決問題之技術 手段」項所述，背壓為導人成膜氣體前的成膜裝置内的真 空度’是可容㈣變更設定的时，耻錄為藉由背壓 控制氧化㈣膜巾的含水量。町，舉舰明控制背壓而 控制含水量的方法。 圖4顯示，對於未實施退火處理狀態的剛賤錢成膜後 的IGZO㈣晶氧化物_ ’亦可形成根據背壓的差異而 具有不同電阻值的IGZQ系非晶氧化物薄膜，但是如「先 前技術」項所述，未實施任何穩定化處理僅實施缝成膜 的絕緣膜在對雜應力或熱的敎性方面存在問題。因 此’於本發明的IGZO系非晶氧化物半導體膜的製造方法 中，是在濺鑛成膜後實施退火處理作為穩定化處理。 即，本發明的IGZO系非晶氧化物半導體膜的製造方 法是在1Χ10-5以上、5x10-4以下的背壓下冑igz〇系非晶 氧化物層濺鍍成膜後，在10(rc以上、3〇(rc以 進行退火虚理β ^ ^ 退火處理的方法並無特別限定，因為常壓下的退火便 足夠’所雜容㈣方法是制加餘等進行滅處理。 除此以外，亦可使用潔淨烘箱或真空腔室。， 制如上所述’於本發㈣IGZC>轉晶氧化物半導體膜 的製造方法巾’在贿成料航變其背壓，成膜裝置内 的含水量在使雌-频成财法時均根據背壓而^變。 因此’於本發⑽IGZ〇轉晶氧化物半導咖的製造方 法中，賴成膜的方法並無特別限定，可應用任意方法。 13 201135853 作為濺鐘成膜方法，例如可舉出：二極濺鍵法、三極 濺鍍法、直流濺鍍法、高頻濺鍍法（radi〇 frequency sputtering )、電子迴旋共振離子束濺鍍法（dectr〇n c〇upUng resonance sputtering )、磁控濺鍍法（magnetr〇n 印論_ )、 對向乾錢鑛法（facing target sputtering)、脈衝濺鍍法、以 及離子束濺鍍法等。 另外，進行成膜的基板並無特別限定，於本實施形態 中，基板並無特別限定，只要根據用途適當選擇si基板、 玻璃基板、各種軟性基板等即可。本發明的IGZ〇系非晶 氧化物絕緣膜的製造方法可藉由3〇〇1以下的低溫製程而 實施，因此耐熱性低的樹脂基板亦適用。因此，本發明的 IGZO系非晶氧化物半導體膜的製造方法亦可應用於軟性 ·.、具示器等所使用的薄膜電晶體（Tft，thin-film transistor ) 的製造。 作為軟性基板’可舉出：聚乙烯醇系樹脂、聚碳酸酯 衍生物（帝人（股）：WRF)、纖維素衍生物（纖維素三乙 酸醋、纖維素二乙酸酯）、聚烯烴系樹脂（Nipp〇n Zeon (股）：ZEONOR、ZEONEX)、聚砜系樹脂（聚醚颯、聚 礙）、降冰片烯系樹脂（JSR (股）：ARTON)、聚酯系樹脂 (PET(聚對本二曱酸乙二醋，p〇iyethyiene terephthalate)、 PEN (聚秦一曱酸乙二g旨，polyethylene naphthalene)、交 聯反丁烯二酸二酯）、聚醯亞胺系樹脂、聚醯胺系樹脂、聚 酿胺醯亞胺系樹脂、聚芳酯系樹脂、丙烯酸系樹脂、環氧 系樹脂、環硫系樹脂、氟系樹脂、聚矽氧系樹脂膜、聚苯 201135853 37524pif ^系樹脂、氰酸料樹脂、芳香族醚系樹脂（聚賴）、 ，丁歸二ϋ亞胺.稀烴純脂等的樹脂基板、液晶聚合物基 另外’於此物脂基板巾含魏化雜子、金屬奈米 ，、無機氧化物奈綠子、無機氮化物奈綠子、金屬 糸/無機m雜或織維、碳纖維 片、玻璃纖維、玻璃珠、黏土礦物、雲母二= 複合樹脂基板；以及[Non-Patent Document 2] K. Nomura et al, Nature, 432 (2004) 488 [Non-Patent Document 3] K. Nomura et al, Applied Physics Letters 93 (2008) 192107 [Non-Patent Document 4] D. Kang et al [Applied Physics Letters 90 (2008) 192101 [Disclosure] [Problems to be Solved by the Invention] However, since the introduction of hydrogen or helium requires new equipment and processes, there are problems in terms of process simplicity and cost. The present invention has been made in view of the above circumstances, and an object of the invention is to provide a method for producing an IGZO-based amorphous oxide semiconductor film, which is an IGZO-based amorphous oxide semiconductor film which can be produced on a resin substrate. 37524pif = method, which uses (four) and low-cost process, and manufacture I has a suitable carrier density and good electrical stress and heat stability! GZO纟Non-filament (4)黯; IGZ0 field effect transistor for element stability«^ Method gas [Technical means for solving the problem] The inventors found that: IGZO-based amorphous oxide film is sputtered on the substrate At the time of film formation, an IGZO-based amorphous oxide insulator film having an excellent t resistance and good thermal conductivity can be produced by optimizing the back pressure to be broken and the annealing temperature after film formation. Further, based on the above findings, the inventors have found that an IGZ lanthanide which can be produced on a resin substrate and has a carrier density which is suitable as an active layer of a TFT and which is excellent in electrical stress and heat stability is found to be simple and low-cost. A method of an amorphous oxide semiconductor film. In other words, the present invention provides a method for producing an IGZO-based amorphous oxide semiconductor film, which is obtained by sputtering an IGZ lanthanide-based oxide layer to form a film, and then performing annealing treatment to produce a semiconductor including IGZ0-based #crystalline oxide. The method of the film is characterized in that a film is formed under the conditions satisfying the following formulas (1) and (2). In the method for producing an IGZO-based crystal oxide semiconductor film of the present invention, it is preferred to form a film under the condition that the following formula (3) is satisfied. Lxl〇-5^P (Pa) ^5χ10*4 (1), lOO^T (°〇^3〇〇(2), 2xl〇'5^p (pa) ^ΐχΐ〇*4 (3) (where, P is the back pressure in the above-mentioned sputtering film formation, and T is the annealing temperature in the above annealing treatment) 201135853 • 3 OZHpif This is the back PCT in the so-called/forging film, which is when the film is splashed and formed. The limit in the vacuum container (film forming apparatus) of the substrate is the film formation before the film forming gas is introduced into the film forming apparatus; i. In the present specification, the ultimate vacuum degree (back pressure) is read and set in the mine. The value of the ion vacuum gauge (iGngauge) of the film formation I. The ultimate vacuum degree (long) of the film forming apparatus is the same as that of the film forming apparatus (10) water content (moisture pressure), and thus the mass spectrometer can be used. In the present specification, the term "IGZ0-based amorphous oxide film" refers to an amorphous oxide film containing In and Ga, and is preferably a value obtained by the measurement of the water pressure. Further, an amorphous oxide film containing Zn may contain other elements such as a dopant or a substitution element in addition to these metal elements. The annealing treatment includes not only the annealing treatment after the sputtering film formation but also the entire processing of heating the film formed by sputtering, for example, a patterning step including photolithography or a film forming step of the film of the laminated layer. Heat treatment, etc. In the present specification, "conductor" means a resistivity of 1 〇〇 Ω·cm or less. "Semiconductor" means a resistivity of 1 〇 3 to 1 〇 6 Ω · cm. In addition, the "insulator" means a resistivity of 107 Ω·cm or more. The annealing temperature is preferably 150 ° C or more and 250 ° C or less. The method for producing an IGZ0 -based amorphous oxide semiconductor film of the present invention is preferably. Under the conditions of the following formulas (4) and (5), or satisfying the conditions of (6) 8 201135853 37524pif and (7), or satisfying the conditions of (8) satisfying (10) and (11) ^.9), or P (Pa) = 2xl 〇 5 (4), 200 ^ T (°C) ^ 300 (5) > P (Pa) = 5xl0 * 5 (6), 120 ^T (°C ) ^270 (7), P (Pa) =6.5xl0'5 ( 8) > lOO^T (°C) ^240 (9). P (Pa) =lxl〇'4 ( 10 ), lOO^T (°C) ^195 (li) The value of the back pressure P, in addition, Said formula (4), (6), (8), (1〇) having an amplitude of ± 10%. In the anodic oxide-based amorphous oxide semiconductor film of the present invention, the film formation pressure of the sputtering film formation is preferably 1 〇 Pa or less; more preferably, the film formation by sputtering is preferably performed. The gas was set to a gas containing Ar and 〇2. The core and ruthenium in the film-forming gas were set to 02/Ar$l/15. The present invention provides a method for producing a field effect transistor, which is characterized in that a thin film transistor including a semiconductor layer including an IGZO-based amorphous oxide, a source electrode, a germanium electrode, a gate electrode, and a gate insulating film is provided on a substrate. The method of the present invention is characterized in that the semiconductor layer is formed by the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention. In the method of producing a field effect transistor of the present invention, it is preferred to use a flexible substrate as the substrate. In the ambient gas at the time of film formation, water is contained in a partial pressure of 5.〇xl〇5 Pa~1〇pa, which can be stably produced _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TFT. "Transfer of the granules of the above-mentioned water pressure _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Between the insulator region and the conductor region, τρΓ cannot be stably produced under the above-described water pressure. For details, see the following. Although the annealing treatment is not described in Japanese Patent Laid-Open No. 2007-73697, the present inventors In the surface described in the Japanese Patent Publication No. 2007-73697 (a general high-fidelity and a water-pressure-pressure layer, a hetero-functional layer was added and a TFT operation was performed. As a result, the operation of the TFT was not light, and the above situation was considered. It is considered that the Japanese Patent Laid-Open Publication No. 2GG7-73697 is annealed at a temperature higher than 働c. Therefore, the present invention can be manufactured for the first time by retreating the temperature at the temperature of the resin substrate. Stabilized, having ΐχΐ〇ΐ3~(4)+妓, the domain cooperation is a TFT semiconductor layer of the TFT riding layer. According to the present invention, the temperature is only treated by the corresponding two L annealing The heat resistance temperature of the resin substrate is not more than the following: = r:rxi~_= [effect of the invention] 201135853 37524pif The present invention is an IGZO-based amorphous oxide by lxl (T5 or more, 5xl〇-4 or less back pressure) After the layer is sputter-deposited, the film is annealed at a temperature of 500° C. or higher to produce a semiconductor film containing an IGZO-based amorphous oxide. According to this method, the temperature of the resin substrate can be lower than the heat-resistant temperature of the resin substrate. An IGZ lanthanide-based amorphous oxide semiconductor film having a carrier density suitable as an active layer of a TFT and having good electrical stress and heat stability is easily and inexpensively manufactured. Therefore, in the IGZO-based field effect transistor In the production method, the active layer (semiconductor layer) can be produced by the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention, which can be manufactured at a low cost by a simple process and has excellent stability against electrical stress and heat. IGZ-based amorphous oxide insulating layer and IGZO-based field effect transistor having excellent element stability. [Embodiment] "Method for producing IGZO-based amorphous oxide semiconductor film" The method of IGZO-based amorphous oxide film with good electrical stress or thermal stability was studied. It was found that the thin _resistance value of the formed IGZO crystal oxide changed according to the water content in the film forming apparatus. (4) The resistance value is changed according to the annealing portion after the film formation, that is, by optimizing the combination of the fire treatment temperature in the film forming apparatus, any resistance value from the conductor region to the absolute region can be manufactured and the electrical stress is applied. And an IGZO糸 amorphous oxide film having good thermal stability (refer to the following example. In the present specification, "conductor" means the resistivity is ι〇〇ω·_. 11 201135853 37524pif In addition, "semiconductor" It means that the resistivity is in the range of l〇3~l〇6 Ω·cm. In addition, in the present specification, "insulator" means a resistivity of 1 〇 7 Ω · cm or more. It is known that the water content (water pressure) in the film forming apparatus in the sputtering film formation is related to the back pressure of the sputtering film formation, and it is known that the lower the back pressure, the higher the vacuum, and the lower the water pressure. The inventors of the present invention changed the back pressure at the time of sputtering film formation, and analyzed the composition of each of the IGZ lanthanide-based amorphous oxide films having different resistance values by fT_ir (fourier transform infrared spectroscopy) measurement. As a result, it was confirmed that in each of the amorphous oxide thin films, the peak area of the OH group is different, and when the back pressure is increased, the amount of the 〇H group is increased, that is, the water content is increased (see the following example, FIG. 5). Fig. 1 is a schematic view showing the relationship between the water content in the film forming apparatus and the water content in the GZ0-based amorphous oxide film when the back pressure (the ultimate vacuum degree in the film forming apparatus) is changed. As shown, the higher the back pressure, the greater the water content in the film forming apparatus. Therefore, it is considered that an increase in the amount of moisture permeating into the film affects the resistance value of the film. From Fig. 1 and Fig. 5 of the following example, it was confirmed that the water content (〇H basis amount) in the IGZO-based amorphous oxide film immediately after the sputtering film formation changes depending on the back pressure at the time of sputtering film formation. Further, FIG. 4 shows that an amorphous oxide film having various resistance values in a region from a conductor region to an insulator region can be produced according to the difference in back pressure at the time of sputtering film formation and the annealing temperature after film formation of the ore. . 7 The method for controlling the water content in the film forming apparatus is not limited to being controlled by the back pressure in the above-described subtractive film formation, and may be controlled, for example, by a method of directly introducing water into the film during the film formation process, 201132853 37524pif. . As described in the "Technical means for solving the problem", when the back pressure is the vacuum degree in the film forming apparatus before the film forming gas is introduced, it is possible to change (4) the setting, and the shame is controlled by the back pressure to control the oxidation (four) film. The moisture content of the towel. In the town, the method of controlling the water content by controlling the back pressure. 4 shows that IGZQ-based amorphous oxide film having different resistance values according to the difference in back pressure can be formed for the IGZO (tetra) crystal oxide _ ' after the film formation without the annealing treatment, but as in the case of "previously As described in the "Technology", the insulating film which is not subjected to any stabilization treatment and which is only subjected to slit film formation has a problem in the compatibility with impurities or heat. Therefore, in the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention, an annealing treatment is performed as a stabilization treatment after sputtering and film formation. In other words, in the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention, after the 胄igz〇-based amorphous oxide layer is deposited by a back pressure of 1Χ10-5 or more and 5×10-4 or less, the film is formed at 10 (rc). The above method of argon annealing for annealing annealing is not particularly limited, because annealing under normal pressure is sufficient to make the impurity (four) method to perform the addition and the like to eliminate the treatment. It is also possible to use a clean oven or a vacuum chamber. As described above, the method of manufacturing the IGZC> crystallized oxide semiconductor film in the present invention is in the back pressure of the briquetting aeronautical material, and the water content in the film forming apparatus is In the method for producing the IGZ〇 crystal oxide semi-conductive coffee according to the present invention, the method for forming the film is not particularly limited, and any method can be applied. 13 201135853 As a method of film formation by sputtering, for example, a two-pole sputtering method, a three-pole sputtering method, a DC sputtering method, a radiant frequency sputtering method, and an electron cyclotron resonance ion beam sputtering method are mentioned. Method (dectr〇nc〇upUng resonance sputtering), magnetron splash The method (magnetr〇n __), the facing target sputtering, the pulse sputtering method, the ion beam sputtering method, etc. Further, the substrate to be formed is not particularly limited. In the embodiment, the substrate is not particularly limited, and the Si substrate, the glass substrate, the various flexible substrates, and the like may be appropriately selected depending on the application. The method for producing the IGZ lanthanum-based amorphous oxide insulating film of the present invention may be 3 〇〇 or less. The resin substrate having a low heat resistance is also suitable for use in a low-temperature process. Therefore, the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention can also be applied to a thin film transistor used for softness, display, and the like. Production of (Tft, thin-film transistor). Examples of the flexible substrate include a polyvinyl alcohol-based resin, a polycarbonate derivative (Teijin: WRF), and a cellulose derivative (cellulose triacetate, Cellulose diacetate), polyolefin resin (Nipp〇n Zeon (ZE), ZEONEX), polysulfone resin (polyether oxime, polyg), norbornene resin (JSR) ARTON), gather Resin (PET (poly-p-ethyl bismuth vinegar, p〇iyethyiene terephthalate), PEN (polyethylene naphthalene), cross-linked fumaric acid diester), poly phthalate An amine resin, a polyamine resin, a polyacrylamide resin, a polyarylate resin, an acrylic resin, an epoxy resin, an episulfide resin, a fluorine resin, a polyoxyn resin film, Polyphenyl 201135853 37524pif ^ resin, cyanate resin, aromatic ether resin (poly lyon), butyl quinone imine, resin substrate such as thin hydrocarbon pure fat, liquid crystal polymer base The substrate towel contains Weizhi heterophase, metal nanoparticle, inorganic oxide naphthalene, inorganic nitride natriuretic, metal ruthenium/inorganic m or woven, carbon fiber sheet, glass fiber, glass beads, clay mineral, mica Two = composite resin substrate;
於薄玻璃與上述單獨有機材料之間至少具有i個接人 界面的積層塑膠材料、藉由將無機層（exSi〇2、Al2(J SK^Ny)與有機層（上述）交替積層而至少具有i個以上 接合界面的具有阻隔性能的複合材料； ^不鏽鋼基板、將不鏽鋼與不同種金屬積層而成的金屬 j基板、IS基板、或藉由對表面實施氧化處理（例如陽 3化處理）而提昇表面的絕緣性的附有氧化被膜的紹基 作為IGZO系非晶氧化物的一例可舉出下述通式 (P1)所表示的InGaZn〇4 (iGZ0)等同系化合物。 (ln2.xGax)03 · (ZnO)m (PI) (式中〇Sx$2且m為自然數） ▲成膜時的成膜壓力並無特別限定，但若成膜壓力過 兩’則成膜速度下降，生產性變差，因此較佳為1〇以以 下，更佳為5 Pa以下，更佳為lpa以下。 麟成膜時的成膜氣體並無特職定，可舉出包含 15 201135853a laminated plastic material having at least one interface between the thin glass and the above-mentioned individual organic material, at least having an inorganic layer (exSi〇2, Al2(J SK^Ny) and an organic layer (described above) alternately laminated a composite material having barrier properties of i or more bonding interfaces; a stainless steel substrate, a metal j substrate in which stainless steel is laminated with different kinds of metals, an IS substrate, or an oxidation treatment (for example, a positive treatment) on the surface An example of the IGZO-based amorphous oxide which is an oxidized film which improves the insulating properties of the surface is an InGaZn〇4 (iGZ0) equivalent compound represented by the following formula (P1). (ln2.xGax) 03 · (ZnO)m (PI) (wherein 〇Sx$2 and m is a natural number) ▲The film formation pressure at the time of film formation is not particularly limited, but if the film formation pressure exceeds two', the film formation rate decreases, and productivity Since it is deteriorated, it is preferably 1 Torr or less, more preferably 5 Pa or less, and still more preferably 1 kPa or less. The film forming gas at the time of film formation has no special purpose, and may include 15 201135853
Ar與〇2者。 如「先前技術」項所述，濺鍍形成的膜的電阻值根據 上述成膜氣體中的Ar與〇2的流量比而改變，於本發明的 成膜方法中，不僅可改變背壓來控制電阻值，亦可改變成 膜氣體的流量比來控制電阻值，但是有提高氧氣分壓而導 致成膜速度下降的傾向，如下述比較例1的圖6所示，亦 存在於某些背壓以及退火處理溫度下，成膜時的氧氣分屋 幾乎不對電阻值產生影響的情況。本發明可藉由僅優化背 壓與退火處理溫度而製造出具有絕緣體區域的電阻值的 IGZO系非晶氧化物薄膜，因此氧氣分壓〇2/Αγ較佳為設為 1/15以下的固定值。 本發明者確認電阻值與載子密度相關（圖2)。通常， "Τ獲得良好的開關特性的電晶體的活性層的載子密度為 1Χ1013〜lxl〇i6個/cm3，因此可獲得良好的開關特性的半導 體區域的電阻值是圖2的虛線框内的電阻值範圍（1〇3〜1〇6 Ω · cm的範圍）内的值。因此，藉由設為上述背壓條件以 及退火處理溫度範圍，可製造出膜面内的載子密度的均勻 性高，開關特性良好，可靠性優異的IGZO系非晶氧化物 半導體膜。 於下述實例1中，於成膜壓力0.8 Pa、輸入電力DC5〇 W、Ar : 30 sccm、a : 〇 25 seem的條件下，改變背壓以 及退火處理溫度而製造顯示各種電阻值的IGZO系非晶氧 化物薄膜。如圖4所示，於背壓較高的範圍、較低的範^、 以及其中間區域’電阻值（電阻率）相對於退火處理溫度 201135853 37524pif 而變化方式不同。 在圖)的_ □、♦、△的線圖（背壓 lxl〇-4Pa、6.5xl〇-5 Pa、5><10_ Pa'2x1(r5pa)中，藉由提昇退火溫度，電阻 值在獅。(：以了的區域持續增大。另外，關於♦的線圖， 於的退火處理溫度細，斜率㈣非常平緩 並成為表π 10〜105Ω _ em範圍㈣大致固定值的形狀。 圖4顯示，藉由在背壓1χ1〇·5 Pa以上、5x1g.4 pa以 下’退火處理溫度WC〜的朗，選擇適宜的背壓 與退火處理溫度敝合，可製造討獲得電喊ι〇3〜ι〇6 Ω· cm範圍内的良好開關特性的半導體膜。 另外顯示，當將背壓設為^⑺^匕時，於15(rc〜25〇 °C的退火處理溫度範_，退火處理溫㈣_均句性對 電阻值造成的影響較小，並可減小退火纽中的薄膜的膜 面内的溫度分佈等對膜面内的電阻值的均勻性產生的影 響。 進而圖4顯示，若將退火處理溫度設為4〇〇〇c以上， 則無論激錄成膜時的背塵如何，均可製造出具有可獲得良 好開關特性的半導體區域的電阻值，膜面内的載子密度的 均勻性高，可靠性優異的IGZO系非晶氧化物薄膜。 如圖4所示，並非在滿足下述式（丨）以及（2)、或 (3)以及（2)的全部範圍内均可獲得具有電阻值1〇3〜 ΙΟ6 Ω . cm範圍内的良好開關特性的半導體膜。圖4顯示 如下傾向：於滿足下述式（1)的範圍内背壓越低（越接近 高真空），可製造可獲得良好開關特性的半導體膜的退火溫 17 201135853 37524pif 度於滿足下述式（2)的範圍内變得越高。 例如，作為可形成上述半導體膜的條件，可舉出滿足 下述式（4)以及（5)的條件、或滿^ (6)以及⑺的 條件、或滿足⑴以及⑼的條件、或者滿足（ι〇)以 及（11)的條件（P為上述背壓，τ為上述退火處理的溫 度）。此外，下述式⑷、⑷、⑴、⑴）的背壓P的值 具有±10%的幅度。 即便於下述式（4)〜（U)所表示的範圍外，只要 調查滿足下述式（1)的任意背壓下的滿足式（2)的退火 溫度與電阻值的關’所發現的背壓與退火溫度的組合亦 可製造出可獲得良好開關特性的半導體膜。 P (Pa) =2x10-5 ⑷、 、 200$T(〇C)S300 ⑴、 P (Pa) =5xl〇'5 ⑷、 120$T(°C)各270 (7)、 P (Pa) =6.5xl〇*5 (8)、 ΙΟΟ^Τ (°〇 ^240 (9). P (Pa) =lxl〇*4 ( 10)、 lOO^T C°C) ^195 (Π) ，另外，於上述本發明的IGZ〇系非晶氧化物半導體膜 的製造方法中，退火處理溫度為1〇(rc〜3〇(rc。因此，本 發明的IGZO系非晶氧化物半導體膜的製造方法在樹脂基 板等耐熱性低的可撓性基板上亦適用。 土 如上所述，根據本發明的IGZ0系非晶氧化物絕緣膜 201135853 37524pif 的製造方法，可在樹脂基板的耐熱溫度以下的溫度下簡便 且低成本地製造具有適合作為TFT的活性層的載子密度且 對電性應力以及熱的穩定性良好的IGZ〇系非晶氧化物 導體膜。 「場效電晶體（薄膜電晶體：TFT)」 參照圖3A至圖3D’對本發明的場效電晶體的製造方 法進行說明。於本實施形態中，以底閘極型為例進行說明。 圖3A〜圖3D為場效電晶體（TFT)的製程圖（基板的厚 度方向的截面圖）。為了容易目視確認’構成要素的縮尺盘 實際有適當不同。 本實施形態的場效電晶體（TFT) 2在基板Β上具備 包含藉由上述本發_ IGZ〇轉晶氧化物半導體膜^製 造方法所製造的IGZO系非晶氧化物半導體膜i的活性層 11 ° 如圖4所示，於本發明的IGZ〇系非晶氧化物半導 膜的製造方法中，只要背壓為lxl〇-5 Pa以上、5χΐ〇.4 & 以下，退火處理溫度在10(rc以上3〇(rc以下的範圍内 可製造出具備具有良好開關特性的載子密度、對電性鹿力 以及熱的穩定性良好的IGZ〇系半導體膜，因此場效^晶 體可結合其他層的退火處理條件等選擇退火處理溫度，選 擇於該退火處理溫度下實現開關特性良好的載子濃度的背 磨。 因此，根據本發明，可藉由簡便的製程低成本地製造 具備對電性應力以及熱的穩定性優異的活性層^，且元件 201135853 37524pif 穩定性優異的IGZO系TFT2。 以下’對TFT2的製造方法進行詳細說明。 首先，如圖3A所示’準備基板B，形成包含η+Si等 的閘電極21後，形成閘極絕緣膜31。 基板B並無特別限定，可使用與上述實施形態所述之 基板相同的基板。於本發明的TFT的製造方法中，是藉由 上述本發明的IGZO系非晶氧化物半導體膜的製造方法而 製造活性層11，因此可在樹脂基板B的耐熱溫度以下的溫 度下製造活性層11。因此，可應用樹脂製軟性基板作為基 板B。 閘極絕緣膜31並無特別限定’於基板B為樹脂基板 之情形時，需為可在樹脂基板B的耐熱溫度以下的溫度下 形成的閘極絕緣膜。 其次，如圖3B所示，形成包含IGZQ系非晶氧化物 薄膜1的活性層11 (亦可包含不可避免的雜質）。活性層 11的形成方法如上述實施形態所述。例如在背壓為5xl〇·5 Pa的情況下，藉由15〇。(：〜220°C (因耐熱性為220°C )的 退火處理可製造良好的活性層U。 繼而’如圖3C所示，於活性層11上形成源電極22 以及汲電極23。 最後，如圖3D所示，於活性層11、源電極22以及 汲電極23上形成保護膜（絕緣膜）32。 藉由以上步驟，可製造出本實施形態的TFT2。 本實施形態的場效電晶體（TFT) 2是使用上述本發 20 201135853 37524pif 明的IGZO系非晶氧化物半導體膜的製造方法來製造活性 層11。因此’根據IGZO系TFT的製造方法，可藉由簡便 的製程低成本地製造具備對電性應力以及熱的穩定性良好 的IGZO系活性層且元件穩定性優異的IGZO系場效電晶 體。 如上所述’圖4顯示，對於導電膜以及絕緣膜，亦可 同樣地藉由優化濺鑛成膜時的背壓與退火處理的溫度的組 合，而製造具有任意電阻值且對電性應力以及熱的穩定性 良好的IGZO系非晶氧化物薄膜。 例如，圖4的^、◊的線圖（背壓6xl(T6pa、lxl〇-5pa: 背壓較低的區域（高真空））有如下傾向：在退火溫度1〇〇 C〜300°C的範圍内具有極小值，其後在4〇〇。〇附近電阻值 上升至lx 106附近，顯示大致固定值。此處，極小值附近 的電阻值處於導體區域（電阻值為iQ · cm以下，較佳 為10 Ω · cm以下）’因此藉由在未達ixi〇-5 pa的背壓（下 述式（12))下，在1〇〇。〇〜3〇〇°c範圍内的適宜溫度（下 述式（2))下進行退火處理，可製造出具有導體區域的電 阻值的IGZO系非晶氧化物薄膜β lOO^T (°C ) ^300 (2) ^ P (Pa) < 1χ1〇·5 (12) 進而，與極大值同樣，極小值附近的溫度下的退火處 理因退火處理溫度的面内均勻性對電阻值產生的影變減 少，所以可獲得與上述相同的效果，故較佳。的^ 如圖4所示，可過為顯示極小值的退火處理溫度根據 21 201135853 37524pif 背壓而不同。因此，於顯示極小值的退火處理溫度不明確 的背壓條件下’較佳為將背壓設為未達^(^以的特定值 而將IGZO系非晶氧化物層濺鐘成膜，預先獲取在i〇〇°c 以上、300°C以下的範圍内進行退火處理時IGZ〇系非晶氧 化物層的電阻值對退火處理溫度的依存性，於電阻值的變 化率成為0的溫度附近（±5。(：）進行退火處理。 與上述情況相反，圖4的〇、#的圖形（背壓5χι〇-4 Pa、2χ1〇 pa)有如下傾向：在退火溫度〜3〇〇。〇的 範圍内具有極大值’其後在4〇〇°C附近電阻值減少至ιχ10-6 附近，顯示大致固定值。極大值附近的電阻值處於絕緣體 區域（電阻值107Ω以上），因此藉由在5xl〇-4Pa以上的 背壓（下述式（13))下，在1〇〇。(：〜300°C的範圍内（下 述式（2))的適宜溫度下進行退火處理，可製造出具有絕 緣體區域的電阻值的IGZO系非晶氧化物薄膜。 1〇〇ST(°C)S3〇G (2)、 5xl〇-4^p (Pa) (13) 與極小值同樣，極大值附近的溫度下的退火處理因退 火處理溫度的面内均勻性對電阻值造成的影響變少，故較 佳。根據基板的耐熱性，決定退火處理溫度，採用於該退 火處理溫度附近具有極大值的背壓，藉此可製造出膜面内 的絕緣性的均勻性高，可靠性優異的絕緣膜。 迄今為止，尚無電阻值相對於退火處理溫度的變化方 式如此根據濺鍍成膜時的背壓而不同的報告。 根據上述本發明者等人的見解，藉由改變背壓及退火 22 201135853 37524pif 度的組合’不僅可製造具有半導體區域的電阻值的 系非晶氧化㈣膜’還可-併製造具有導體區域以及絕緣 體區域丨丨圍_的電雜的IGZ。㈣晶氧化物薄膜， 因此可藉由於濺鍍成膜中僅改變背壓的簡便方法，於基板 上形成IGZQ彡非晶氧化物半導顏、以及具有絕緣體區 域及導體輯的特定電阻值的多種IGZ〇系非晶氧化物薄 膜，而製造場效電晶體，故較佳。 例如，可在藉由上述製造方法於基板上製造具有絕緣 體區域的败電阻值的IGZ〇系非晶氧化物薄膜後，降低 滅鐘成膜巾的背壓，藉由上述本發_ IGZ〇系非晶石夕半 導體膜的製造方法而製造半導體層丨，進—步降低背磨而 製造源電極22及沒電極23、或此等的接觸層。此時，退 火處理的溫度較佳為全部層採用相同溫度，或上層的退火 溫度小於下層的退火溫度。 就簡化製程方面而言，較佳為藉由上述1(}2〇系非晶 氧化物薄膜的製造方法製造儘可能多的層。 如上所述，本發明的IGZ0系非晶氧化物半導體膜的 製造方法可藉纟·。c以τ的低溫㈣而實施，因此财熱 =低的可撓&基板亦適用^因此，本發明的場效電晶體的 裝造方法可同樣地藉由肩Μ下的低溫製程來製造構成 TFT2的其他層’藉此亦可適用於軟性顯示器等所使用的薄 膜電晶體（TFT )的製造。 上述實施形態是對底閘極型場效電晶體 亦可適用於高閘極型場效電晶體。 一 23 201135853 D /JZ^pif [實例] 對本發明的實例以及比較例進行說明。 (實例1) 使用InGaZn〇4 ( at比）多結晶靶材，於約i cm2見方 的市售合成石英基板（厚度1 mm，τ_4〇4〇合成石英基板） 上形成膜厚50 nm的IGZO膜。 為了調查背壓以及退火處理溫度對IGZO膜的電阻值 所產生的影響，將背壓（成膜前的極限真空度）分別設為 όχίο·6 Pa、lxi〇-5 Pa、2xl〇-5 Pa、5xl〇-5 Pa、6.5xl〇-5 Pa、 lxl(T4 Pa、5xl(T4 Pa、2xl〇·3 Pa ’ 分別準備樣品。此時背 壓的设定是以如下方式進行：於大氣開放後開始對濺鍵裝 置的成膜室真空排氣，利用設置於濺鍍裝置中的離子真空 叶確認到達所期望的背壓條件後開始成膜。其他成膜條件 為：基板溫度Ts=常溫、Ar/〇2混合環境（Ar流量：3〇 seem，〇2流量0.25 seem)、成膜壓力〇.8Pa、基板名材的 間距150 mm、靶材輸入電力DC 50 W (IGZO)、成膜時間 約19分鐘。 減錄成膜後’利用 XRF( X-ray Fluorescent Analyzer， X射線螢光分析儀）對退火處理前的5種樣品測定膜厚以 及組成’結果確認任一樣品均為In : Ga : Zn= 1 : 0.9 : 0.7， 膜厚約50 nm。 繼而，使用加熱板，在各種退火處理溫度（l〇〇°C、 150°C ' 200°C ' 250〇C ' 300°C > 350〇C ' 400°C ' 450〇C ' 500 C、600°C )下對上述樣品實施5分鐘的退火，使用Hiresta 24 201135853 37524pif (三菱化學製造，MCP-HT45〇 (探針式URS))測定電阻 值（電阻率）。將其結果示於圖4。 圖4顯示，例如於退火處理溫度為25〇<>(：時，電阻值 根據煮壓條件而有約9位數的變化β由圖4確認，藉由優 化濺鍍成膜時的背壓與退火處理溫度，可製造具有導體區 域至絕緣體區域中的電阻值的IGZ〇轉^氧化物^ 膜。Ar and 〇2. As described in the "Prior Art", the resistance value of the film formed by sputtering changes according to the flow ratio of Ar to 〇2 in the film forming gas, and in the film forming method of the present invention, not only the back pressure can be changed to control The resistance value may also change the flow ratio of the film forming gas to control the resistance value, but there is a tendency to increase the partial pressure of oxygen to cause a decrease in the film forming speed, as shown in Fig. 6 of Comparative Example 1 below, and also in some back pressure. At the annealing treatment temperature, the oxygen partitioning at the time of film formation hardly affects the resistance value. According to the present invention, the IGZO-based amorphous oxide film having the electric resistance value of the insulator region can be produced by optimizing only the back pressure and the annealing treatment temperature. Therefore, the oxygen partial pressure 〇2/Αγ is preferably set to be 1/15 or less. value. The inventors confirmed that the resistance value is related to the carrier density (Fig. 2). In general, the carrier density of the active layer of the transistor which obtains good switching characteristics is 1Χ1013~lxl〇i6/cm3, so the resistance value of the semiconductor region which can obtain good switching characteristics is within the dotted line of FIG. The value of the resistance value range (range of 1〇3~1〇6 Ω·cm). Therefore, by setting the above-mentioned back pressure conditions and the annealing treatment temperature range, it is possible to produce an IGZO-based amorphous oxide semiconductor film having high uniformity of carrier density in the film surface, excellent switching characteristics, and excellent reliability. In the following Example 1, an IGZO system exhibiting various resistance values was produced under conditions of a film formation pressure of 0.8 Pa, an input power of DC 5 〇W, Ar: 30 sccm, and a: 〇25 seem, by changing the back pressure and the annealing treatment temperature. Amorphous oxide film. As shown in Fig. 4, the range in which the back pressure is high, the lower range, and the resistance value (resistivity) of the intermediate portion thereof are different with respect to the annealing treatment temperature 201135853 37524pif. In the graph of _ □, ♦, △ of the graph) (back pressure lxl〇-4Pa, 6.5xl〇-5 Pa, 5><10_ Pa'2x1 (r5pa), by increasing the annealing temperature, the resistance value is Lion. (: The area that has been used continues to increase. In addition, regarding the line diagram of ♦, the annealing temperature is fine, and the slope (4) is very gentle and becomes a shape with a substantially fixed value of π 10~105 Ω _ em range (4). It is shown that by selecting the appropriate annealing pressure and the annealing temperature in the back pressure of 1χ1〇·5 Pa or more and 5×1g.4 Pa or less, the optimum back pressure and the annealing temperature can be selected to obtain the electric shouting 〇3~半导体6 semiconductor film with good switching characteristics in the range of Ω·cm. Also shows that when the back pressure is set to ^(7)^匕, at 15 (rc~25〇°C annealing treatment temperature _, annealing temperature) (4) _ uniformity has less influence on the resistance value, and can reduce the influence of the temperature distribution in the film surface of the film in the annealing layer on the uniformity of the resistance value in the film surface. Further, FIG. 4 shows that When the annealing treatment temperature is set to 4 〇〇〇c or more, it can be produced regardless of the back dust at the time of film formation. An IGZO-based amorphous oxide film having a high resistance of a semiconductor region having good switching characteristics, high uniformity of carrier density in a film surface, and excellent reliability. As shown in FIG. 4, the following formula (丨) is not satisfied. And a semiconductor film having good switching characteristics in the range of resistance values from 1 〇 3 to ΙΟ 6 Ω·cm can be obtained in all ranges of (2), or (3) and (2). Fig. 4 shows the following tendency: The lower the back pressure in the range of the formula (1) (the closer to the high vacuum), the annealing temperature of the semiconductor film which can obtain good switching characteristics is 17 201135853 37524 pif degree becomes more and more within the range satisfying the following formula (2) For example, as conditions for forming the semiconductor film, conditions satisfying the following formulas (4) and (5), conditions exceeding (6) and (7), or conditions satisfying (1) and (9), or The conditions of (ι) and (11) are satisfied (P is the above-mentioned back pressure, and τ is the temperature of the above annealing treatment). Further, the values of the back pressure P of the following formulas (4), (4), (1), and (1) have ±10%. The range of the following equations (4) to (U) It is also possible to produce a combination of back pressure and annealing temperature which satisfies the relationship between the annealing temperature of the formula (2) and the resistance value at any back pressure satisfying the following formula (1) to obtain good switching characteristics. Semiconductor film P (Pa) = 2x10-5 (4), 200$T (〇C) S300 (1), P (Pa) = 5xl 〇 '5 (4), 120$T (°C) 270 (7), P ( Pa) = 6.5xl 〇 *5 (8), ΙΟΟ^Τ (°〇^240 (9). P (Pa) = lxl〇*4 (10), lOO^TC°C) ^195 (Π), In the method for producing an IGZ lanthanum-based amorphous oxide semiconductor film of the present invention, the annealing treatment temperature is 1 〇 (rc 〜 3 〇 (rc). Therefore, the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention is also applicable to a flexible substrate having low heat resistance such as a resin substrate. As described above, according to the method for producing an IGZ0-based amorphous oxide insulating film 201135853 37524pif of the present invention, a carrier having an active layer suitable as a TFT can be easily and inexpensively produced at a temperature lower than the heat-resistant temperature of the resin substrate. An IGZ lanthanide-based amorphous oxide conductor film having a high density and good electrical stress and heat stability. "Field Effect Transistor (Thin Film Transistor: TFT)" A method of manufacturing the field effect transistor of the present invention will be described with reference to Figs. 3A to 3D'. In the present embodiment, the bottom gate type will be described as an example. 3A to 3D are process diagrams of a field effect transistor (TFT) (a cross-sectional view in the thickness direction of the substrate). In order to make it easy to visually confirm that the scale elements of the constituent elements are actually different. The field effect transistor (TFT) 2 of the present embodiment includes an active layer including an IGZO-based amorphous oxide semiconductor film i produced by the above-described method for producing a IGZ〇-transfer oxide semiconductor film. 11 ° As shown in FIG. 4, in the method for producing an IGZ lanthanide-based amorphous oxide semiconductor film of the present invention, the annealing temperature is as long as the back pressure is lxl 〇 -5 Pa or more and 5 χΐ〇.4 & 10 (rc or more 3 〇 (in the range below rc, an IGZ lanthanide semiconductor film having a carrier density with good switching characteristics, good electrical deer force, and heat stability can be produced, so field effect crystals can be combined. The annealing treatment temperature of the other layer is selected to select the annealing treatment temperature, and the back grinding of the carrier concentration with good switching characteristics is selected at the annealing treatment temperature. Therefore, according to the present invention, it is possible to manufacture the electricity with low cost by a simple process. The active layer excellent in the stress and the thermal stability, and the IGZO-based TFT 2 having excellent stability of the element 201135853 37524pif. Hereinafter, the method of manufacturing the TFT 2 will be described in detail. First, the substrate is prepared as shown in FIG. 3A. B. After forming the gate electrode 21 including η+Si or the like, the gate insulating film 31 is formed. The substrate B is not particularly limited, and the same substrate as the substrate described in the above embodiment can be used. In the above, the active layer 11 is produced by the method for producing an IGZO-based amorphous oxide semiconductor film of the present invention. Therefore, the active layer 11 can be produced at a temperature lower than the heat-resistant temperature of the resin substrate B. Therefore, a resin can be used. The flexible substrate is used as the substrate B. The gate insulating film 31 is not particularly limited to a case where the substrate B is a resin substrate, and a gate insulating film which can be formed at a temperature lower than the heat resistant temperature of the resin substrate B is required. As shown in Fig. 3B, an active layer 11 containing an IGZQ-based amorphous oxide film 1 (which may also contain unavoidable impurities) is formed. The method of forming the active layer 11 is as described in the above embodiment. For example, the back pressure is 5xl〇· In the case of 5 Pa, a good active layer U can be produced by an annealing treatment of 15 Å (: 220 ° C (heat resistance is 220 ° C). Then, as shown in Fig. 3C, on the active layer 11 Forming the source electrode 22 and Electrode 23. Finally, as shown in Fig. 3D, a protective film (insulating film) 32 is formed on the active layer 11, the source electrode 22, and the germanium electrode 23. The TFT 2 of the present embodiment can be manufactured by the above steps. In the field effect transistor (TFT) 2, the active layer 11 is produced by the method for producing an IGZO-based amorphous oxide semiconductor film according to the above-mentioned Japanese Patent Publication No. 2011-A No. 2011-35853, the entire disclosure of which is incorporated herein by reference. In the process, an IGZO-based field effect transistor having an IGZO-based active layer excellent in electrical stress and heat stability and excellent in element stability is manufactured at low cost. As described above, FIG. 4 shows that, for the conductive film and the insulating film, it is also possible to manufacture an arbitrary resistance value and electrical stress as well by optimizing the combination of the back pressure at the time of sputtering film formation and the annealing treatment temperature. An IGZO-based amorphous oxide film having good thermal stability. For example, the line diagram of ^ and ◊ of Fig. 4 (back pressure 6xl (T6pa, lxl〇-5pa: area with low back pressure (high vacuum)) has the following tendency: at an annealing temperature of 1 〇〇 C to 300 ° C There is a minimum value in the range, and then it is at 4 〇〇. The resistance value near 〇 rises to around lx 106, showing a substantially fixed value. Here, the resistance value near the minimum value is in the conductor area (resistance value is below iQ · cm, It is preferably 10 Ω · cm or less). Therefore, at a suitable temperature in the range of 1 〇〇 〇〇 3 〇〇 ° c under the back pressure of ixi 〇 -5 pa (the following formula (12)) (Annealing treatment is carried out under the following formula (2)) to produce an IGZO-based amorphous oxide film having a resistance value of a conductor region β lOO^T (°C) ^300 (2) ^ P (Pa) < 1χ1〇·5 (12) Further, similarly to the maximum value, the annealing treatment at a temperature near the minimum value reduces the influence of the in-plane uniformity of the annealing treatment temperature on the resistance value, so that the same effects as described above can be obtained. Therefore, as shown in Fig. 4, the annealing treatment temperature which can be displayed as a minimum value differs according to the 21 201135853 37524pif back pressure. Therefore, under the back pressure condition in which the annealing temperature of the minimum value is not clear, it is preferable to set the IGZO-based amorphous oxide layer into a film by setting the back pressure to a specific value. When the annealing treatment is performed in the range of i 〇〇 °c or more and 300 ° C or less, the resistance value of the IGZ lanthanum-based amorphous oxide layer depends on the annealing treatment temperature, and the temperature change rate of the resistance value becomes zero. (±5. (:) Annealing treatment. Contrary to the above, the pattern of 〇 and # in Fig. 4 (back pressure 5χι〇-4 Pa, 2χ1〇pa) has the following tendency: at the annealing temperature ~3〇〇.〇 The range has a maximum value. Then the resistance value decreases to around ιχ10-6 near 4〇〇°C, showing a substantially fixed value. The resistance value near the maximum value is in the insulator region (resistance value is 107Ω or more), so 5xl〇-4Pa or more back pressure (the following formula (13)) can be produced by annealing at a suitable temperature in the range of (1 to 300 ° C (the following formula (2)) An IGZO-based amorphous oxide film having a resistance value of an insulator region is formed. 1〇〇ST(°C)S3 G (2), 5xl〇-4^p (Pa) (13) Like the minimum value, the annealing treatment at a temperature near the maximum value has less influence on the resistance value due to the in-plane uniformity of the annealing treatment temperature. Preferably, the annealing temperature is determined according to the heat resistance of the substrate, and a back pressure having a maximum value in the vicinity of the annealing temperature is used, whereby an insulating film having high insulation uniformity and excellent reliability in the film surface can be produced. Heretofore, there has been no report on how the resistance value changes with respect to the annealing treatment temperature in accordance with the back pressure at the time of sputtering film formation. According to the above-described inventors' knowledge, by changing the combination of back pressure and annealing 22 201135853 37524 pif degrees, it is possible to manufacture not only an amorphous oxide (tetra) film having a resistance value of a semiconductor region but also a conductor region and The insulator region is surrounded by _ IGZ. (4) A crystalline oxide film, so that a IGZQ彡 amorphous oxide semiconductive film can be formed on a substrate by a simple method of changing only the back pressure in the sputtering film formation, and a specific resistance value having an insulator region and a conductor series can be formed. IGZ is an amorphous oxide film, and a field effect transistor is preferred. For example, after the IGZ lanthanum-based amorphous oxide film having the insulating region of the insulator region is formed on the substrate by the above-described manufacturing method, the back pressure of the smear-forming film can be reduced by the above-mentioned IGZ 〇 In the method for producing an amorphous stellite semiconductor film, a semiconductor layer is produced, and back-grinding is further reduced to produce a source electrode 22 and a non-electrode 23, or a contact layer thereof. At this time, the temperature of the annealing treatment is preferably such that the same temperature is used for all the layers, or the annealing temperature of the upper layer is smaller than the annealing temperature of the lower layer. In terms of simplification of the process, it is preferred to produce as many layers as possible by the above-described method for producing a bismuth-based amorphous oxide film. As described above, the IGZ0-based amorphous oxide semiconductor film of the present invention The manufacturing method can be implemented by the low temperature (four) of τ, so the heat of the low = flexible substrate is also applicable. Therefore, the method of fabricating the field effect transistor of the present invention can be similarly performed by the shoulder blade. The lower layer process to produce the other layers constituting the TFT 2 can be applied to the manufacture of a thin film transistor (TFT) used for a flexible display or the like. The above embodiment is also applicable to a bottom gate type field effect transistor. High gate field effect transistor. A 23 201135853 D /JZ^pif [Examples] Examples and comparative examples of the present invention will be described. (Example 1) An InGaZn〇4 (at ratio) polycrystalline target is used, about i An IGZO film with a thickness of 50 nm was formed on a commercially available synthetic quartz substrate (thickness 1 mm, τ_4〇4〇 synthetic quartz substrate) of cm2 square. In order to investigate the effect of back pressure and annealing temperature on the resistance value of the IGZO film, Back pressure (the limit before film formation) Degree) is set to όχίο·6 Pa, lxi〇-5 Pa, 2xl〇-5 Pa, 5xl〇-5 Pa, 6.5xl〇-5 Pa, lxl (T4 Pa, 5xl (T4 Pa, 2xl〇·3 Pa) ' Prepare samples separately. At this time, the back pressure is set as follows: after the atmosphere is opened, the film forming chamber of the splashing device is vacuum-exhausted, and the ion vacuum blade provided in the sputtering device is used to confirm the desired arrival. The film formation conditions were started after the back pressure conditions. The other film formation conditions were: substrate temperature Ts = normal temperature, Ar/〇2 mixed environment (Ar flow rate: 3〇seem, 〇2 flow rate 0.25 seem), film formation pressure 〇8 Pa, substrate The pitch of the famous materials is 150 mm, the input power of the target is DC 50 W (IGZO), and the film formation time is about 19 minutes. After the film is reduced, the XRF (X-ray Fluorescent Analyzer) is used for annealing. The first five samples were measured for film thickness and composition. The results confirmed that any sample was In : Ga : Zn = 1 : 0.9 : 0.7, and the film thickness was about 50 nm. Then, using a hot plate at various annealing temperatures (l〇 〇°C, 150°C '200°C '250〇C ' 300°C > 350〇C '400°C '450〇C '500 C, 600°C) Annealing the sample for 5 minutes embodiment, using Hiresta 24 201135853 37524pif measured resistance value (manufactured by Mitsubishi Chemical, MCP-HT45〇 (the URS probe type)) (resistivity). The result is shown in Fig. 4. Fig. 4 shows, for example, that when the annealing treatment temperature is 25 Å <>, the resistance value has a change of about 9 digits according to the boiling pressure condition, which is confirmed by Fig. 4, by optimizing the back of the film during sputtering. By pressing and annealing the treatment temperature, an IGZ oxide film having a resistance value in the conductor region to the insulator region can be produced.
為調查濺鍍成膜時的背壓對膜特性的影響，藉由ATR 法（attenuated total reflectance method，減弱全反射法）對 濺鍍成膜後未經退火處理的5種樣品以及用作參考的石英 基板實施表面的FT-IR測定（Therm〇Fisher製造的Nk〇le't 4700)。將其結果示於圖5。如圖5所示，確認任一樣品均 觀，到來自0H基的伸縮振動的波峰（25〇〇 (^.1至4〇〇〇 cm·1範圍的寬波峰），隨著背壓變高其波峰面積增大。 此外，確認上述傾向即便於使用複數種乾材的共麟 時亦相同。 (比較例1 ) …除，背壓設為pa的固定條件，將成膜氣體的 氧氣流量變為〇·25 sccm、0.33 seem、0.4 seem以外，藉由 與實例1相_方式製造脱0非晶氧化_膜的樣^， 於與實例1相同的退火條件下進行退火，測定各自的電阻 值。將其結果示於圖6。 如圖6所示’確認藉由增加氧氣流量， 脱〇薄_電阻值增高，但藉由在25Gt下進行退= 25 201135853 J / -/厶-Tpif 理，任一樣品的電阻值均成為極小值，電阻降至導體區域。 【圖式簡單說明】 ' 圖1是模式性地表示在濺鍍成膜時改變背壓時的成膜 裝置中的含水量與所形成的IGZ0系非晶氧化物簿 ' 含水量賴係_。 m + # 圖2是表示半導體膜的載子密度與電阻率的關係的 圖。 、 圖3A是表示本發明的一實施形態的半導體裴置（薄 膜元件）的製程的截面圖（1)。 ‘ 圖3B是表示本發明的一實施形態的半導體 程的截面圖（2)。 ϋ 圖3C是表示本發明的一實施形態的半導體裝置的 程的截面圖（3)。 圖3D是表示本發明的一實施形態的半導體 程的截面圖（4)。 ' 圖4是表示實例1中於不_壓下猶成膜的ι〇ζ〇 系非晶氧化物薄膜的電阻值與退火處理溫度的關係的圖。 圖5是表不1 4所示的機鑛成臈後的IGZO系非晶氧 化物薄膜表面的ΟΗ基的峰值波長附近的汉光譜的圖。 圖6是1批較例1中以抑氧氣流量舰成膜的 IGZO系非晶氧化物薄_電阻值與退讀理溫度的關係 的圖。 圖7是專利文獻1的圖4。 26 201135853 37524pif 【主要元件符號說明】 1 : IGZO系非晶氧化物半導體膜（半導體膜） 2 :場效電晶體（薄膜電晶體：TFT) 11 :活性層 21 :閘電極 22 :源電極 23 :汲電極 31 :閘極絕緣膜 32 :保護膜 B:成膜基板 27In order to investigate the effect of back pressure on the film characteristics during sputtering film formation, the ATR method (attenuated total reflectance method) was used to treat five samples which were not annealed after sputtering and used as a reference. The quartz substrate was subjected to FT-IR measurement of the surface (Nk〇le't 4700 manufactured by Therm〇 Fisher). The result is shown in Fig. 5. As shown in Fig. 5, it is confirmed that any sample is observed, and the peak of the stretching vibration from the 0H group (25 〇〇 (wide peak of the range of ^.1 to 4〇〇〇cm·1) becomes higher as the back pressure becomes higher. In addition, it is confirmed that the above tendency is the same even when a plurality of common materials are used. (Comparative Example 1) ... except that the back pressure is set to a fixed condition of pa, the oxygen flow rate of the film forming gas is changed. Except for 〇·25 sccm, 0.33 seem, and 0.4 seem, a sample of the amorphous oxide film was formed by the same method as in Example 1, and annealed under the same annealing conditions as in Example 1, and the respective resistance values were measured. The result is shown in Fig. 6. As shown in Fig. 6, it is confirmed that by increasing the oxygen flow rate, the 〇 _ resistance value is increased, but by retreating at 25 Gt = 25 201135853 J / - / 厶 - Tpif theory, The resistance value of any sample is extremely small, and the resistance is reduced to the conductor area. [Simplified description of the drawing] 'Fig. 1 is a schematic diagram showing the water content in the film forming apparatus when the back pressure is changed during sputtering film formation. The formed IGZ0-based amorphous oxide book 'water content is _. m + # Figure 2 shows the semiconductor film FIG. 3A is a cross-sectional view (1) showing a process of a semiconductor device (thin film device) according to an embodiment of the present invention. FIG. 3B is a view showing an embodiment of the present invention. Fig. 3C is a cross-sectional view (3) showing a process of a semiconductor device according to an embodiment of the present invention. Fig. 3D is a cross-sectional view showing a semiconductor process according to an embodiment of the present invention. 4) Fig. 4 is a graph showing the relationship between the resistance value of the ITO-based amorphous oxide film of the film formed in Example 1 and the annealing treatment temperature in Fig. 1. Fig. 5 is a table showing The graph of the Han spectrum near the peak wavelength of the sulfhydryl group on the surface of the IGZO-based amorphous oxide film after the formation of the alloy is shown in Fig. 6. Fig. 6 is an IGZO-based amorphous film formed by the oxygen suppression flow ship in the first batch of Example 1. Fig. 7 is a diagram showing the relationship between the oxide thinness_resistance value and the readout temperature. Fig. 7 is Fig. 4 of Patent Document 1. 26 201135853 37524pif [Description of main components] 1 : IGZO-based amorphous oxide semiconductor film (semiconductor film) 2 : Field effect transistor (thin film transistor: TFT) 11 : active layer 2 1 : gate electrode 22 : source electrode 23 : germanium electrode 31 : gate insulating film 32 : protective film B : film forming substrate 27