KR101449278B1 - Graphene growth method using semiconductor - Google Patents

Abstract

A graphene growth method using semiconductor of the present invention comprises a step of preparing a structure including a conductor layer; an insulator layer arranged on the conductor layer; a non-crystalline carbon layer disposed on the insulator layer, and a semiconductor layer arranged on the phase of the carbon layer; and a step of growing the carbon layer into a graphene by heat treating the structure while applying voltage between the conductor layer and the semiconductor layer.

Description

[0001] The present invention relates to a graphene growth method using semiconductor,

The present invention relates to a method for producing graphene, and more particularly, to a graphene growth method using a semiconductor capable of forming graphene at a low temperature.

Graphene is a two-dimensional hexagonal carbon crystal 2-dimensional hexagonal crystalline carbon structure with a thickness of one atom, and is a zero-gap semiconductor having excellent electrical, thermal and optical characteristics. In other words, graphene is not only structurally and chemically stable but also has a carrier mobility of 100,000 cm ² V ^-1 s ^-1 at room temperature (15-25 ° C.) And has attracted attention as a new electronic device to replace silicon in the future.

Methods for producing graphene having excellent physical properties as described above include a mechanical peeling method, a chemical peeling method, an epitaxy synthesis method, and a chemical vapor deposition (CVD) method.

The mechanical peeling method is a method of separating graphene by mechanical force in graphite crystals composed of a weak bond of van der Waals force between layers. This is possible because electrons in graphene's π-orbital are spread out over the surface and have a smooth surface. In the early days, these characteristics were used to make microscopic sized graphite crystals on the scanning probes and then slip on the substrate to create single layer graphene. Thereafter, a method of separating the single-layer graphene using the adhesive force of the scotch tape was used.

The mechanical peeling method as described above has facilitated diffusion of early graphene research because of its simplicity. However, the size of graphene obtained by the mechanical peeling method is usually within a few tens of micrometers. Particularly, the method using scotch tape has a problem that graphene and various layers of graphite are easily broken in the process of depositing from a scotch tape onto a substrate. Therefore, the mechanical peeling method is not suitable for use in manufacturing a large-sized device.

The chemical peeling method is a method in which graphene pieces separated from graphite crystals are dispersed in a solution by a chemical method, spin-coated on the substrate, and then the graphene is obtained by reducing the graphite oxide or removing impurities sticking to the surface Method. That is, graphite is oxidized and then broken through ultrasonic waves to form graphene oxide dispersed in an aqueous solution, and the graphene is formed through a process of returning it to graphene using a reducing agent such as hydrazine.

The above chemical peeling method has an advantage that graphene can be produced in a large area and in a large amount regardless of the type and structure of the substrate. However, since the chemical peeling method can not completely reduce the graphene oxide, the physical properties such as electrical properties are deteriorated compared to other methods, and graphene may be greatly damaged due to various complicated chemical processes. To improve this, a method of dispersing by using a surfactant or the like without using an oxidation process may be used. In this case, however, the layer resistance between the small micrometer-sized graphene pieces fails to achieve a practical level of sheet resistance.

The epitaxial synthesis method is a method in which a polar surface such as silicon carbide (SiC) and ruthenium (Ru) having a polar structure is heat-treated at a high temperature to differentially evaporate silicon on the surface, And growing graphene along the surface texture. In the case of SiC, the carbon contained in the crystal grows into graphene while being separated to the surface. In the case of Ru, adsorbed graphene diffuses from the surface and grows into graphene.

By using the epitaxial synthesis method as described above, it is possible to synthesize a graphene film having a uniform crystallinity up to the wafer size. However, graphene grown by this method has poor electrical properties than graphene grown by mechanical stripping or chemical vapor deposition. In addition, the epitaxial synthesis method is disadvantageous in that the silicon carbide wafer itself is expensive, and it is very difficult to manufacture a silicon carbide wafer having a large size. In addition, since the domain size of graphene grown from silicon carbide is very small, it is difficult to fabricate a large-sized device using the epitaxy synthesis method.

The chemical vapor deposition method is a method of synthesizing graphene using a transition metal that adsorbs carbon well at a high temperature as a catalyst layer, which is also referred to as a catalyst method. That is, after a catalyst layer of nickel / copper or the like is deposited on a substrate, the carbon is reacted with a methane / hydrogen mixed gas at a high temperature of about 1000 ° C or more to adsorb carbon on the catalyst layer, To form a graphene crystal structure. The graphene thus formed is separated from the substrate by removing the catalyst layer, and is used according to the intended use.

The chemical vapor deposition method as described above has an advantage that graphene having much improved sheet resistance and transparency characteristics than the chemical peeling method can be produced. However, in the chemical vapor deposition method, since it is difficult to remove graphene from the catalyst layer after growing graphene on the surface of the catalyst layer, the crystallinity is lower than that of graphene obtained from the crystallized graphite, Is high. Particularly, since the chemical vapor deposition method includes a chemical etching process and a process using a PR polymer, damage due to graphene damage due to an etching process and contamination of residual PR polymer may occur, and as the processes are added The process time becomes longer. That is, according to the chemical vapor deposition method, in order to remove the nickel metal layer adhering to the graphene, a nickel layer which is only tens or several hundreds of nanometers must be chemically etched gradually from the side having a very small cross-sectional area. It takes a long time to diffuse and it is not effective in obtaining large area graphene.

It is an object of the present invention to provide a graphene growth method using semiconductors capable of growing graphene at a low temperature and capable of maintaining excellent physical properties possessed by graphene in order to solve the above problems .

According to another aspect of the present invention, there is provided a method of growing a graphene film using a semiconductor, comprising the steps of: (1) forming a conductive layer, a nonconductive layer on the conductive layer, an amorphous carbon layer on the non- Preparing a structure including a semiconductor layer provided on the carbon layer, and (2) annealing the structure while applying a voltage between the conductor layer and the semiconductor layer to grow the carbon layer into a graphene layer.

In addition, the step of preparing the structure may further include the step of patterning the semiconductor layer.

In particular, the semiconductor layer preferably includes a plurality of n-type semiconductor regions and a p-type semiconductor region.

In addition, the n-type semiconductor region and the p-type semiconductor region may be formed in a mesa structure.

The step of growing the carbon layer into a graphene layer may further include a step of selectively applying a voltage to the n-type semiconductor region and the p-type semiconductor region.

The graphene growth method using the semiconductor according to the present invention having the above-described structure has the following effects.

(1) The process is simple. That is, in the case of graphene grown by the conventional chemical vapor deposition method (catalyst method), since graphene is formed on the catalyst metal layer, a process for removing the catalyst metal layer is required to implement the semiconductor device, Since the graphene is grown on the nonconductor layer, the step of etching and removing the metal layer is not necessary, so that the graphene can be easily grown.

(2) Graphenes can be grown at low temperatures. That is, unlike the conventional chemical vapor deposition method, which is performed at a high temperature of 1000 ° C or higher, graphene can be grown at a low temperature of 200 ° C to 1000 ° C according to the use of a semiconductor according to the present invention. Can be maintained, and the time and cost required for graphene fabrication can be saved.

(3) High utilization. That is, the structure of the metal layer-insulator layer-graphene layer-semiconductor layer formed as a result of the present invention can be utilized as a semiconductor device using graphene as it is.

(4) Optionally, graphene can be grown. A voltage can be selectively applied to a desired semiconductor region in a semiconductor layer including a plurality of p-type semiconductor regions and an n-type semiconductor region to form a graphene layer.

1 illustrates a method of growing a graphene using a semiconductor according to an embodiment of the present invention.
2 is a view showing a case where a semiconductor layer includes a plurality of n-type semiconductor regions and a p-type semiconductor region in a graphene growth method using a semiconductor according to an embodiment of the present invention.
FIG. 3 illustrates a plurality of n-type semiconductor regions and a p-type semiconductor region formed in a mesa structure in a graphene growth method using a semiconductor according to an embodiment of the present invention.
4 (a) to 4 (d) illustrate growth of a graphene layer by applying a voltage in a graphene growth method using a semiconductor according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, . In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

Furthermore, terms used herein are for the purpose of illustrating embodiments and are not intended to limit the present invention. In this specification, the singular forms include plural forms as the case may be, unless the context clearly indicates otherwise. &Quot; comprises "and / or" comprising "used in the specification do not exclude the presence or addition of one or more other elements other than the stated element. Unless defined otherwise, all terms used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. In addition, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1, a method for growing a graphene using a semiconductor according to an embodiment of the present invention includes a conductor layer 110, a nonconductor layer 120 provided on the conductor layer 110, (S10) preparing a structure 100 including an amorphous carbon layer 130 provided on the carbon layer 130 and a semiconductor layer 140 provided on the carbon layer 130; And growing the carbon layer 130 into a graphene layer 160 by applying a voltage between the conductor layer 110 and the semiconductor layer 140 by heat treating the structure 100.

In step S20, the structure 100 is preferably subjected to a heat treatment in a vacuum-free chamber.

The conductor layer 110 is preferably formed of a conductive material such as Au, Ni, Ti, or Cr. In addition, the conductor layer 110 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO) a transparent conductive oxide (TCO) such as aluminum zinc oxide and indium zinc tin oxide (IZTO), a conductive polymer, and a graphene.

The nonconductor layer 120 is formed on the semiconductor layer 140 by a voltage applied between the conductor layer 110 and the semiconductor layer 140 so that the charge of the static electricity can be induced in the interface between the carbon layer 130 and the semiconductor layer 140 Lt; / RTI > Particularly, when the structure 100 in which the graphene layer 160 is grown through the step S20 is utilized as a semiconductor device, the nonconductor layer 120 is formed so that the charge carriers (electrons or holes) tunneling). At this time, when the thickness of the nonconductor layer 120 is too thin, the tunneling of the charge carriers occurs too much and the switching characteristics deteriorate. Also, when the thickness of the nonconductor layer 120 is too thick, tunneling of charges does not occur easily. Therefore, the nonconductor layer 120 should be designed in consideration of this, and is preferably formed to a thickness of several nm to several hundreds nm. Particularly, it is preferable that the nonconductor layer 20 is made of an organic material such as silicon oxide (Si _x O _y ), a metal oxide, a high K nonconductive dielectric, and plastic as a material having a large energy band gap and a large dielectric constant .

Specifically, the nonconductor layer 120 may be formed of an insulating material such as a polymer or glass, but the material thereof is not limited thereto. For example, the material of the nonconductor layer 120 may be a silicon oxide (Si _x O _y ), an aluminum oxide (Al _x O _y ), a hafnium oxide (Hf _x O _y ), a zirconium oxide (Zr _x O _y ) (y _x O _y), lanthanum oxide (La _x O _y), tantalum oxide (Ta _x O _y), praseodymium oxide (Pr _x O _y), and titanium oxide (Ti _x O _y), aluminum silicon oxide (AlxSi _y O _z ), zirconium silicon oxide (ZrSi _x O _y ), and hafnium silicon oxide (HfSi _x O _y ), or a combination thereof. The High K nonconductive dielectric includes, but is not limited to, one or more materials selected from the group consisting of HfO ₂ , ZrO ₂ , TiO ₂ and Ta ₂ O ₅ . In particular, when the material of the nonconductor layer 120 is a polymer or glass, a structure in which a graphene layer 160 is grown on a polymer or glass can be obtained, and the structure is useful as a semiconductor device.

The amorphous carbon 130 is carbon having both sp3 bond and sp2 bond and has lower electrical conductivity than graphite and is grown as a graphene layer 160 through step S20. The amorphous carbon layer 130 may be formed by physical vapor deposition (PVD) such as sputtering, molecular beam epitaxy (MBE) and thermal evaporation, or chemical vapor deposition (Chemical Vapor Deposition, CVD). In addition, the amorphous carbon layer 130 may be formed to have a thickness of several nm to several tens nm, for example, a thickness of 1 nm to 30 nm.

The semiconductor layer 140 may be formed of a semiconductor having various energy bandgaps of various sizes (Si, aSi, SiC, aSiC, Ge, GaAs, GaN, InGaAs, AlGaAs, and metal oxides). In particular, the semiconductor layer 140 may include an n-type semiconductor region 141 doped with an n-type and a p-type semiconductor region 142 doped with a p-type, as shown in FIG. 2 A plurality of the n-type semiconductor regions 141 and the p-type semiconductor regions 142 may be formed.

Accordingly, it is preferable that the method further comprises a step (S21) of selectively applying a voltage to the n-type semiconductor region 141 and the p-type semiconductor region 142 in operation S20. That is, a voltage is applied to a region where the graphene layer 160 is to be grown in the plurality of n-type semiconductor regions 141 and the p-type semiconductor regions 142 to induce charges, and then heat treatment is performed. Thereby allowing the graphene layer 160 to grow. In this case, the n-type semiconductor region 141 and the p-type semiconductor region 142 are preferably formed in a mesa structure as shown in FIG.

The method of growing a graphene using a semiconductor according to the present invention may further include patterning (S11) patterning the semiconductor layer 140 in step S10, To grow nano-graphene. That is, by patterning the semiconductor layer 140, the graphene layer 160 having the pattern can be grown on the nonconductor layer 120 through the step S20.

The temperature at which the heat treatment is performed in step S20 is preferably 200 deg. C to 1000 deg. C, which is a category in which the characteristics of the semiconductor layer 140 are not changed, but is not limited thereto. Particularly, as the amorphous carbon layer 130 is annealed at a low temperature in step S20, it takes more time to grow the amorphous carbon layer 130 into the graphene layer 160, and the crystalline domain of the graphene layer 160 is also reduced. Therefore, in order to increase the crystal domain size of the graphene layer 160, it is preferable to heat-treat the structure 100 at a temperature as high as possible within a range of 200 ° C to 1000 ° C.

Hereinafter, the process of implementing the graphene growth method using the semiconductor according to the present invention will be described in detail with reference to FIG.

4 (a), a non-conductive layer 120 is formed on a conductor layer 110 formed of a metal, an amorphous carbon layer 130 is deposited on the nonconductor layer 120, A structure 100 in which a semiconductor layer 140 is deposited on a carbon layer 130 is prepared.

A voltage V _G is applied to the conductor layer 110 and the semiconductor layer 140 to form the semiconductor layer 140 and the carbon layer 130 of the structure 100, Charge is induced electrostatically at the interface where the structure 100 is heated to grow an amorphous carbon layer 130 into the nano-graphene layer 160. The conductivity of the doped semiconductor layer 140 is controlled by the voltage applied to the conductor layer 110 and the semiconductor layer 140 so that the growth of the graphene layer 160 is also controlled by the conductor layer 110 and the semiconductor layer 140 ). ≪ / RTI >

4 (c), when the structure 100 includes a plurality of n-type semiconductor regions 141 and p-type semiconductor regions 142, as shown in Fig. 4 (d) A voltage is selectively applied between the semiconductor regions 141 and 142 and the conductor layer 110 and then the structure 100 is annealed to form the carbon layer 130 under the selected semiconductor layer 140 in the graphene layer 160). 4 (d), when a positive voltage is applied to all the semiconductor regions 141 and 142 and a negative voltage is applied to the conductor layer 110, The conductivity of the semiconductor region 141 is increased so that the carbon layer 130 under the n-type semiconductor region 141 is grown into the graphene layer 160 during the heat treatment.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be appreciated that one embodiment is possible. Accordingly, the true scope of the present invention should be determined by the technical idea of the claims.

100: Structure 110: Conductor layer
120: non-conductive layer 130: amorphous carbon layer
140: semiconductor layer 141: n-type semiconductor region
142: p-type semiconductor region 160: graphene layer

Claims (5)

Preparing a structure including a conductor layer, a nonconductive layer provided on the conductor layer, an amorphous carbon layer provided on the nonconductor layer, and a semiconductor layer provided on the carbon layer;
And annealing the structure while applying a voltage between the conductor layer and the semiconductor layer to grow the carbon layer into a graphene layer. The method according to claim 1,
Wherein the step of preparing the structure further comprises the step of patterning the semiconductor layer. The method according to claim 1,
Wherein the semiconductor layer comprises a plurality of n-type semiconductor regions and a p-type semiconductor region. The method of claim 3,
Wherein the n-type semiconductor region and the p-type semiconductor region are formed of a mesa structure. The method of claim 3,
The step of growing the carbon layer into a graphene layer comprises:
And selectively applying a voltage to the n-type semiconductor region and the p-type semiconductor region.

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