KR20100055098A - Electrical device having large-scale graphene layer and preparing method thereof - Google Patents

Electrical device having large-scale graphene layer and preparing method thereof Download PDF

Info

Publication number
KR20100055098A
KR20100055098A KR1020080114024A KR20080114024A KR20100055098A KR 20100055098 A KR20100055098 A KR 20100055098A KR 1020080114024 A KR1020080114024 A KR 1020080114024A KR 20080114024 A KR20080114024 A KR 20080114024A KR 20100055098 A KR20100055098 A KR 20100055098A
Authority
KR
South Korea
Prior art keywords
graphene
sapphire substrate
graphene layer
region
layer
Prior art date
Application number
KR1020080114024A
Other languages
Korean (ko)
Inventor
천승현
Original Assignee
천승현
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 천승현 filed Critical 천승현
Priority to KR1020080114024A priority Critical patent/KR20100055098A/en
Publication of KR20100055098A publication Critical patent/KR20100055098A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02527—Carbon, e.g. diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

Disclosed are a method for manufacturing an electronic device comprising efficiently epitaxially growing a large area graphene layer on a sapphire substrate, and an electronic device including the large area graphene layer thus formed.

Description

Electronic device having a large-area graphene layer and a method of manufacturing the same

The present invention relates to an electronic device comprising a large area graphene layer and a method of manufacturing the same.

Graphene is a two-dimensional sheet-like material with carbon atoms arranged in a honeycomb hexagonal lattice. Graphene is also the basic block of carbonaceous materials such as graphite.

Graphene has attracted great attention in the field of electronic devices because of its excellent properties. Among them, graphene has the potential to replace or supplement silicon due to its high carrier mobility and good current carrying capability, and can also be an alternative for interconnection. have.

Although several research groups have obtained more than one layer of graphene by mechanical exfoliation of graphite flakes using adhesive tape, the large area (millimeter or centimeter range lateral dimension) grown on the semiconductor substrate or the insulating substrate dimension) Graphene is required for industrial applications.

Several methods of growing graphene on a semiconductor substrate or an insulating substrate are known. One method is to heat the SiC single crystal to a sufficiently high temperature to evaporate Si atoms from the surface, leaving one or more layers of graphene [C. Berger et al., J. Phys. Chem. B, Vol. 108, p19912 (2004). This method is actually pyrolysis rather than epitaxial growth. Since the grain size of the graphene thus obtained is far smaller than that of graphene obtained by mechanical exfoliation, this method is not yet suitable for growing large-area graphene.

L.N. Pfeiffer outlined a method for epitaxial growth of graphene in US Published Patent Publication 2007/0187694 A1. In a preferred embodiment, this technique proposes hexagonal boron nitride (hexagonal BN) on a graphite substrate as a platform for graphene growth. However, this technique has not been realized yet and the step of epitaxially growing boron nitride on the graphite substrate complicates the whole process.

Therefore, there is still a need for an electronic device including a large area graphene layer and an efficient method of manufacturing an electronic device including a large area graphene layer to satisfy industrial demands.

It is therefore an object of the present invention to provide an electronic device comprising a large area graphene layer.

It is another object of the present invention to provide an efficient method of manufacturing an electronic device comprising a large area graphene layer.

One aspect of the present invention to achieve the above object is

Sapphire substrates; And

Provided is an electronic device including at least one epitaxially grown graphene layer formed on the sapphire substrate.

In one embodiment, the one or more layers of graphene may be made of single crystal having lateral dimensions of about 1 mm or more. In another embodiment, an insulating layer formed between the sapphire substrate and the graphene layer may be further included. An insulating layer may be further provided on the graphene layer.

Another aspect of the present invention to achieve the above object is

Sapphire substrates; Conductive layer patterns spaced apart from each other while exposing a portion of the sapphire substrate; And a graphene layer connecting the conductive layer patterns on the sapphire substrate.

Another aspect of the present invention to achieve the above object is

A field effect transistor, comprising: a sapphire substrate; A source region, a drain region, and a channel region connecting the source region and the drain region to each other formed on the sapphire substrate; And a gate region for applying a voltage to the channel region to control a current flow between the source region and the drain region, wherein the source region, the drain region, and the channel region are in one or more epitaxially grown graphene layers. Provided is a field effect transistor.

Another aspect of the present invention to achieve the above other object

(a) providing a sapphire substrate;

(b) epitaxially growing one or more layers of graphene by depositing carbon atoms evaporated on the sapphire substrate.

In one embodiment, the at least one graphene layer may be formed of a single crystal having a lateral dimension of about 1 mm or more by MBE or CVD method. In another embodiment, an insulating layer may be further formed on the sapphire substrate between the step (a) and the step (b). The insulating layer may include single crystal hexagonal nitride.

By using the epitaxial growth method of the graphene layer disclosed in the present invention, an electronic device including a large area graphene layer can be obtained simply and economically. In particular, the present invention does not require a boron nitride interlayer as in the Berger technique described above for high temperature pyrolysis or Pfeiffer techniques to grow the graphene layer. Because of the expansion of the nitride semiconductor industry, high quality and large size sapphire substrates of 6 inches or more in diameter are available at much lower prices than SiC substrates used in Berger technology and highly oriented graphite used in Pfeiffer technology.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic cross-sectional view of an electronic device 10 according to an embodiment of the present invention.

Referring to FIG. 1, the electronic device 10 includes at least one graphene layer 12 formed on the sapphire single crystal substrate 11. The graphene layer 11 is made of large area single crystal graphene. The lateral dimensions of this large area single crystal graphene may be at least about 1 mm and about 10 cm, but are limited by the size of the substrate and not by the content of the present invention. Such lateral dimensions are much larger than the typical lateral dimensions of graphene on the order of a few μm when using the epitaxial growth method disclosed in the above-mentioned US Patent Publication 2007/0187694 A1.

An insulating layer (not shown) may be further formed on the graphene layer 12. The lateral dimension of single crystal graphene means 1 mm. An insulating layer (not shown) may be further formed on the graphene layer 12.

The electronic device 10 having such a large area graphene layer 12 may be formed as follows.

First, the sapphire substrate 11 is prepared. Then, one or more layers of graphene layers 12 are epitaxially grown by depositing carbon atoms evaporated on the sapphire substrate 11. The sapphire substrate 11 may be used as it is obtained from a supplier, or may be annealed at a sufficiently high temperature for a sufficient time in a suitable atmosphere to have a flatter and / or cleaner surface. A sapphire substrate coated with a backside with a metal such as titanium may be used to maintain a uniform temperature throughout the entire wafer. Prior to growing the graphene layer 12, a preliminary heating may be performed in a chemical etch and / or cleaning step followed by a growth chamber.

Graphene growth can occur in any type of ultrahigh vacuum or high vacuum high vacuum chamber. 2 shows a schematic of an exemplary device that can be used to grow a graphene layer 12 on a sapphire substrate 11 in accordance with one embodiment of the present invention.

Referring to FIG. 2, the sapphire substrate 21 is placed on the metal holder 22 and covered by the metal mask 23. The metal mask 23 is fixed to the metal holder 22 by a screw 24. The metal holder 22 is introduced into the sample manipulator 25. The sample manipulator 25 can increase the sapphire substrate temperature as needed. A typical method is to heat the back side of the metal holder 22 to about 1000 ° C. by means of a heater 26 by means of radiation using heated filaments. If ultra high temperatures of about 1000 ° C. or more are required, a method of impinging an electron beam may be used. The sample manipulator 25 can be rotated during graphene growth to grow a more uniform high quality graphene layer.

Graphene layer 12 may be deposited by molecular beam epitaxy (MBE), chemical vapor deposition (CVD), or any other known technique. Initially, MBE is the preferred method because of its ability to control sub-monolayer thickness. Once the growth process mechanism is understood, faster and cheaper CVD methods can be used for mass production. Low pressure CVD methods are advantageous for controlling graphene layer thickness over other types of CVD methods.

Standard Knudsen cell type source 27 can be used for the graphene MBE. It consists of a crucible 271 comprising carbon 272 and a heating heater 273 around the crucible. Alternatively, carbon 272 may also be heated by the electron beam. A simpler and cleaner method is to use a carbon sublimation source 28 (eg SUKO model of Dr. Eberl MBE-Komponenten GmbH). Carbon may be supplied by heating the high purity graphite filament 281 surrounded by the graphite shielding.

Another cell may be installed in the chamber for doping purposes. Boron, aluminum, gallium, indium are suitable dopants for p-type doping. Nitrogen, phosphorus, arsenic and antimony are suitable dopants for n-type doping. Co-evaporation of such dopants with carbon is a preferred method.

Graphene epitaxy can be easily achieved due to the crystallographic compatibility between the graphene and the sapphire substrate 11.

That is, the sapphire substrate 11 is made of alpha-Al 2 O 3 , and the sapphire hexagon has a lattice constant in-plane lattice constant of 4.754 하는 which is about twice the 2.455 의 of graphene lattice constant. It has a hexagonal crystal lattice. Thus, sapphire is a very suitable lattice-matched substrate having a lattice constant about twice that of graphene, but with nearly the same crystal symmetry as graphene. The electrical insulation of sapphire satisfies the requirement to electrically isolate the graphene layer. Since the sapphire substrate 11 does not require in-situ high temperature annealing for oxide desorption, system requirements for the substrate temperature range can be alleviated.

3 shows the crystallographic structure of the (0001) plane 31 of the sapphire substrate 11 and the graphene 32 of one layer, respectively.

As can be seen in FIG. 3, since the lattice constant (4.754 kV) of the sapphire is about twice the lattice constant (2.455 kPa) of the graphene, the graphene layer 12 on the sapphire substrate 11 has a large area efficiently. Epitaxial growth is possible. The lattice mismatch between the sapphire substrate 11 and the graphene layer 12 is less than 3.3%. Thus, 2x2 commensurate epitaxy may occur between the sapphire substrate 11 and the graphene layer 12. Other arrangements on the (0001) plane or other sapphire plane of the sapphire substrate 12 are also possible. The grown graphene layer 12 may be annealed in-situ or x-situ to increase grain size. This may improve carrier mobility and other performance of the graphene layer 12.

As described above, the graphene layer formation method in the present invention is actually a growth method so that the graphene layer 12 thickness can be controlled by the amount of total carbon flux onto the sapphire substrate 11. This is in sharp contrast to the pyrolysis method described above by Berger et al., In which the graphene layer thickness is not well controlled.

The graphene layer 12 may be epitaxially grown on the sapphire substrate 11, and then another material including sapphire and nitride semiconductor may be epitaxially grown on the graphene layer 12. In this way, graphene properties can be adjusted to achieve optimal performance depending on the application. In addition, using this graphene epitaxy technology in combination with the above-described material sapphire crystallographically epitaxial, a multilayer structure comprising a graphene superlattice and at least one layer of graphene It can form efficiently. Growth of graphene and nitride semiconductors on the same sapphire substrate facilitates the integration of graphene and nitride semiconductors, thereby promoting the commercial application of graphene.

As can be seen from the above description, the graphene layer growth method using the sapphire substrate disclosed in the present invention requires an intermediate layer such as boron nitride used in US Patent Publication No. 2007/0187694 A1 to epitaxially grow the graphene layer. Do not However, the graphene layer growth method disclosed in the present invention does not exclude the use of boron nitride epitaxially grown on a sapphire substrate as an intermediate layer. This is because boron nitride also has excellent crystallinity with the graphene layer.

4 is a schematic cross-sectional view of an electronic device 50 according to another embodiment of the present invention.

Referring to FIG. 4, the electronic device 50 includes an insulating layer 52 and at least one graphene layer 53 on the sapphire single crystal substrate 51. Graphene layer 52 is shown above It consists of large area single crystal graphene formed by the method disclosed in the present invention. The insulating layer may be single crystal hexagonal nitride such as single crystal hexagonal boron nitride. An insulating layer (not shown) may be further formed on the graphene layer 53. This insulating layer may also be made of single crystal hexagonal nitride, such as single crystal hexagonal boron nitride.

According to the embodiments of the present invention shown in FIGS. 1 and 4, the graphene layers 12 and 53 in the electronic device may be patterned in a predetermined pattern using conventional methods well known in the art. Thereby, a desired structure can be formed.

5 shows a plan view of a simple test structure of a graphene layer.

Referring to FIG. 5, the graphene 41 film grown using a metal mask may have a cross shape. Gate structure 42 may be deposited on top of the graphene layer using conventional lithography techniques. The carrier density and carrier mobility of graphene layer 941 can be measured using an electrical property investigation method using the van der Pauw method under various gate voltages.

6 is a schematic cross-sectional view of a field effect transistor 60 according to another embodiment of the present invention.

Referring to FIG. 6, the field effect transistor 60 connects the sapphire substrate 62, the source region s, the drain region d, and the source region and the drain region formed on the sapphire substrate 62. The channel region c is provided. The source region s, the drain region d, and the channel region c are separate regions in the one or more epitaxially grown graphene layers 63 formed by the graphene layer growth method according to the present invention described above. Is formed. The source region s, the drain region d, and the channel region c may be formed by selective implantation and implantation amount control of impurity ions well known in the art. The source and drain electrodes Vs and Vd schematically shown are in electrical contact with the source region s and the drain region d, respectively. The resistance and conductivity of the channel region c is controlled by the gate region 66. The gate region 66 includes a patterned gate insulator 64 stacked on the channel region c and a gate electrode 65 stacked thereon. The common electrode 61 is formed under the sapphire substrate 62.

In operation, when the appropriate voltages Vs and Vd are applied to the source region s and the drain region d, respectively, current flows from the source region s to the drain region d or vice versa depending on the gate voltage Vg. Or blocked. If the gate voltage Vg increases sufficiently to deplete the channel region c to reduce electron transport, the channel resistance increases and the current decreases. The opposite phenomenon occurs when the gate voltage drops to Vg.

7 is a schematic cross-sectional view of the electronic neglect 80 according to another embodiment of the present invention.

Referring to FIG. 7, the electron neglect 80 may expose the sapphire substrate 81 and a portion of the sapphire substrate 81 while separating the conductive layer patterns 82 and the conductive layer formed on the sapphire substrate 81. And a graphene layer pattern 83 interconnecting the patterns 82.

The electronic device 80 may be manufactured in the following manner. After the conductive layer is deposited on the sapphire substrate 81, the conductive layer is deposited and then patterned to form a conductive layer pattern 82 separated from each other at intervals while exposing a portion of the sapphire substrate 81. The graphene layer pattern 83 interconnecting the conductive layer patterns 82 by epitaxially growing and then patterning the graphene layer on the entire surface of the sapphire substrate 81 on which the conductive layer patterns 82 are formed. To form. The conductive layer patterns 82 and the graphene layer pattern 83 may be formed through selective etching after deposition. Such techniques may be practiced by methods commonly performed in the art, including, for example, post deposition deposition, deposition through a mask, post deposition deposition on photoresist structures, and the like. .

1 is a schematic cross-sectional view of an electronic device 10 according to an embodiment of the present invention.

2 shows a schematic of an exemplary device that can be used to grow a graphene layer 12 on a sapphire substrate 11 in accordance with one embodiment of the present invention.

3 shows the crystallographic structure of the (0001) plane 31 of the sapphire substrate 11 and the graphene 32 of one layer, respectively.

4 is a schematic cross-sectional view of an electronic device 50 according to another embodiment of the present invention.

5 shows a plan view of a simple test structure of a graphene layer.

6 is a schematic cross-sectional view of a field effect transistor 60 according to another embodiment of the present invention.

7 is a schematic cross-sectional view of the electronic neglect 80 according to another embodiment of the present invention.

Claims (17)

Sapphire substrates; And And at least one epitaxially grown graphene layer formed on the sapphire substrate. The electronic device of claim 1, wherein the at least one graphene layer comprises a single crystal having a lateral dimension of about 1 mm or more. The electronic device of claim 1, further comprising an insulating layer formed between the sapphire substrate and the graphene layer. The electronic device of claim 3, wherein the insulating layer comprises single crystal hexagonal nitride. The electronic device of claim 3, further comprising a multilayer single crystal insulating layer on the graphene layer. The electronic device of claim 5, wherein the insulating layer comprises single crystal hexagonal nitride. The electronic device according to any one of claims 1 to 6, wherein the graphene layer has a predetermined pattern. Sapphire substrates; Conductive layer patterns spaced apart from each other while exposing a portion of the sapphire substrate; And And a graphene layer connecting the conductive layer patterns on the sapphire substrate. As a field effect transistor, Sapphire substrates; A source region, a drain region, and a channel region connecting the source region and the drain region to each other formed on the sapphire substrate; A gate region for applying a voltage to the channel region to control a current flow between the source region and the drain region, And the source region, the drain region and the channel region are formed in one or more layers of graphene epitaxially grown. (a) providing a sapphire substrate; (b) epitaxially growing at least one layer of graphene by depositing carbon atoms evaporated on the sapphire substrate. The method of claim 10, wherein the graphene layer is formed of a single crystal having a lateral dimension of about 1 mm or more. The method of claim 10, wherein the one or more graphene layers are formed by MBE or CVD. The method of claim 10, further comprising forming an insulating layer on the sapphire substrate between the steps (a) and (b). The method of claim 13, wherein the insulating layer comprises single crystal hexagonal nitride. The method of claim 13, further comprising forming a multilayer single crystal insulating layer on the graphene layer. The method of claim 15, wherein the insulating layer comprises single crystal hexagonal nitride. The method of claim 10, wherein by the steps (a) and (b), a sapphire substrate; And forming a structure including at least one epitaxially grown graphene layer formed on the sapphire substrate, (c) implanting impurity ions into predetermined first and second regions of the graphene layer to form a source region and a drain region; (d) forming a channel region connecting the two regions in the graphene layer between the source region and the drain region; And (e) applying a voltage to the channel region to form a gate region for controlling a current flow between the source region and the drain region.
KR1020080114024A 2008-11-17 2008-11-17 Electrical device having large-scale graphene layer and preparing method thereof KR20100055098A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080114024A KR20100055098A (en) 2008-11-17 2008-11-17 Electrical device having large-scale graphene layer and preparing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080114024A KR20100055098A (en) 2008-11-17 2008-11-17 Electrical device having large-scale graphene layer and preparing method thereof

Publications (1)

Publication Number Publication Date
KR20100055098A true KR20100055098A (en) 2010-05-26

Family

ID=42279630

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080114024A KR20100055098A (en) 2008-11-17 2008-11-17 Electrical device having large-scale graphene layer and preparing method thereof

Country Status (1)

Country Link
KR (1) KR20100055098A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012015267A2 (en) * 2010-07-30 2012-02-02 성균관대학교산학협력단 Method for preparing graphene, graphene sheet, and device using same
KR101150270B1 (en) * 2011-01-26 2012-06-12 고려대학교 산학협력단 Semiconductor device using graphene, and fabricating method for the device
WO2012057512A3 (en) * 2010-10-26 2012-07-26 주식회사 엘지실트론 Compound semiconductor device and method for manufacturing same
WO2012102559A2 (en) * 2011-01-26 2012-08-02 고려대학교 산학협력단 Semiconductor device using graphene, semiconductor device using carbon nano-material, semiconductor device array using graphene, and method for fabricating same
KR101245893B1 (en) * 2011-11-01 2013-03-20 금오공과대학교 산학협력단 Compound semiconductor devices and methods for fabricating the same
KR101275282B1 (en) * 2011-09-07 2013-06-18 성균관대학교산학협력단 Field-effect transistor using n-doped graphene and preparing method of the same
KR101332635B1 (en) * 2010-07-23 2013-11-25 한국기계연구원 Method for forming graphene pattern
US8927414B2 (en) 2011-06-27 2015-01-06 Samsung Electronics Co., Ltd. Graphene structure and method of manufacturing the graphene structure, and graphene device and method of manufacturing the graphene device
US9053932B2 (en) 2012-11-21 2015-06-09 Samsung Electronics Co., Ltd. Methods of preparing graphene and device including graphene
US10723620B2 (en) 2011-05-06 2020-07-28 Samsung Electronics Co., Ltd. Direct graphene growing method

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101332635B1 (en) * 2010-07-23 2013-11-25 한국기계연구원 Method for forming graphene pattern
WO2012015267A2 (en) * 2010-07-30 2012-02-02 성균관대학교산학협력단 Method for preparing graphene, graphene sheet, and device using same
WO2012015267A3 (en) * 2010-07-30 2012-05-18 성균관대학교산학협력단 Method for preparing graphene, graphene sheet, and device using same
WO2012057512A3 (en) * 2010-10-26 2012-07-26 주식회사 엘지실트론 Compound semiconductor device and method for manufacturing same
WO2012057517A3 (en) * 2010-10-26 2012-07-26 주식회사 엘지실트론 Compound semiconductor device and method for manufacturing a compound semiconductor
US9214596B2 (en) 2010-10-26 2015-12-15 Lg Siltron Inc. Compound semiconductor devices and methods for fabricating the same
US8878233B2 (en) 2010-10-26 2014-11-04 Lg Siltron Inc. Compound semiconductor devices and methods of fabricating the same
WO2012102559A2 (en) * 2011-01-26 2012-08-02 고려대학교 산학협력단 Semiconductor device using graphene, semiconductor device using carbon nano-material, semiconductor device array using graphene, and method for fabricating same
WO2012102559A3 (en) * 2011-01-26 2012-11-29 고려대학교 산학협력단 Semiconductor device using graphene, semiconductor device using carbon nano-material, semiconductor device array using graphene, and method for fabricating same
KR101150270B1 (en) * 2011-01-26 2012-06-12 고려대학교 산학협력단 Semiconductor device using graphene, and fabricating method for the device
US11407637B2 (en) 2011-05-06 2022-08-09 Samsung Electronics Co., Ltd. Direct graphene growing method
US10723620B2 (en) 2011-05-06 2020-07-28 Samsung Electronics Co., Ltd. Direct graphene growing method
US8927414B2 (en) 2011-06-27 2015-01-06 Samsung Electronics Co., Ltd. Graphene structure and method of manufacturing the graphene structure, and graphene device and method of manufacturing the graphene device
US9178020B2 (en) 2011-06-27 2015-11-03 Samsung Electronics Co., Ltd. Graphene structure and method of manufacturing the graphene structure, and graphene device and method of manufacturing the graphene device
KR101275282B1 (en) * 2011-09-07 2013-06-18 성균관대학교산학협력단 Field-effect transistor using n-doped graphene and preparing method of the same
KR101245893B1 (en) * 2011-11-01 2013-03-20 금오공과대학교 산학협력단 Compound semiconductor devices and methods for fabricating the same
US9053932B2 (en) 2012-11-21 2015-06-09 Samsung Electronics Co., Ltd. Methods of preparing graphene and device including graphene

Similar Documents

Publication Publication Date Title
KR20100055098A (en) Electrical device having large-scale graphene layer and preparing method thereof
US8084371B2 (en) Field effect transistors, methods of fabricating a carbon-insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor
CN101385126B (en) Devices including graphene layers epitaxially grown on single crystal substrates
US6896731B1 (en) P-type single crystal zinc-oxide having low resistivity and method for preparation thereof
US20120056201A1 (en) Insulated gate bipolar transistor
US9142623B2 (en) Substrate for epitaxial growth, and crystal laminate structure
CN111682061B (en) Nitride epitaxial wafer, preparation method thereof and semiconductor device
US9324839B2 (en) Graphene structure, graphene device including same, and method of manufacturing graphene structure
KR102395778B1 (en) Method of forming nanostructure, method of manufacturing semiconductor device using the same and semiconductor device including nanostructure
EP2862198A1 (en) Method for depositing a group iii nitride semiconductor film
KR101952501B1 (en) Transition metal chalcogenide based thin film having hetero junction, method of fabricating the same, and apparatus of fabricating the same
KR102232558B1 (en) Group 13 nitride composite substrate, semiconductor element, and production method for group 13 nitride composite substrate
JP4904541B2 (en) Substrate having organic thin film, transistor using the same, and method for producing them
US10727050B1 (en) Wafer-scale catalytic deposition of black phosphorus
US6703289B2 (en) Method for forming crystalline silicon layer and crystalline silicon semiconductor device
CN114477105B (en) Two-dimensional BiCuSeO nanosheet, preparation method thereof and semiconductor device
JPH04233277A (en) Transistor provided with layer of cubic boron nitride
JP2004343133A (en) Manufacturing method of silicon carbide, silicon carbide, and semiconductor device
US20050186435A1 (en) Light emitting device and method for manufacturing the same
CN114284349A (en) Graphene transistor and method of manufacturing graphene transistor
Yoshida et al. Selective-Area Growth of Vertical InGaAs Nanowires on Ge for Transistor Applications
US11492696B2 (en) Manufacturing method for semiconductor laminated film, and semiconductor laminated film
US11972947B2 (en) Manufacturing method for semiconductor laminated film, and semiconductor laminated film
KR101449278B1 (en) Graphene growth method using semiconductor
WO2023058493A1 (en) Method for achieving uniform carrier concentration in epitaxial layer, and structure created by means of said method

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination