KR101361440B1 - Transparent thin film transistor using metal thin film as diffusion sources and method thereof - Google Patents

Transparent thin film transistor using metal thin film as diffusion sources and method thereof Download PDF

Info

Publication number
KR101361440B1
KR101361440B1 KR1020130033474A KR20130033474A KR101361440B1 KR 101361440 B1 KR101361440 B1 KR 101361440B1 KR 1020130033474 A KR1020130033474 A KR 1020130033474A KR 20130033474 A KR20130033474 A KR 20130033474A KR 101361440 B1 KR101361440 B1 KR 101361440B1
Authority
KR
South Korea
Prior art keywords
thin film
active layer
metal
metal thin
zno
Prior art date
Application number
KR1020130033474A
Other languages
Korean (ko)
Inventor
마대영
Original Assignee
경상대학교산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 경상대학교산학협력단 filed Critical 경상대학교산학협력단
Priority to KR1020130033474A priority Critical patent/KR101361440B1/en
Application granted granted Critical
Publication of KR101361440B1 publication Critical patent/KR101361440B1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

The present invention is to improve the property of a transparent thin film transistor by using metal thin film as a diffusion source and doping a source and a drain region with a high concentration impurity. According to the present invention, A ZnO based active layer is formed. A ZnO based active layer is stacked on the ZnO based active layer. A thermal process is carried out in order to form an n-type thin film doped with a high concentration impurity. A source and a drain electrode are formed on the n-type thin film. Therefore, the transparent thin film transistor is manufactured.

Description

Transparent Thin Film Transistor Using Metal Thin Film As Diffusion Sources And Method Thereof}

The present invention relates to a transparent thin film transistor and a method of manufacturing the same, and more particularly, by doping a high concentration of impurities in the source and drain regions of the transparent thin film transistor using a metal thin film as a diffusion source to lower the contact resistance of the source and drain regions Increasing the electron mobility of the thin film transistor improves the characteristics of the transparent thin film transistor.

The transparent thin film transistor is a case where all the materials constituting the driving unit of the transistor are transparent, and in particular, an application field is possible when the material constituting the active layer is a transparent material such as ZnO. Transparent thin film transistors are expected to be applied to various applications such as light emitting devices, solar cells.

ZnO thin films are attracting much attention in their application to thin film transistors because they can obtain high mobility even when they are formed at low temperatures. In particular, since the resistance change is large depending on the oxygen content of the ZnO thin film, it is very easy to obtain desired physical properties, and the transparent property of ZnO also has the advantage of being applicable to transparent displays.

[1] has disclosed a technique of using ZnO as a transparent semiconductor material of a thin film transistor.

However, in the case of pure ZnO thin film having no dopant added thereto, when it is exposed to the air for a long time, there is a problem in that electrical properties change as the stoichiometry of Zn and O changes due to the influence of oxygen. In order to solve these disadvantages, dopants such as Al, Ga, In, etc. increase the charge concentration and electrical conductivity, and manufacture high quality thin films with high durability and longevity. have.

For example, in [2], a doped transparent metal oxide layer is locally doped to a transparent metal oxide layer by using a local ion implantation method or a diffusion method to form a high concentration impurity layer. A method of manufacturing a thin film transistor is known, in which a portion of a transparent metal oxide layer that is used as a pixel electrode and an undoped portion is used as a channel region. Local ion implantation, however, is advantageous for thinly doping impurities, but requires expensive equipment and may cause damage to the semiconductor lattice during ion implantation. In addition, the diffusion method is generally applied to a wide range of doping, and since it does not provide specific process conditions for locally doping high-concentration impurities, it may cause a lot of problems until its practical application.

As another example of the prior art, [3] has a Zn precursor adsorbed on a substrate by adsorbing a Zn precursor to the surface of the substrate by atomic layer deposition to form an atomic layer containing Zn and injecting a nitrogen precursor and an oxygen precursor, respectively; A method of forming a nitrogen-doped n-type ZnO semiconductor thin film using a surface chemical reaction between a nitrogen precursor and an oxygen precursor is provided. However, although ALD applied in [3] is advantageous for thin film deposition, it is difficult to apply widely to mass production line due to slow deposition rate because it has to repeat the process of periodically supplying raw materials and removing excess. There is this.

As another example of the prior art, a thin film transistor in which a metal-doped transparent conductive oxide thin film is applied is known, and the transparent conductive oxide thin film is formed of Mo and ZnO such that Mo is doped into the ZnO film simultaneously with ZnO film formation. Simultaneously depositing a Mo-doped ZnO film, coating the metal film with Mo on the Mo-doped ZnO film, and then heat-treating the Mo-doped ZnO film coated with the Mo metal film at a temperature of 250 to 350 ° C. It is formed to include.

In the above documents, in order to dope an impurity in a source region and a drain region, a method of depositing a heat treatment by depositing a metal film on an active layer (channel layer) or by simultaneously depositing a metal and a ZnO film is proposed. In the case of heat treatment in this manner, the interfacial adhesion between the metal film and the active layer can be partially improved, but it is difficult to expect a drastic reduction in contact resistance due to diffusion of metal atoms. In order to diffuse the metal atoms, the heat treatment temperature should be increased close to the melting point of the metal film. At this time, the metal thin film is evaporated into the air or peeled off due to the difference in thermal expansion coefficient with the active layer. There is a problem.

In order to solve these and other problems in connection with the prior art including the prior art described above, there is a need to selectively dopant high concentration impurities in the source and drain regions using a thermal diffusion method that is easy to implement and practical.

[Document 1] Korean Patent Registration No. 10-0490924 (2005.05.24) [Document 2] Korean Patent Registration No. 10-0847846 (2008.07.23) [Patent 3] Korean Patent Publication No. 10-2010-0055655 (2010.05.27) [Document 4] Korean Patent Registration No. 10-0999501 (2010.12.09)

none

One aspect of the present invention is an interface bonded to the active layer by depositing the active layer, the metal thin film and the active layer in a laminated structure in order to use a metal thin film as a diffusion source, and then selectively doping high concentration impurities in the source and drain regions using a thermal diffusion method It is to provide a highly transparent transparent thin film transistor by lowering the contact resistance of.

In the method of manufacturing a transparent thin film transistor using the metal thin film according to the embodiment of the present invention as a diffusion source, forming a ZnO-based first active layer, corresponding to the source electrode and the drain electrode in the upper region of the first active layer A metal thin film is formed on the plurality of regions, and a ZnO-based second active layer is formed on the metal thin film, and the laminated first active layer, the metal thin film, and the second active layer are heat-treated to form the first active layer and the second active layer. The metal atoms of the metal thin film are diffused to form an n-type thin film, and a source electrode and a drain electrode are formed on the n-type thin film.

In the transparent thin film transistor using the metal thin film according to the embodiment of the present invention as a diffusion source, the ZnO-based first active layer, the metal thin film and the ZnO-based second active layer are sequentially formed in a laminated structure, and the thermal diffusion method is used. An n-type thin film formed by diffusing the metal atoms of the metal thin film on the first and second active layers; And a drain electrode and a source electrode formed on the n-type thin film.

As described above, the present invention forms an n-type metal film by depositing an active layer, a metal thin film, and an active layer in a stacked structure, and then heat-treating it. By doping, the contact resistance of the interface bonded to the active layer may be lowered to increase the electron mobility, thereby improving the characteristics of the transparent thin film transistor.

1 is a cross-sectional view of a transparent thin film transistor using a metal thin film as a diffusion source according to an embodiment of the present invention.
2A to 2F are diagrams showing process steps of a method of manufacturing a transparent thin film transistor using a metal thin film as a diffusion source according to an embodiment of the present invention.
Figure 3 is a graph showing the XPS analysis results measured after depositing and heat-treating a metal thin film between the ZnO-based active layer according to an embodiment of the present invention.
4 is a graph showing a transfer characteristic curve for explaining electrical characteristics of a transparent thin film transistor using a metal thin film as a diffusion source according to an embodiment of the present invention.

The transparent thin film transistor using the metal thin film as a diffusion source according to the embodiment of the present invention forms a metal thin film on the ZnO-based active layer and forms a ZnO-based active layer thereon to heat-treat to form an n-type thin film doped with high concentration impurities. and forming source and drain electrodes on the n-type thin film.

The n-type thin film is formed in the source region and the drain region, respectively. The metal thin film used for the n-type thin film is a metal film of Group 3 element such as indium (In) or antimony (Sb) in a thickness range of 10 to 50 nm. It may be formed by vapor deposition. The thickness of the metal thin film may vary depending on the thickness of the transparent thin film.

As the metal thin film formed on the upper and lower portions of the ZnO-based active layer is subjected to heat treatment, the metal atoms of the metal thin film diffuse into the upper and lower ZnO-based active layers to form an n-type thin film doped with high concentration impurities. Depending on the type of thin film transistor, an n-type thin film may be formed on the ZnO-based active layer, or an n-type thin film may be formed on the source and drain electrodes.

The transparent thin film transistor according to the present invention may have a structure as shown in FIG. 1. Referring to FIG. 1, a gate electrode 20, a gate insulating film 30, an active layer 40, and an n-type thin film 50 having a stacked structure and a source / drain electrode 60 are sequentially formed on a substrate 10. It may have a staggered bottom-gate type structure is formed.

Although not shown in the embodiment, a staggered top-gate type structure, a coplanar bottom-gate type structure, and a coplanar top-gate type structure type) may have a structure.

For convenience of description, the manufacturing process of each layer will be described in detail with reference to FIGS. 2A to 2F with reference to the transparent thin film transistor of the staggered top gate type structure of FIG. 1.

Glass, silicon, and plastics may be used as the substrate 10, but are not particularly limited as long as a transparent material may be used.

The gate electrode 20 on the substrate 10 may be a transparent oxide such as ITO, IZO, or the like, or various kinds of low-resistance metals or conductive polymers such as Mo, Pt, Ti, Ag, Al, Cr, Ni, etc. may be used. It is not limited to this. The gate electrode 20 is formed after patterning by a process such as sputtering, atomic layer deposition (ALD), or chemical vapor deposition (CVD) to a thickness conventional in the art.

The gate insulating layer 30 formed on the substrate 10 and the gate electrode 20 may be a transparent oxide or nitride such as SiNx, ATO, TiO 2 , AlOx, TaOx and other high-k materials. It may include any one or more of.

As shown in FIG. 2A, the ZnO-based active layer 40 formed on the gate insulating layer 30 serves as a channel layer of a source electrode and a drain electrode, and may be formed using a ZnO-based material such as sputtering and laser deposition. It may be formed to a conventional thickness in the art, for example, ZnO-based material may be selected from the group consisting of ZnInO, ZnSnO, ZnGaO and the like.

The n-type thin film 50 and the source / drain electrode 60 formed on the gate insulating film 30 are sequentially formed in a stacked structure, and the n-type thin film 50 according to FIGS. 2B to 2E is sequentially formed. After the formation, the source and drain electrodes 60 are formed thereon. Here, the n-type thin film 50 is a doped region of a source and a drain. First, as shown in FIG. 2B, the metal thin film 51 is formed in a plurality of regions corresponding to the source electrode and the drain electrode among the upper regions of the ZnO-based active layer 30. To form. The metal thin film 51 is formed by depositing a Group 3 metal including indium (In) and antimony (Sb). The thickness of the metal thin film is preferably in the range of 10 to 50 nm.

Then, a ZnO-based active layer 52 is laminated on the metal thin film 51 as shown in FIG. 2C. The ZnO-based material may be formed by a process such as sputtering or laser deposition using a ZnO-based material, for example, ZnO-based. The material may be one or more selected from the group consisting of ZnInO, ZnSnO, ZnGaO and the like.

Then heat treatment as shown in Figure 2d. The heat treatment here is carried out for 10 to 30 minutes at a temperature of 300 ℃ to 400 ℃. By heat treatment, the metal atoms of the metal thin film 51 are diffused into the lower ZnO active layer 40 and the upper ZnO active layer 52 to form an n-type thin film 50 doped with a high concentration of impurities as shown in FIG. 2E.

Then, as shown in FIG. 2F, source and drain electrodes 60 are formed on the n-type thin films 50 bonded to both sides of the channel layer 40, respectively.

Experimental results for determining the characteristics of the n-type thin film 50 formed by applying a thermal diffusion method of diffusing a metal atom by heat treatment was obtained as follows.

FIG. 3 shows a ZnO thin film, a metal thin film and a ZnO-based thin film, and a ZnO-based active layer respectively disposed on the upper and lower portions of a metal thin film formed by, for example, depositing indium (In) to a thickness of 10 to 50 nm. XPS analysis results after heat treatment for 10 to 30 minutes at 300 ℃ to 400 ℃ temperature for the structure. It can be seen from the graph of FIG. 3 that indium (In) is doped into the ZnO thin film.

4 is a graph showing a transfer characteristic curve for explaining the electrical characteristics of a transparent thin film transistor to which the n-type thin film according to the present invention is applied, and the interface contact resistance between the source and drain regions and the ZnO-based active layer is reduced through heat treatment. The drain current was increased, and the electron mobility was found to increase from 14 cm 2 / Vsec to 22 cm 2 / Vsec.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken as limitations. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

10: substrate
20: gate electrode
30: gate insulating film
40 ZnO-based active layer
50: n-type thin film
51: metal thin film
52: ZnO-based active layer
60: source electrode, drain electrode

Claims (8)

To form a ZnO-based first active layer,
Forming a metal thin film on a plurality of regions corresponding to the source electrode and the drain electrode of the upper region of the first active layer,
Forming a ZnO-based second active layer on the metal thin film,
Heat-treating the stacked first active layer, the metal thin film, and the second active layer to diffuse the metal atoms of the metal thin film to the first active layer and the second active layer to form an n-type thin film,
And a source electrode and a drain electrode formed on the n-type thin film.
The method of claim 1,
The metal thin film is a method of manufacturing a transparent thin film transistor using a metal thin film as a diffusion source, characterized in that formed by depositing a metal of the Group 3 element including indium and antimony.
The method of claim 1,
The thickness of the metal thin film is a method of manufacturing a transparent thin film transistor using a metal thin film as a diffusion source, characterized in that 10 to 50 nm.
The method of claim 1,
The heat treatment is a method of manufacturing a transparent thin film transistor using a metal thin film as a diffusion source, characterized in that performed for 10 to 30 minutes at 300 ℃ to 400 ℃.
The method of claim 1,
The ZnO-based first and second active layers are ZnInO, ZnSnO, ZnGaO a transparent thin film transistor using a metal thin film as a diffusion source, characterized in that at least one selected from the group consisting of a thin film transistor.
An n-type thin film formed by sequentially forming a ZnO-based first active layer, a metal thin film, and a ZnO-based second active layer in a stacked structure, and diffusing metal atoms of the metal thin film on the first and second active layers by thermal diffusion method. ; And
And a drain electrode and a source electrode formed on the n-type thin film. The transparent thin film transistor using a metal thin film as a diffusion source.
The method according to claim 6,
The metal thin film is a transparent thin film transistor using a metal thin film as a diffusion source, characterized in that formed by depositing a metal of the Group III element including indium and antimony.
The method according to claim 6,
The ZnO-based first and second active layers are ZnInO, ZnSnO, ZnGaO transparent thin film transistor using a metal thin film as a diffusion source, characterized in that at least one selected from the group consisting of.
KR1020130033474A 2013-03-28 2013-03-28 Transparent thin film transistor using metal thin film as diffusion sources and method thereof KR101361440B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020130033474A KR101361440B1 (en) 2013-03-28 2013-03-28 Transparent thin film transistor using metal thin film as diffusion sources and method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020130033474A KR101361440B1 (en) 2013-03-28 2013-03-28 Transparent thin film transistor using metal thin film as diffusion sources and method thereof

Publications (1)

Publication Number Publication Date
KR101361440B1 true KR101361440B1 (en) 2014-02-24

Family

ID=50270581

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020130033474A KR101361440B1 (en) 2013-03-28 2013-03-28 Transparent thin film transistor using metal thin film as diffusion sources and method thereof

Country Status (1)

Country Link
KR (1) KR101361440B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018049265A (en) * 2016-09-08 2018-03-29 グッドリッチ コーポレイション Apparatus and methods of electrically conductive optical semiconductor coating

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007004729A1 (en) 2005-07-06 2007-01-11 Semiconductor Energy Laboratory Co., Ltd. Light-emitting element, light-emitting device, and electronic device
KR20100028347A (en) * 2008-09-04 2010-03-12 한국전자통신연구원 Method for preparing metal doped transparent conductive oxide thin film and thin film transistor using the same
JP2010156963A (en) 2008-12-05 2010-07-15 Semiconductor Energy Lab Co Ltd Semiconductor device
KR20110003775A (en) * 2009-07-06 2011-01-13 주성엔지니어링(주) Metal oxide semiconductor thin film transistor and method for manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007004729A1 (en) 2005-07-06 2007-01-11 Semiconductor Energy Laboratory Co., Ltd. Light-emitting element, light-emitting device, and electronic device
KR20100028347A (en) * 2008-09-04 2010-03-12 한국전자통신연구원 Method for preparing metal doped transparent conductive oxide thin film and thin film transistor using the same
JP2010156963A (en) 2008-12-05 2010-07-15 Semiconductor Energy Lab Co Ltd Semiconductor device
KR20110003775A (en) * 2009-07-06 2011-01-13 주성엔지니어링(주) Metal oxide semiconductor thin film transistor and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018049265A (en) * 2016-09-08 2018-03-29 グッドリッチ コーポレイション Apparatus and methods of electrically conductive optical semiconductor coating
US11852977B2 (en) 2016-09-08 2023-12-26 Danbury Mission Technologies, Llc Apparatus and methods of electrically conductive optical semiconductor coating

Similar Documents

Publication Publication Date Title
JP5137146B2 (en) Semiconductor device and manufacturing method thereof
CN103872138B (en) Transistor, the method for manufacturing transistor and the electronic device including the transistor
US8071434B2 (en) Method of fabricating a thin film transistor using boron-doped oxide semiconductor thin film
US9396940B2 (en) Thin film semiconductors made through low temperature process
US9960281B2 (en) Metal oxide thin film transistor with source and drain regions doped at room temperature
KR102402547B1 (en) Graphene electronic device having channel including graphene islands and methods of fabricating the same
KR20080074515A (en) Thin film transistor and method for forming the same
JP2011124532A (en) Thin film transistor and method of fabricating the same
WO2015119385A1 (en) Thin-film transistor having active layer made of molybdenum disulfide, method for manufacturing same, and display device comprising same
JP2010123913A (en) Thin-film transistor and method of manufacturing the same
US9070779B2 (en) Metal oxide TFT with improved temperature stability
KR101361440B1 (en) Transparent thin film transistor using metal thin film as diffusion sources and method thereof
KR101539294B1 (en) Thin-Film Transistor with ZnO/MgZnO Active Structure
KR101417932B1 (en) Thin film transistor having double layered semiconductor channel and method of manufacturing the thin film transistor
KR102524882B1 (en) Thin film transistor including crystalline izto oxide semiconductor and fabrication method for the same
KR20100010888A (en) Method for preparing zto thin film, thin film transistor using the same and method for preparing thin film transistor
US20200303555A1 (en) Oxide semiconductor thin-films with content gradient
JP6327548B2 (en) Thin film transistor and manufacturing method thereof
KR20150128322A (en) Method for manufacturing thin film transistor
KR101249483B1 (en) Fabrication method of CuO thin film and TFT and it manufacturing the same method, CuO thin film transistor
TWI831682B (en) Thin film transistor and fabrication method thereof
KR102660923B1 (en) DOPED TIN OXIDE THIN FILE TRANSISTOR and manufacturing method thereof
JP2018014472A (en) Manufacturing method for semiconductor element
JP2013172031A (en) Semiconductor device and manufacturing method thereof
CN115136323A (en) Transistor, electronic device and method for manufacturing transistor

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20170111

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20180112

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee