KR101539294B1 - Thin-Film Transistor with ZnO/MgZnO Active Structure - Google Patents

Abstract

The present invention relates to a thin-film transistor with a ZnO/MgZnO active layer structure. The present invention relates to a thin-film transistor with a ZnO/MgZnO active layer structure, which comprises: an insulation substrate; a ZnO active layer, which is the first thin film formed on the insulation substrate; a MgZnO active layer, which is the second thin film formed on the ZnO active layer, which is the first thin film; a source contacting the MgZnO active layer, which is the second thin film; and a drain electrode. According to the present invention, it is found that the device performance of the thin-film transistor can be controlled by adjusting the thickness of the ZnO active layer, which is the first thin film, and the MgZnO active layer, which is the second thin film, and the critical thickness of the ZnO active layer, which is the first thin film showing the optimum electron mobility, can be calculated. In addition, the electron mobility of the thin-film transistor with a ZnO/MgZnO active layer structure is improved by 30% or greater over a single ZnO device, and the sub-threshold slope (S.S) of the thin-film transistor with a ZnO/MgZnO active layer structure is reduced by 50% or greater over a single ZnO device, leading to enhanced performance of the device and greater usability.

Description

[0001] The present invention relates to a thin film transistor having a ZnO / MgZnO active layer structure,

The present invention relates to a thin film transistor having a dual active layer structure, and more particularly, to a dual layer thin film transistor having an active layer structure that exhibits superior device performance over a single active layer structure.

2. Description of the Related Art In general, a thin film transistor (TFT) is used in a display device such as a liquid crystal display (LCD) and an organic light emitting diode (OLED).

Among them, there is a thin film transistor in which an active layer for forming a source, a drain, and a channel is formed of crystalline silicon (Crystalline Silicone). A thin film transistor used in a display device such as a liquid crystal display (LCD) or an organic light emitting diode (OLED) is formed by depositing silicon on a transparent substrate such as glass or quartz, forming a gate and a gate electrode, injecting a dopant into a source and a drain, And then forming an insulating layer.

The active layer constituting the source, drain and channel of the thin film transistor is usually formed by depositing a silicon layer on a transparent substrate such as glass by a chemical vapor deposition (CVD) method or the like. However, the silicon layer directly deposited on the substrate by CVD or the like has a low electron mobility as an amorphous silicon film.

As display devices require high operating speed and miniaturization, many methods are being studied to improve mobility and stability of a thin film transistor using an oxide semiconductor.

As a conventional technique, "a method for manufacturing a thin film transistor including a crystalline silicon active layer" of Korean Patent Registration No. 10-0390522 (filed on Dec. 1, 2000) includes a crystallized silicon active layer and a gate electrode, And a method of manufacturing a thin film transistor (TFT) in which an LDD region or an offset junction is formed in an active layer.

"A thin film transistor containing a polysilicon active layer, a manufacturing method thereof, and an array substrate" of Korean Patent Application Publication No. 10-2012-0127318 (filed on May 11, 2012) discloses an amorphous silicon layer Depositing and patterning the amorphous silicon layer to form an active layer including a source region, a drain region, and a channel region; Depositing an induction metal on the source region and the drain region; Performing a first heat treatment on the active layer on which the induction metal is deposited to cause the active layer to undergo crystallization under the action of the induction metal; Doping the source region and the drain region with a first impurity for collecting the induction metal; And performing a second heat treatment on the active layer after the doping so that the first impurity absorbs the guiding metal remaining in the channel region. The present invention also relates to a method of manufacturing a thin film transistor including such a polysilicon active layer.

The above conventional techniques relate to a single active layer thin film transistor in which the active layer is a single layer. In recent years, dual active layer thin film transistors, in which the active layer is double, are emerging for higher electron mobility.

Korean Patent Registration No. 10-0390522 Korean Published Patent Application No. 10-2012-0127318

The present invention relates to a thin film transistor having a dual active layer structure and an object of the present invention is to provide a double active layer thin film transistor having superior device performance (electron mobility, element stability) compared with a thin film transistor having a single active layer structure.

According to an aspect of the present invention, there is provided an active matrix substrate including an insulating substrate, a ZnO active layer that is a first thin film formed on the insulating substrate, a MgZnO active layer that is a second thin film formed on the ZnO active layer that is the first thin film, And a source electrode and a drain electrode which are in contact with the MgZnO active layer, which is a ZnO / MgZnO active layer.

It is preferable that the insulating substrate is one of silicon, plastic, and glass substrate.

The ZnO active layer, which is the first thin film, is preferably formed to a thickness of 1 nm to 100 nm.

In addition, the MgZnO active layer as the second thin film is preferably formed to a thickness of 1 nm to 100 nm.

The MgZnO active layer, which is the second thin film, is deposited by co-sputtering, and the MgZnO active layer, which is the second thin film, has a composition of 1 at% to 50 at% (atomic percent) desirable.

In addition, the amount of Mg in the MgZnO active layer as the second thin film is preferably controlled by varying the power applied to the MgZnO target during the co-sputtering deposition process.

In addition, it is preferable that ohmic contact is formed by contacting the MgZnO active layer, which is the second thin film, with Ti or Ni metal, and Au is deposited on the Ti or Ni metal to form the source and drain electrodes.

The Ti or Ni metal is preferably formed to a thickness of 1 nm to 20 nm.

Further, it is preferable that a ZnO active layer is further formed as a third thin film between the MgZnO active layer, which is the second thin film, and the source and drain electrodes.

The ZnO active layer, which is the third thin film, is preferably formed to a thickness of 1 nm to 100 nm.

According to the present invention, the device performance of the thin film transistor can be controlled by controlling the thickness of the ZnO active layer as the first thin film and the MgZnO active layer as the second thin film. As a result, it can be seen that the ZnO active layer It is possible to calculate the critical thickness value.

In addition, the thin film transistor of ZnO / MgZnO active layer structure improves the electron mobility by more than 30% and the sub-threshold slope (SS) by more than 50% have.

1 is a cross-sectional view of a thin film transistor having a ZnO / MgZnO active layer structure according to an embodiment of the present invention.
2 is a graph showing a UV-Vis measurement graph of a MgZnO active layer deposited by co-sputtering according to the power of ZnO and MgZnO target according to an embodiment of the present invention.
FIG. 3 is a graph showing a current-voltage (IV) graph of ohmic contact characteristics between MgZnO and a source and a drain electrode (Ti / Au) according to an embodiment of the present invention.
4 is a graph showing the output characteristics of a thin film transistor having a ZnO / MgZnO active layer structure according to an embodiment of the present invention.
5 is a graph showing a conduction characteristic of a thin film transistor of a ZnO / MgZnO active layer structure according to an embodiment of the present invention.

The present invention relates to a thin film transistor having a dual active layer structure, and more particularly, to a double-layered active layer thin film transistor having superior device performance (electron mobility, element stability) than a single thin film transistor having a single active layer structure.

A ZnO active layer that is a first thin film formed on the insulating substrate; a MgZnO active layer that is a second thin film formed on the ZnO active layer that is the first thin film; a source contacted with the MgZnO active layer that is the second thin film; And a drain electrode.

Particularly, it was found that the device performance of the thin film transistor can be controlled by controlling the thickness of the ZnO active layer as the first thin film and the MgZnO active layer as the second thin film. As a result, Thin film transistor with dual active layer structure that improved the device performance by reducing the sub-threshold slope (SS) by more than 30% and the sub-threshold slope (SS) by more than 50% will be.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 1 is a cross-sectional view of a thin film transistor having a ZnO / MgZnO active layer structure according to an embodiment of the present invention. 2 is a graph showing the UV-Vis measurement of the MgZnO active layer deposited by co-sputtering according to the power of the ZnO and MgZnO target according to an embodiment of the present invention. 3 is a graph of an ohmic contact characteristic current-voltage (I-V) between MgZnO and a source and a drain electrode (Ti / Au) according to an embodiment of the present invention. 4 is a graph illustrating an output characteristic of a thin film transistor having a ZnO / MgZnO active layer structure according to an embodiment of the present invention. FIG. 5 is a graph illustrating a conduction characteristic of a thin film transistor of a ZnO / MgZnO active layer structure according to an embodiment of the present invention.

As shown in the figure, the present invention provides a semiconductor device comprising an insulating substrate 100, a ZnO active layer 200 as a first thin film formed on the insulating substrate 100, a second thin film formed on the ZnO active layer 200 as the first thin film, And the source and drain electrodes contacted with the MgZnO active layer 300 as the second thin film.

First, the insulating substrate 100 will be described.

The insulating substrate 100 includes a ZnO active layer 200 as a first thin film, a MgZnO active layer 300 as a second thin film formed on the ZnO active layer as a first thin film, and a MgZnO active layer 300 as a second thin film, And the source and drain electrodes to be contacted are raised.

The structure of a typical thin film transistor consists of a gate electrode / insulating layer / source and drain electrodes. When a positive voltage is applied to the gate electrode, the hole is pushed by the repulsive force and the electrons are attracted. The channels through which these electrons can pass are forming. That is, a voltage must be applied so that a channel is formed in the gate. On the other hand, when a negative voltage is applied to the gate electrode, holes are accumulated instead of electrons, so that the current does not flow. The gate voltage at the time when the channel is formed and the current increases is referred to as a threshold voltage.

The insulating substrate 100 is obtained by insulating a substrate of a material selected from one of silicon, plastic and glass substrates. According to an embodiment of the present invention, an SiO ₂ insulating substrate 100 is formed by a dry oxidation method at 900 ° C. using a horizontal thermal oxidation furnace of an n ⁺ -Si silicon substrate. The n ⁺ -Si silicon into which a large amount of impurities are implanted serves as a gate electrode, and a portion where an insulating layer is formed by a dry oxidation method using a horizontal type thermal oxidation furnace serves as an insulating layer. That is, the insulating substrate 100 serves as a gate electrode including an insulating layer.

Next, the ZnO active layer 200, which is a first thin film formed on the insulating substrate 100, will be described.

The ZnO active layer 200 is located between the insulating substrate 100 and a MgZnO active layer 300, which is a second thin film to be described later. According to one embodiment of the present invention, the ZnO thin film was deposited by a co-sputtering deposition method (100 W power) with a 4 inch ZnO target.

The deposition conditions of the ZnO active layer 200 according to an embodiment of the present invention are as follows. And argon (Ar) gas was flowed through the mass flow controller (MFC) at 20 sccm into the chamber. The deposition pressure is 5 mTorr and the deposition temperature is 300 ° C.

The thickness of the ZnO active layer 200 to be formed under the above conditions is preferably 1 nm to 100 nm. The thickness can be driven by the device and is at least a minimum thickness (1 nm) as a thin film and is less than or equal to the thickness (100 nm) that is suitable for the purpose of a highly integrated transistor.

The thickness of 1 nm to 100 nm is a range including a critical thickness value showing optimum electron mobility to be described later, more preferably 5 nm to 30 nm, and still more preferably 10 nm. In addition, since the increase of the ZnO thickness (the distance by the gate electric field is distant), the improvement of the electrical characteristics by the formed high-density electrons is not large, so that the thickness is preferably limited to 100 nm or less.

As shown in Table 1, the device having the highest mobility according to an embodiment of the present invention was the best at 10 nm of ZnO and the lowest at 5 nm of ZnO. However, ZnO 20 nm and 30 nm devices showed similar values to ZnO thin film transistors.

In addition, the sub-threshold slope (SS) was calculated by the following equation.

The single ZnO thin film transistor exhibited a value of about 0.44 V / decade for the S.S value, while an increase of 0.72 V / decade for the ZnO 5 nm device. However, in case of ZnO 20 nm device, it is 0.22 V / decade, which is about half that of ZnO. Such a change significantly reduces the phenomenon such as electron trapping in the channel, thereby improving the electrical characteristics.

This phenomenon shows that in a transistor having a single active layer, a plurality of carriers are formed at the semiconductor and insulator boundaries depending on the gate voltage, thereby contributing to current flow. However, in the case of a dual active layer, current flow may occur not only at the semiconductor and insulator boundaries but also at the potential wells created by the difference in conduction band formed at the interface between MgZnO and ZnO, which may lead to low electron scattering, And a decrease in the sub-threshold slope (SS) due to the low electron trapping density.

In addition, the electrical properties of ZnO thin films (<10 nm) were not improved much, which is a problem of crystallinity of ZnO thin films during initial growth. However, at 10 nm or more, it showed improved electrical characteristics compared to a single active layer thin film transistor. Such a change shows a remarkable reduction of the phenomenon such as electron trapping in the channel, which shows excellent electrical conductivity. It can be seen that the improvement of the electrical characteristics due to the formed high-density electrons is not large as the distance by the gate electric field (the ZnO thickness increase) increases.

Therefore, it was found that the device performance of the thin film transistor can be controlled by controlling the thickness of the ZnO active layer, which is the first thin film. As a result, the critical thickness (about 10 nm) of the ZnO active layer, .

Next, the MgZnO active layer 300, which is a second thin film formed on the ZnO active layer 200 as the first thin film, will be described. The MgZnO active layer 300 is positioned between the ZnO active layer 200 and a source and drain electrode (or a ZnO active layer, which is a third thin film) to be described later.

The amount of Mg in the MgZnO active layer 300 may be in the range of 1 at% to 50 at% (atomic percent), and the amount of Mg in the MgZnO active layer 300 may be in the range of 1 at% And is controlled by varying the power applied to the MgZnO target during the co-sputtering deposition process.

According to an embodiment of the present invention, a ZnO target is fixed to a power of 100 W and a power is applied to a target of Mg _x Zn _{1 -x} O (x = 30 at%) at a range of 50 W to 200 W to perform co-sputtering -putputing). As the power increases, the composition ratio of Mg increases, and the photonic bandgap increases as shown in FIG. The increase in the photonic bandgap means that the difference (width) between the conduction band and the valence band of the MgZnO thin film is widened. When the bandgap of MgZnO is widened, band gap difference (band offset) occurs by subtracting the bandgap of ZnO at the heterojunction with ZnO. The conduction band offset and the valence band offset occur due to the difference. When the Mg composition increases, the band gap increases and the conduction band offset becomes larger. So that the electrons can be further constrained. It may be desirable to increase the density of two-dimensional electron gas (2DEG) by restricting more electrons, but the amount of Mg can not be increased unconditionally due to the difference in the crystal structure of ZnO and MgO.

In general, the technical significance of blue and ultraviolet light emitting diodes, laser diodes, and UV detector devices is wide bandgap semiconductors with ZnO based oxide semiconductors. In particular, when MgO is added to ZnO, the bandgap can be increased to 3.3 eV to 7.8 eV, and when the ZnO / MgZnO superlattice structure is used, the free exciton binding energy can be increased to over 100 meV Have. However, since MgO has a cubic structure with a crystal structure of ROCKSALT structure, it has a large limitation on the solubility when added to ZnO having a hexagonal structure.

Therefore, in this embodiment, a ZnO / MgZnO thin film is deposited on a silicon substrate by co-sputtering vapor deposition. The RF power was adjusted by adjusting the MgO target power and fixing the ZnO target. As a result, it can be seen that as the MgO target power is increased, the half width increases and the lattice constant decreases along the C-plane, and the UV Emission Peak Intensity decreases, And the activation energy is increased.

The thickness of the MgZnO active layer 300 to be formed under the above conditions is preferably 1 nm to 100 nm. The thickness can be driven by the device and is at least a minimum thickness (1 nm) as a thin film and is less than or equal to the thickness (100 nm) that is suitable for the purpose of a highly integrated transistor.

Next, the source and drain electrodes contacted with the MgZnO active layer 300, which is the second thin film, will be described. The source electrode and the drain electrode form an ohmic contact by contacting the MgZnO active layer 300 and the Ti or Ni metal 400 with the second thin film and Au 500 ).

The reason why the Au (500) is deposited on the Ti or Ni metal (400) is that the metal such as Ti is oxidized in the air to form an insulating film such as TiO ₂ , .

The present invention can be applied to top contact and bottom gate structures and vice versa top gate and bottom contact structures.

The driving principle of the thin film transistor of the ZnO / MgZnO active layer structure according to an embodiment of the present invention is as follows. An insulated substrate dry-oxidized at 900 ° C using a horizontal thermal oxidation furnace serves as a gate electrode and an insulating layer, and a ZnO / MgZnO active layer and source and drain electrodes are formed on the insulating substrate. When a voltage higher than a certain voltage is applied to an insulating substrate (= gate electrode), an electric field is formed in the thin film transistor element and a two dimensional electron gas (2DEG) between the insulating layer / ZnO active layer and ZnO / MgZnO A channel through which electrons can flow is formed and a current flows to the source and drain electrodes.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a thin film transistor having a ZnO / MgZnO active layer structure according to an embodiment of the present invention. ZnO and MgZnO thin films were deposited by controlling the deposition time so that each active layer had a thickness of about 50 nm. In the active layer thin film transistor, the ZnO layer is first grown in the range of about 5 to 30 nm, and one of the MgZnO thin films is grown in the range of 20 nm to 45 nm. Then, the active layer is etched through a first photolithography process. A second photolithography process is used to form the electrode pattern, and then a metal is deposited using a Ti / Au or Ni / Au metal to a thickness of about 10 nm to 50 nm using an electron beam (E-beam) evaporator, -Source and drain electrodes are formed by a lift-off method.

FIG. 2 is a graph showing a UV-Vis measurement of a MgZnO active layer deposited by co-sputtering according to a change in power of ZnO and MgZnO target according to an embodiment of the present invention, and Mg _x Zn _1-x O (x = 30 at%) Co-sputtering is performed by selecting power from 50 W to 200 W in the target. As the power increases, the composition ratio of Mg increases, and the photonic bandgap increases as shown in FIG. The increase in the photonic bandgap means that the difference (width) between the conduction band and the valence band of the MgZnO thin film is widened.

3 is a graph of an ohmic contact characteristic current-voltage (I-V) between MgZnO and a source and a drain electrode (Ti / Au) according to an embodiment of the present invention. In the current-voltage (I-V) graph, the current increases as the voltage increases.

4 is a graph illustrating an output characteristic of a thin film transistor having a ZnO / MgZnO active layer structure according to an embodiment of the present invention. As shown, the saturation I _DS current increases as V _GS increases from 0 V to 10 V. This phenomenon is characteristic of a typical n-type thin film transistor by electrons in the active layer. The output characteristics of a typical thin-film transistor are also shown.

FIG. 5 is a graph illustrating a conduction characteristic of a thin film transistor of a ZnO / MgZnO active layer structure according to an embodiment of the present invention. The V _DS gave 10.5 V and the V _GS changed the voltage from 10 V to 20 V. At V _DS = 0.5 V, the field effect mobility μ _FE was determined by the following equation.

Here, g _m is the maximum transconductance (Transconductance), W is a channel width, L represents the amount of charge in the channel length, Ci insulating film. The μ _FE of a single ZnO thin film transistor 5.74 cm ² V ^-1 s ^- a ^1, ZnO / MgZnO thin film transistor (the thickness of the ZnO 5 nm, 10 nm, 20 nm, 30 nm) is from 2.24 showed a value of 7.40 cm ² V ^-1 s ^-1. In addition, the sub-threshold slope (SS) was calculated by the following equation.

The single ZnO thin film transistor exhibited a value of about 0.44 V / decade for the S.S value, while an increase of 0.72 V / decade for the ZnO 5 nm device. However, in case of ZnO 20 nm device, it is 0.22 V / decade, which is about half that of ZnO. Such a change significantly reduces the phenomenon such as electron trapping in the channel, thereby improving the electrical characteristics.

division

μ _FE (cm ² V ^-1 s ^-1 )
SS (V / decade)
Single ZnO thin film transistor (60 nm)

5.74
0.44
ZnO / MgZnO thin film transistor (5 nm)

2.24
0.72
ZnO / MgZnO thin film transistor (10 nm)

7.40
0.24
ZnO / MgZnO thin film transistor (20 nm)

4.35
0.22
ZnO / MgZnO thin film transistor (30 nm)

5.04
0.27

Table 1 is a value obtained by using a formula that determines the electron mobility (μ _FE) and the slope (Sub-Threshold Slope, SS) below a threshold voltage. As shown in Table 1, the electron mobility of the double-formed ZnO / MgZnO thin film transistor (electron mobility μ _FE = 7.40 cm ² V ^-1 s ^-1 at a ZnO thickness of 10 nm in a ZnO / MgZnO thin film transistor) electron mobility than that of the device (electron mobility of the ZnO single thin film transistor 60 nm Fig ^{_{μ FE = 5.74 cm 2 V -1}} s -1) is improved by more than 30%, formed of a double-ZnO / MgZnO thin film transistor (ZnO / MgZnO thin film transistor Sub-Threshold Slope (SS) = 0.24 V / decade for a ZnO thickness of 10 nm) is higher than the electron mobility of a single ZnO device (a sub-threshold Slope, SS) = 0.44 V / decade) is reduced by 50% or more.

Accordingly, the thin film transistor of the ZnO / MgZnO active layer structure according to the present invention exhibits superior device performance (electron mobility, element stability) as compared with the thin film transistor of the single active layer structure of the prior art. In particular, It was found that the device performance of the thin film transistor can be controlled by controlling the thickness of the MgZnO active layer, and thus, the critical thickness value of the ZnO active layer, which is the first thin film having the optimal electron mobility, And it is expected that the utilization will be maximized by reducing the sub-threshold slope (SS) by 50% or more.

100: insulating substrate
200: ZnO active layer
300: MgZnO active layer
400: Ti or Ni metal
500: Au

Claims (10)

An insulating substrate;
A ZnO active layer that is a first thin film formed on the insulating substrate;
An MgZnO active layer as a second thin film formed on the ZnO active layer as the first thin film;
And source and drain electrodes contacted with the MgZnO active layer, which is the second thin film,
And a ZnO active layer is further formed as a third thin film between the MgZnO active layer and the source and drain electrodes, wherein the second thin film is a ZnO / MgZnO active layer. The semiconductor device according to claim 1, wherein the insulating substrate
Wherein the thin film transistor is one of silicon, plastic, and glass substrate. The method according to claim 1, wherein the ZnO active layer, which is the first thin film,
Wherein the active layer is formed with a thickness of 1 nm to 100 nm. The method of claim 1, wherein the MgZnO active layer, which is the second thin film,
Wherein the active layer is formed with a thickness of 1 nm to 100 nm. The method of claim 1, wherein the MgZnO active layer, which is the second thin film,
The ZnO / MgZnO active layer structure is formed by co-sputtering vapor deposition, and the MgZnO active layer, which is the second thin film, has a composition of 1 at% to 50 at% (atomic percent) transistor. The method according to claim 5, wherein the amount of Mg in the MgZnO active layer, which is the second thin film,
And the ZnO / MgZnO active layer structure is controlled by varying the power applied to the MgZnO target during the co-sputtering deposition process. The thin film transistor of claim 1, wherein the ZnO / MgZnO active layer structure comprises:
Wherein the first and second thin films are formed of an active layer of MgZnO and Ti or Ni metal to form an ohmic contact and source and drain electrodes of Au are formed on the Ti or Ni metal. Structure of Thin Film Transistor. The method of claim 7, wherein the Ti or Ni metal
Wherein the active layer is formed with a thickness of 1 nm to 20 nm. delete The method according to claim 1, wherein the ZnO active layer, which is the third thin film,
Wherein the active layer is formed with a thickness of 1 nm to 100 nm.

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