TWI508225B - 具有插入物之積體電路封裝系統及其製造方法 - Google Patents

具有插入物之積體電路封裝系統及其製造方法 Download PDF

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TWI508225B
TWI508225B TW099119412A TW99119412A TWI508225B TW I508225 B TWI508225 B TW I508225B TW 099119412 A TW099119412 A TW 099119412A TW 99119412 A TW99119412 A TW 99119412A TW I508225 B TWI508225 B TW I508225B
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integrated circuit
insert
hole
preformed
substrate
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TW099119412A
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TW201110268A (en
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Chanhoon Ko
Soo-San Park
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Stats Chippac Ltd
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Description

具有插入物之積體電路封裝系統及其製造方法
本發明大致關於積體電路封裝系統，且尤關於具有插入物之積體電路封裝系統。
元件的愈趨微型化、積體電路(IC)的較大封裝密度、較高的效能、與較低的成本是電腦工業進行的目標。半導體封裝結構持續朝向微型化前進，以增加封裝其中的元件密度，同時縮小由該半導體封裝結構所製成產品的尺寸。這是對於資訊與通訊產品的持續縮減尺寸、厚度、與成本並連同持續增加的效能的需求不斷增加的回應。
這些對於微型化的需要增加是特別顯著的，舉例來說，在例如行動電話、免持行動電話耳機、個人資料助理(PDA)、攝錄像機(camcorder)、筆記型電腦等等的可攜式資訊與通訊裝置中。所有這些裝置持續被做得更小與更薄以增進其可攜性。因此，需要納入有這些裝置於其中的大型IC(LSI)封裝件以做得更小與更薄。容置與保護LSI的封裝組構也需要它們以做得更小與更薄。
許多習知半導體(或「晶片」)封裝件的類型是以樹脂(例如環氧樹脂模製化合物(epoxy molding compound))將半導體晶粒模製在封裝件中。許多封裝方法係堆疊多個積體電路晶粒或封裝內封裝(package in package；PIP)或其組合。其他方法包含封裝階層堆疊(package level stacking)或層疊封裝(package on package；POP)。結合朝向微型化的趨勢的習知封裝件對於低成本、彈性與可靠的製造造成了挑戰。
因此，對於提供高連接性(connectivity)、低成本製造、與縮減尺寸的積體電路封裝系統的需求仍舊維持。鑑於對節省成本與增進效率的需求持續增加，找到這些問題的答案是愈來愈關鍵。鑑於愈趨增加的商業競爭壓力，連同成長的消費者期待且市場中有意義的產品差異的機會減少，找到這些問題的答案是愈來愈關鍵。此外，減低成本、增進效率與效能、及達到競爭壓力的需求更大大地增加了對於找到這些問題的答案的關鍵必要的迫切性。
已經思考過這些問題的解決方案許久，但是先前的發展並未教示或建議任何解決方案，而因此這些問題的解決方案已經長期困擾本發明所屬技術領域中具有通常知識者。
本發明提供一種積體電路封裝系統的製造方法，係包含：將具有第一貫孔的下積體電路附接在基板上方，且該第一貫孔耦接至該基板；將具有插入物貫孔與積體被動裝置的預成形插入物安裝在該下積體電路上方，且該插入物貫孔耦接至該第一貫孔；將具有第二貫孔的上積體電路附接在該預成形插入物上方；以及，在該上積體電路與該預成形插入物上方形成囊裝。
本發明提供一種積體電路封裝系統，包含：基板；下積體電路，係具有第一貫孔並位在該基板上方，且該第一貫孔耦接至該基板；預成形插入物，係具有插入物貫孔與積體被動裝置並位在該下積體電路上方，且該插入物貫孔耦接至該第一貫孔；上積體電路，係具有第二貫孔並位在該預成形插入物上方；以及，囊裝，係位在該上積體電路與該預成形插入物上方。
本發明的一些實施例具有除上述提及的那些步驟或元件之外或代替上述提及的那些步驟或元件的其他步驟或元件。對於閱讀下列實施方式並參照所附圖式後的本發明所屬技術領域中具有通常知識者而言，該等步驟或元件將變得顯而易見。
為了使本發明所屬技術領域中具有通常知識者能夠製造與使用本發明，下列實施例是以足夠的細節來描述。應了解，基於本揭露內容，其他實施例將是顯而易見的，且在不背離本發明的範疇下，可進行系統、製程、或機構的改變。
在下列描述中，將提供許多具體細節，以徹底了解本發明。然而，應明白，可不需這些具體細節來實施本發明。為了避免模糊本發明，將不詳細揭露一些習知的電路、系統組構、與製程步驟。
顯示系統實施例的圖式是部分圖解而非按照比例，特別是一些尺寸係為了清楚表示而在圖式中誇大顯示。同樣地，雖然圖式中的圖樣為了描述方便而一般顯示為相似的方向，但是圖式中的表示大部分是任意的。一般來說，本發明可操作在任何方向上。
在所有圖式中使用的相同元件符號是描述相同的元件。為了描述方便，實施例已經被標號成第一實施例、第二實施例等等，而並非意欲有任何其他意義或用以限制本發明。
為了說明的目的，在此使用的用語「水平的(horizontal)」是定義成平行於積體電路的平面或表面的平面，而不論其方向。用語「垂直的(vertical)」是關於垂直於剛才定義的該水平的方向。例如「上方(above)」、「下方(below)」、「底部(bottom)」、「頂部(top)」、「側邊(side)」(如在「側壁(sidewall)中」)、「上(higher)」、「下(lower)」、「上面的(upper)」、「在…上方(over)」、與「在…之下(under)」的用語是相對於圖式中所顯示的該水平平面來定義。用語「在…上(on)」意指在元件之間有直接接觸。
在此使用的用語「加工(processing)」包含形成所述結構所需的材料或光阻的沉積、圖案化、曝光、顯影、蝕刻、清潔、及/或該材料或光阻的移除。
在此使用的用語「提供(providing)」包含供給(supply)或配置(furnish)材料。在此使用的用語「附接(attaching)」包含扣住(fasten)、貼住(affix)、與黏住(adhere)。在此使用的用語「形成(forming)」包含建構(construct)、成形(shape)、與模製(mold)。
現在參照第1圖，其顯示在本發明的第一實施例中之積體電路封裝系統100的俯視圖。該俯視圖描述囊裝(encapsulation)102，例如包含環氧樹脂模製化合物的蓋體(cover)。
為了說明之目的，顯示該積體電路封裝系統100具有方形組構，雖然要了解，該積體電路封裝系統100可形成為不同的組構。舉例來說，該積體電路封裝系統100可形成為矩形組構或在側邊的非垂直交叉(intersection)中具有角落。
現在參照第2圖，其顯示沿著第1圖的線2--2的積體電路封裝系統100的剖視圖。該剖視圖描述基板204，例如印刷電路板或壓合基板。該基板204可具有外部互連206，例如焊料球或導電柱。
第一下積體電路208(例如積體電路晶粒或覆晶(flip chip))可附接至該基板204。第二下積體電路210可安裝在該第一下積體電路208上方。第一貫孔(through via)212可貫穿該第一下積體電路208。第二貫孔213可貫穿該第二下積體電路210。
舉例來說，該第一下積體電路208與該第二下積體電路210是顯示為相同類型。應了解的是，該第一下積體電路208與該第二下積體電路210可彼此不同。舉例來說，該第一下積體電路208與該第二下積體電路210可形成為不同技術、不同尺寸、與不同功能。
該第一下積體電路208的下積體電路主動側214(其上具有主動電路系統)可面對該基板204。該第一下積體電路208可包含下積體電路被動側216，該下積體電路被動側216之面對方向可遠離該基板204。該第一下積體電路208可在該下積體電路主動側214與該基板204之間包含第一裝置互連217，例如焊料凸塊、導電凸塊或導電柱。以更具體的例子來說，該第一裝置互連217可在該第一貫孔212與該基板204之間。
該第一裝置互連217可在該第一下積體電路208與該第二下積體電路210之間。以更具體的例子來說，該第一裝置互連217可連接該第一貫孔212與該第二貫孔213。
預成形(pre-formed)插入物218(例如壓合插入物、印刷電路板、矽插入物、半導體插入物、或積體電路晶粒)可在被安裝在該第二下積體電路210上方之前被預成形。該預成形插入物218之內部可預成形有插入物貫孔219、積體被動裝置220(例如電阻器、電容器、或電感器)，可使用該積體被動裝置220以形成濾波電路或可程式化電路路徑。該插入物貫孔219可具有接觸墊221(例如觸點或接合墊)，且較佳係不與插入物水平側222共平面。
為了說明之目的，該積體電路封裝系統100是顯示有該積體被動裝置220，該積體被動裝置220具有與該插入物貫孔219相同或相似的剖視圖，雖然應了解，該積體電路封裝系統100可具有不同的組構。舉例來說，該預成形插入物218可在該積體被動裝置220與該插入物貫孔219之間具有不相似或不相同的不同結構。
為了說明之目的，該積體電路封裝系統100是顯示有不與該插入物水平側222共平面的接觸墊221，雖然應了解，該積體電路封裝系統100可具有不同組構。舉例來說，該接觸墊221可與該插入物水平側222共平面或從該插入物水平側222延伸。
該預成形插入物218可預成形有預附接互連223，例如焊料凸塊或其他預附接導電突部(protrusion)。該預成形插入物218可預成形有第一電性互連224，例如接合線、帶狀接合線(ribbon bond wire)、或導電夾(conductive clip)。
該第一電性互連224可連接在該插入物貫孔219與另一插入物貫孔219之間，以用於該預成形插入物218的再熔接(re-fusing)或再排定路線(re-routing)或再切換(re-switching)功能。該第一電性互連224可連接該積體被動裝置220以形成濾波電路。
已經發現本發明提供具有預成形插入物的積體電路封裝系統，該預成形插入物提供可靠的連接結構。在該預成形插入物中的積體被動裝置的加入(inclusion)係藉由消除個別製造步驟而將被動元件安裝至該預成形插入物以增加該積體電路封裝系統的可靠度。此結構也消除由該囊裝製程引起的可靠度問題，該囊裝製程可從該預成形插入物分離出離散的被動元件。
也已經發現本發明提供具有預成形插入物的積體電路封裝系統，該預成形插入物提供彈性的連接結構，該連接結構可在最終組合前修改而導致效能改進。可使用該第一電性互連以再排定路線、再熔接、或再切換具有該積體被動裝置的預成形插入物以形成濾波電路，例如用於高頻率雜訊或電感器、電阻器、電容器(LRC)電路的雜訊取消濾波器(noise cancellation filter)。此改進該積體電路封裝系統的電性效能。也可使用該第一電性互連以再排定路線、再熔接、或再切換訊號、電力、或經由該預成形插入物以接地路徑至該積體電路封裝系統的剩餘部分。
可將第一上積體電路226附接至該預成形插入物218上方。上積體電路主動側228(其上具有主動電路系統)可面對該預成形插入物218。第三貫孔230可貫穿該第一上積體電路226。
該第一上積體電路226也可包含上積體電路被動側232，該上積體電路被動側232之面對方向係遠離該預成形插入物218。可藉由第二裝置互連234(例如焊料凸塊或導電柱)將該第一上積體電路226附接至該預成形插入物218。
可將第二上積體電路236安裝在該第一上積體電路226上方。該第二裝置互連234也可在該第二上積體電路236與該第一上積體電路226之間。
舉例來說，該第一上積體電路226與該第二上積體電路236是顯示成不同類型。應了解，該第一上積體電路226與該第二上積體電路236可彼此相似或相同。舉例來說，該第一上積體電路226與該第二上積體電路236可形成有相似或相同的技術、尺寸、與功能。
第二電性互連233(例如接合線、帶狀接合線、或導電夾)可連接用以再排定路線、再熔接、或再切換該基板204的該基板204的不同導電部分。該囊裝102可在該基板204上方而覆蓋該第一下積體電路208、該第二下積體電路210、該預成形插入物218、該第一上積體電路226與該第二上積體電路236。
現在參照第3圖，其顯示在本發明的第二實施例中的積體電路封裝系統300的近似於第2圖的剖視圖。該剖視圖描述基板304，例如印刷電路板或壓合基板。該基板304可具有外部互連306，例如焊料球或導電柱。
可將第一下積體電路308(例如積體電路晶粒或覆晶)附接至該基板304。可將第二下積體電路310安裝在該第一下積體電路308上方。第一貫孔312可貫穿該第一下積體電路308。第二貫孔313可貫穿該第二下積體電路310。
舉例來說，該第一下積體電路308與該第二下積體電路310是顯示為相同類型。應了解的是，該第一下積體電路308與該第二下積體電路310可彼此不同。舉例來說，該第一下積體電路308與該第二下積體電路310可形成為不同技術、不同尺寸、與不同功能。
該第一下積體電路308的下積體電路主動側314(其上具有主動電路系統)可面對該基板304。該第一下積體電路308可包含下積體電路被動側316，該下積體電路被動側316之面對方向可遠離該基板304。該第一下積體電路308可在該下積體電路主動側314與該基板304之間包含第一裝置互連317，例如焊料凸塊、導電凸塊或導電柱。以更具體的例子來說，該第一裝置互連317可在該第一貫孔312與該基板304之間。
該第一裝置互連317可在該第一下積體電路308與該第二下積體電路310之間。以更具體的例子來說，該第一裝置互連317可連接來自該第一下積體電路308的第一貫孔312與該第二下積體電路310。
預成形插入物318(例如壓合插入物或印刷電路板)可在被安裝在該第一下積體電路308與第二下積體電路310上方之前被預成形。在該預成形插入物318內可預成形嵌入式積體電路(embedded integrated circuit)338。該預成形插入物318可預成形有插入物貫孔319、積體被動裝置320(例如電阻器、電容器、或電感器)以形成濾波電路或可程式化電路路徑。
為了說明之目的，該積體電路封裝系統300是顯示有該積體被動裝置320，該積體被動裝置320具有與該插入物貫孔319相同或相似的剖視圖，雖然應了解，該積體電路封裝系統300可具有不同的組構。舉例來說，該預成形插入物318可在該積體被動裝置320與該插入物貫孔319之間具有不相似或不相同的不同結構。
該預成形插入物318可預成形有預附接互連323，例如焊料凸塊或其他預附接導電突部。該預成形插入物318可預成形有第一電性互連324，例如接合線、帶狀接合線、或導電夾。
該第一電性互連324可連接在該插入物貫孔319與另一插入物貫孔319之間，以用於該預成形插入物318的再熔接或再排定路線或再切換功能。該第一電性互連324可連接不同類型的該積體被動裝置320(例如電阻器、電容器、或電感器)以形成濾波電路。該第一電性互連324可連接再排定路線或再切換連接至該嵌入式積體電路338。
已經進一步發現本發明提供具有預成形插入物的積體電路封裝系統，該預成形插入物提供可靠的連接結構。在該預成形插入物中的嵌入式積體電路的加入係藉由消除個別製造步驟而將額外的積體電路安裝至該預成形插入物以增加該積體電路封裝系統的可靠度。
又已經進一步發現本發明提供具有該預成形插入物的積體電路封裝系統，該預成形插入物提供來自雙連接性與增加再排定路線、再熔接、或再切換能力的緊密佔板面積(compact footprint)。具有沿著該預附接互連的插入物貫孔的預成形插入物提供來自該積體封裝系統上方與下方的雙連接性。該第一貫孔與該插入物貫孔使該嵌入式積體電路被電性耦接至該預成形插入物上方與下方的該積體電路封裝系統的剩餘部分。該第一電性互連容許前往與來自該嵌入式積體電路與該積體電路封裝系統的剩餘部分的該預成形插入物的再排定路線、再熔接、或再切換。該第一電性互連也提供再定址(re-addressing)能力。
可將第一上積體電路326附接在該預成形插入物318上方。上積體電路主動側328(其上具有主動電路系統)可面對該預成形插入物318。第三貫孔330可貫穿該第一上積體電路326。
該第一上積體電路326也包含上積體電路被動側332，該上積體電路被動側332之面對方向係遠離該預成形插入物318。可藉由第二裝置互連334(例如焊料凸塊或導電柱)將該第一上積體電路326附接至該預成形插入物318。
可將第二上積體電路336安裝在該第一上積體電路326上方。該第二裝置互連334也可在該第二上積體電路336與該上積體電路326之間。
第二電性互連333(例如接合線、帶狀接合線、或導電夾)可連接用以再排定路線、再熔接、或再切換該基板304的該基板304的不同導電部分。囊裝302可在該基板304上方而覆蓋該第二下積體電路310、該預成形插入物318、與該第一上積體電路326。
現在參照第4圖，其顯示在本發明的進一步實施例中的積體電路封裝系統的製造方法400的流程圖。該方法400包含：在方塊402中，將具有第一貫孔的下積體電路附接在基板上方，且該第一貫孔耦接至該基板；在方塊404中，將具有插入物貫孔與積體被動裝置的預成形插入物安裝在該下積體電路上方，且該插入物貫孔耦接至該第一貫孔；在方塊406中，將具有第二貫孔的上積體電路附接在該預成形插入物上方；以及，在方塊408中，在該上積體電路與該預成形插入物上方形成囊裝。
所產生的方法與產品是直接了當的、有成本效益的、不複雜的、高度多元的、且有效的，並可藉由改造已知技術來出人意外地和不明顯地實作，且因此是立即地適合於高效率地與經濟地製造積體電路封裝系統。
本發明的另一重要態樣是它大大地支持並幫助降低成本、簡化系統、及增進效能的歷史趨勢。
本發明的這些與其他重要態樣因此促進該技術的狀態至至少下一階層。
雖然本發明已經連結具體最佳模式來敘述，但是應了解，對於已按照先前的描述的本發明所屬技術領域中具有通常知識者而言，許多替代、修改、與變化型式將是顯而易知的。據此，本發明是要涵蓋落入所附申請專利範圍的範疇內的所有此種替代、修改、與變化型式。在此提出或在所附圖式中顯示的所有內容應解讀成說明及非限制的意思。
2--2．．．線
100、300．．．積體電路封裝系統
102、302．．．囊裝
204、304．．．基板
206、306．．．外部互連
208、308．．．第一下積體電路
210、310．．．第二下積體電路
212、312．．．第一貫孔
213、313．．．第二貫孔
214、314．．．下積體電路主動側
216、316．．．積體電路被動側
217、317．．．第一裝置互連
218、318．．．預成形插入物
219、319．．．插入物貫孔
220、320．．．積體被動裝置
221．．．接觸墊
222．．．插入物水平側
223、323．．．預附接互連
224、324．．．第一電性互連
226、326．．．第一上積體電路
228、328．．．上積體電路主動側
230、330．．．第三貫孔
232、332．．．上積體電路被動側
233、333．．．第二電性互連
234、334．．．第二裝置互連
236、336．．．第二上積體電路
338．．．嵌入式積體電路
400．．．方法
402、404、406、408．．．方塊
第1圖係在本發明的第一實施例中之積體電路封裝系統的俯視圖；
第2圖係沿著第1圖的線2--2的積體電路封裝系統的剖視圖；
第3圖係在本發明的第二實施例中的積體電路封裝系統的近似於第2圖的剖視圖；以及
第4圖係在本發明的進一步實施例中的積體電路封裝系統的製造方法的流程圖。
100．．．積體電路封裝系統
102．．．囊裝
204．．．基板
206．．．外部互連
208．．．第一下積體電路
210．．．第二下積體電路
212．．．第一貫孔
213．．．第二貫孔
214．．．下積體電路主動側
216．．．下積體電路被動側
217．．．第一裝置互連
218．．．預成形插入物
219．．．插入物貫孔
220．．．積體被動裝置
221．．．接觸墊
222．．．插入物水平側
223．．．預附接互連
224．．．第一電性互連
226．．．第一上積體電路
228．．．上積體電路主動側
230．．．第三貫孔
232．．．上積體電路被動側
233．．．第二電性互連
234．．．第二裝置互連
236．．．第二上積體電路

Claims (10)

  1. 一種積體電路封裝系統的製造方法，係包括：將具有第一貫孔的下積體電路附接在基板上方，且該第一貫孔耦接至該基板；將具有插入物貫孔與積體被動裝置的預成形插入物安裝在該下積體電路上方，且該插入物貫孔耦接至該第一貫孔，而該積體被動裝置位於該預成形插入物中；將具有第二貫孔的上積體電路附接在該預成形插入物上方；以及在該上積體電路與該預成形插入物上方形成囊裝。
  2. 如申請專利範圍第1項所述之方法，復包括在該積體被動裝置與該插入物貫孔之間連接第一電性互連。
  3. 如申請專利範圍第1項所述之方法，其中，在該下積體電路上方安裝該預成形插入物包含在該下積體電路上方安裝嵌入式積體電路，且該嵌入式積體電路在該預成形插入物內。
  4. 如申請專利範圍第1項所述之方法，復包括在不同類型的積體被動裝置之間連接第一電性互連，以形成濾波電路。
  5. 如申請專利範圍第1項所述之方法，復包括在該基板的不同部分之間連接第二電性互連。
  6. 一種積體電路封裝系統，係包括：基板；下積體電路，係具有第一貫孔並位在該基板上方， 且該第一貫孔耦接至該基板；預成形插入物，係具有插入物貫孔與積體被動裝置並位在該下積體電路上方，且該插入物貫孔耦接至該第一貫孔，而該積體被動裝置位於該預成形插入物中；上積體電路，係具有第二貫孔並位在該預成形插入物上方；以及囊裝，係位在該上積體電路與該預成形插入物上方。
  7. 如申請專利範圍第6項所述之系統，復包括第一電性互連，係位在該積體被動裝置與該插入物貫孔之間。
  8. 如申請專利範圍第6項所述之系統，其中，該預成形插入物包含位在該下積體電路上方的嵌入式積體電路。
  9. 如申請專利範圍第6項所述之系統，復包括第一電性互連，係位在不同類型的該積體被動裝置之間，以形成濾波電路。
  10. 如申請專利範圍第6項所述之系統，復包括第二電性互連，係位在該基板的不同部分之間。
TW099119412A 2009-06-17 2010-06-15 具有插入物之積體電路封裝系統及其製造方法 TWI508225B (zh)

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