TWI498968B - Semiconductor process - Google Patents

Description

Semiconductor process

The present invention relates to a semiconductor process and structure, and more particularly to a semiconductor process and structure that reduces process cost.

With the development of technology, the application of semiconductor structures is increasingly widespread, and is widely used in various integrated circuits and various electronic products. The Passivation Layer is used as an insulating material in a semiconductor structure for electrical insulation and to protect metal wires in a semiconductor structure, and is one of the indispensable film layers in a semiconductor structure.

In the conventional semiconductor process, a common protective layer material is a photoresist material or an epoxy resin, and the formation method thereof generally includes a deposition and a photolithography etching process, but it is difficult to process the semiconductor process due to the high cost of the photolithography etching process. The cost is reduced to the desired range.

In view of this, it is an object of the present invention to provide a low cost semiconductor process.

It is still another object of the present invention to provide a low cost semiconductor structure.

The present invention provides a semiconductor process that first provides a conductive substrate and then forms at least one insulating pattern on the conductive substrate. Then, a metal pattern is formed on the insulating pattern. Then, a first electroplating process is performed to form a protective layer covering metal pattern on the conductive substrate.

In a preferred embodiment of the present invention, the semiconductor process further includes forming a sacrificial layer on a portion of the metal pattern before forming the protective layer, and after forming the protective layer, removing the sacrificial layer to form an opening to expose a portion Metal pattern. A method in which the sacrificial layer is removed includes plasma etching or wet etching.

In a preferred embodiment of the present invention, the method of forming a metal pattern on the insulating pattern is, for example, first forming a plating seed layer over the conductive substrate to cover the insulating pattern, and then forming a patterned photoresist layer on the plating seed layer to expose A partially plated seed layer on the insulating pattern. Then, a portion of the exposed plating seed layer is subjected to a second plating process to form a metal pattern. In addition, after forming the metal pattern and before forming the protective layer, the method further includes removing the patterned photoresist layer and the plating seed layer remaining on the conductive substrate. For example, a method of removing a plating seed layer remaining on a conductive substrate includes wet etching.

In a preferred embodiment of the invention, the electrically conductive substrate is a crucible substrate.

The invention further provides a semiconductor process comprising: providing a conductive substrate; and performing an electroplating process using the conductive substrate as an electrode to form a protective layer on the conductive substrate. The conductive substrate is a germanium substrate.

The invention further provides a semiconductor structure comprising a conductive substrate, at least one insulating pattern, at least one metal pattern, and a protective layer. The insulating pattern is disposed on the conductive substrate, the metal pattern is disposed on the insulating pattern, and the protective layer is formed on the conductive substrate by electroplating and covering the metal pattern.

In a preferred embodiment of the invention, the protective layer includes an opening that exposes a portion of the metal pattern.

In a preferred embodiment of the invention, the electrically conductive substrate is a crucible substrate.

In a preferred embodiment of the invention, the metal pattern is a metal composite layer such as copper/nickel/gold or aluminum/nickel/gold.

In a preferred embodiment of the invention, the material of the protective layer comprises an electrophoretic coating.

Since the semiconductor process of the present invention forms a protective layer by an electroplating process, and forms an opening in the protective layer by forming a sacrificial layer on the metal pattern and then removing the sacrificial layer after forming the protective layer, it is known The lithography process forms a protective layer. In contrast, the present invention can substantially reduce the cost of the semiconductor process.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Please refer to FIG. 1A to FIG. 1C , which are schematic diagrams showing a semiconductor process according to an embodiment of the present invention.

Referring to FIG. 1A, a conductive substrate 110, such as a germanium substrate, is provided. Then, at least one insulating pattern 120 is formed on the conductive substrate 110. Specifically, in this embodiment, for example, an insulating material (not shown) is entirely coated on the conductive substrate 110, and then the layer insulating material is etched into at least one insulating pattern 120 by a photolithography etching process. In the present embodiment, for example, the insulating material is etched into a plurality of insulating patterns 120.

Referring to FIG. 1B, a metal pattern 130 is formed on the insulating pattern 120. In particular, the metal pattern 130 can be formed using an electroplating process. Specifically, please refer to FIGS. 2A-2D , which are schematic cross-sectional views of the metal pattern 130 of the present embodiment in a process. As shown in FIG. 2A, a plating seed layer 131 is first formed on the conductive substrate 110 to cover the insulating pattern 120. Next, as shown in FIG. 2B, a patterned photoresist layer 132 is formed on the plating seed layer 131 to expose a portion of the plating seed layer 131 on the insulating pattern 120. Further, as shown in FIG. 2C, the plating process is performed using the exposed portion of the plating seed layer 131. Thereafter, the patterned photoresist layer 132 and the plating seed layer 131 remaining on the conductive substrate 110 are removed to form the metal pattern 130 shown in FIG. 1B. Wherein, the plating seed layer 131 remaining on the conductive substrate 110 can be removed by etching, such as wet etching.

In addition, the metal pattern 130 of the embodiment may be a metal composite layer, such as a copper/nickel/gold composite layer or an aluminum/nickel/gold composite layer, which can form a metal pattern 130 of the metal composite layer by replacing the electrolyte.

Of course, those skilled in the art should know that the metal pattern 130 can also be formed by a common sputtering or chemical deposition process with a lithography process, and will not be described herein.

Referring to FIG. 1C , after the metal pattern 130 is formed, an electroplating process is performed by using the conductive substrate 110 as an electrode, thereby forming a protective layer 150 on the conductive substrate 110 to cover the metal pattern 130 , that is, substantially completing the semiconductor structure 100 . Process. In detail, the material of the protective layer 150 is, for example, an electrophoretic paint or other insulating material that can be formed by electroplating. Since this type of material has the characteristics of acid and alkali resistance, corrosion resistance, heat resistance and water resistance, the metal pattern 130 can be effectively protected from external materials from causing damage to the metal pattern 130.

In particular, in the process of a semiconductor device electrically connected to an external circuit by using a through silicon via (TSV) technology, the insulating pattern 120 may be formed in the same process as the insulating layer in the via hole, and the metal The pattern 130 can be formed in the same process as the metal layer in the via hole, which will be described below with reference to the drawings.

Please refer to FIG. 3A to FIG. 3C , which are schematic diagrams showing a semiconductor process according to an embodiment of the present invention. As shown in FIG. 3A, the conductive substrate 310 has a through hole 316 extending through the back surface 312 and the active surface 314, and a bonding pad 302 has been formed on the active surface of the conductive substrate 310, and the through hole 316 is corresponding to Connect the pad 302. First, an insulating pattern 120 and an insulating layer 320 covering the sidewalls of the via 316 are formed on the back surface 312 of the conductive substrate 110. In detail, in this embodiment, for example, a layer of insulating material (not shown) is completely coated on the back surface 312 of the conductive substrate 310, and then the layer insulating material is etched into at least one insulating pattern 120 by using a photolithography etching process. At the same time, a portion of the insulating material located at the bottom of the through hole 316 is removed to form an insulating layer 320 exposing the connection pad 302.

Referring to FIG. 3B, a metal pattern 130 and a metal layer 330 filled in the through hole 316 are formed on the insulating pattern 120. The method for forming the metal pattern 130 and the metal layer 330 is the same as or similar to that of the foregoing embodiment, and may be fabricated by a plating, sputtering or chemical deposition process with a lithography process, and details thereof will not be described herein.

Referring to FIG. 3C , in particular, in order to electrically connect the connection pad 302 to the external circuit through the metal layer 330 , the embodiment is formed on the metal layer 330 after the metal layer 330 and the metal pattern 130 are formed, for example. The sacrificial layer 140 is made of, for example, a polymer material. Then, an electroplating process is performed using the conductive substrate 310 as an electrode, thereby forming a protective layer 150 on the conductive substrate 310 to cover the metal pattern 130 not covered by the sacrificial layer 140.

Referring to FIG. 3D, the sacrificial layer 140 is removed, thereby forming an opening 141 to expose a portion of the metal layer 330, which substantially completes the fabrication of the semiconductor structure 300. Wherein, the sacrificial layer 140 can be removed by plasma etching or wet etching.

As described above, the opening 141 of the semiconductor structure 300 can be used for subsequent processing to fill a conductive structure (not shown) electrically connected to the metal layer 330, such as a via or solder ball, so that the connection pad 302 can be The metal layer 330 and the conductive structure are electrically connected to the external circuit.

It is worth mentioning that, although the foregoing two embodiments firstly form the insulating pattern 120 / the insulating layer 320 and the metal pattern 130 / the metal layer 330 on the conductive substrate 110 / the conductive substrate 310, the conductive substrate 110 / conductive substrate 310 performs an electroplating process for the electrodes to form the protective layer 150, but is only one embodiment of the present invention. The present invention does not limit whether any film layer is formed on the conductive substrate 110 / the conductive substrate 310, as long as the protective layer 150 is formed by an electroplating process using the conductive substrate 110 / the conductive substrate 310 as an electrode, that is, the present invention is desired The scope of protection.

In summary, the semiconductor process of the present invention uses an electroplating process to form a protective layer, and forms an opening in the protective layer by forming a sacrificial layer on the metal pattern and then removing the sacrificial layer after forming the protective layer. . Compared with the conventional method of forming a protective layer by a photolithography process, the present invention can greatly reduce the cost of the semiconductor process.

Moreover, since the present invention is an insulating material which can be plated into a film as a protective layer, and has the characteristics of being resistant to acid, alkali, corrosion, heat and water, it can effectively protect the metal pattern from damage in subsequent processes, and further Improve process yield.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100, 300. . . Semiconductor structure

110, 310. . . Conductive substrate

120. . . Insulation pattern

130. . . Metal pattern

131. . . Electroplated seed layer

132. . . Patterned photoresist layer

140. . . Sacrificial layer

141. . . Opening

150. . . The protective layer

302. . . Connection pad

312. . . back

314. . . Active surface

316. . . Through hole

320. . . Insulation

330. . . Metal layer

1A-1C are schematic diagrams showing the flow of a semiconductor process in an embodiment of the present invention.

2A-2C are schematic flow charts showing the formation of a metal pattern by an electroplating process according to an embodiment of the invention.

3A-3D are schematic flow charts showing a semiconductor process in another embodiment of the present invention.

120. . . Insulation pattern

130. . . Metal pattern

141. . . Opening

150. . . The protective layer

300. . . Semiconductor structure

302. . . Connection pad

310. . . Conductive substrate

312. . . back

314. . . Active surface

320. . . Insulation

330. . . Metal layer

Claims (13)

A method of fabricating a semiconductor, comprising: forming a conductive substrate having at least a uniform hole penetrating a back surface of the conductive substrate and an active surface of the conductive substrate; forming at least one connection pad on the active surface of the conductive substrate Forming an insulating pattern on the conductive substrate, wherein the insulating pattern is formed on sidewalls of the at least one of the common holes; forming a metal pattern on the insulating pattern; and performing a first plating process to form the metal pattern A protective layer, wherein the protective layer comprises an insulating material. The method of claim 1, wherein before forming the protective layer, further comprising forming a sacrificial layer on the metal pattern, and after forming the protective layer, removing the sacrificial layer to form a through-protection One of the layers is open to expose at least a portion of the metal pattern. The method of claim 2, wherein the method of removing the sacrificial layer comprises using a plasma etching process or a wet etching process. The method of claim 1, wherein the method of forming the metal pattern on the insulating pattern comprises: forming a plating seed layer on the conductive substrate to cover the insulating pattern; forming a pattern on the plating seed layer And forming a photoresist layer to expose a portion of the plating seed layer on the insulating pattern; and performing a second plating process on the exposed portion of the plating seed layer to form the metal pattern. The method of claim 4, wherein after forming the metal pattern and before forming the protective layer, further comprising: removing the patterned photoresist layer; and removing the plating remaining on the conductive substrate Seed layer. The method of claim 5, wherein the method of removing the electroplated seed layer remaining on the conductive substrate comprises using a wet etching process. The method of claim 1, wherein the electrically conductive substrate comprises a crucible substrate. A method of fabricating a semiconductor, comprising: providing a conductive substrate having at least a uniform hole penetrating a back surface of the conductive substrate and an active surface of the conductive substrate; and providing at least one connection pad on the active surface of the conductive substrate; Providing an insulating pattern on the conductive substrate; providing a metal pattern on the insulating pattern, wherein the insulating pattern is on the conductive substrate and sidewalls of the at least one of the consistent holes; and performing an electroplating process using the conductive substrate as an electrode A protective layer is formed on the conductive substrate, wherein the protective layer covers the metal pattern, and wherein the protective layer comprises an insulating material. The method of claim 8, wherein the electrically conductive substrate comprises a crucible substrate. The method of claim 1, wherein the protective layer comprises an electrophoretic coating. The method of claim 8, wherein the protective layer comprises electricity Swimming paint. The method of claim 1, wherein performing the first electroplating process comprises directly forming the protective layer on the conductive substrate. The method of claim 8, wherein the electroplating process using the conductive substrate as an electrode comprises forming the protective layer to directly contact the conductive substrate.