CN111446178A - Processing method of polyimide combined copper column element - Google Patents
Processing method of polyimide combined copper column element Download PDFInfo
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- CN111446178A CN111446178A CN202010300158.6A CN202010300158A CN111446178A CN 111446178 A CN111446178 A CN 111446178A CN 202010300158 A CN202010300158 A CN 202010300158A CN 111446178 A CN111446178 A CN 111446178A
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1182—Applying permanent coating, e.g. in-situ coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/165—Material
- H01L2224/16501—Material at the bonding interface
- H01L2224/16502—Material at the bonding interface comprising an eutectic alloy
Abstract
The invention discloses a processing method of a polyimide combined copper column element, belonging to the technical field of wafer production and comprising the following steps: s0 depositing a silicon nitride layer on the wafer substrate and completing etching to complete the tungsten plug through hole process and tungsten chemical vapor deposition to form a tungsten column; s1 depositing a copper seed layer on the silicon nitride layer and the tungsten column; s2, generating a mask pattern on the copper seed layer, wherein the mask pattern is a photoresist layer; s3, generating a copper pillar above the tungsten pillar by a single-chip electroplating process; s4 removing the photoresist layer on the copper seed layer with organic solvent; s5, etching the copper seed layer on the silicon nitride layer by wet etching to remove the copper seed layer under the pattern; s6 coating polyimide on the silicon nitride layer; s7, dry etching the polyimide layer on the silicon nitride layer to expose the upper structure of the copper pillar; s8 forming a noble metal coating layer of the copper pillar in a selective chemical plating mode; the problem of among the prior art wire welding copper pad face the technology thermal diffusivity relatively poor and contact point reliability poor in adverse circumstances occasion use is solved.
Description
Technical Field
The invention relates to the technical field of wafer production, in particular to a processing method of a polyimide combined copper column element.
Background
The chip grain production process generates copper/aluminum pad surfaces, after the grain is cut, lead frames (L eadFrame) are welded by gold, aluminum or copper wires for packaging operation, silicon nitride is used as a passivation layer on the conductive pad surface of the grain, and the lead frames are welded by wires, but the process of welding the copper pad surfaces by the wires is poor in heat dissipation, and the problem of contact reliability is easily caused when the chip grain is used in severe environment for a long time.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a processing method of a polyimide combined copper column element, which solves the problems of poor process heat dissipation of a lead welding copper pad surface and poor contact point reliability in severe environment occasions in the prior art.
The purpose of the invention can be realized by the following technical scheme:
1. a processing method of a polyimide combined copper pillar element comprises the following steps:
s0 depositing to form a silicon nitride layer on the wafer substrate by plasma enhanced chemical vapor deposition process and completing etching, and completing tungsten plug through hole process and tungsten chemical vapor deposition to form a tungsten column on the silicon nitride layer;
s1 depositing a copper seed layer on the silicon nitride layer and the tungsten column by physical vapor deposition;
s2, generating a mask pattern on the copper seed layer by using a photoresist coating technology, wherein the mask pattern is a photoresist layer, and performing a yellow light process on the photoresist layer;
s3, generating a copper pillar above the tungsten pillar by a single-chip electroplating process, wherein the height of the copper pillar is 5-10 um;
s4 removing the photoresist layer on the copper seed layer with organic solvent;
s5, etching the copper seed layer on the silicon nitride layer by wet etching to remove the copper seed layer under the pattern;
s6, coating polyimide on the silicon nitride layer, wherein the thickness of the polyimide layer is higher than that of the copper pillar, and performing a yellow light process to enable the polyimide layer to cover the edge of the copper pillar and wrap the top of the copper pillar;
s7, etching the polyimide layer on the silicon nitride layer by a dry method to expose the upper structure of the copper pillar, etching until the exposed depth of the upper part of the copper pillar is 0.5-2 um, curing the remained polyimide layer at 350-450 ℃, and curing the polyimide layer to form a passivation protective layer;
s8 forming a noble metal coating layer of the copper pillar in a selective chemical plating mode;
s9, welding a lead frame on the noble metal coating layer, wherein the welding contact surfaces of the lead frame and the noble metal coating layer form a eutectic alloy contact layer.
As a preferable aspect of the present invention, in step S1, the thickness of the copper seed layer is greater than that of the copper seed layer
。
As a preferred embodiment of the present invention, in step S3, the method further includes forming a copper pillar on the tungsten pillar by a trench plating process.
As a preferable scheme of the present invention, in step S6, the polyimide layer wraps the top of the copper pillar by a distance greater than 0.1 um;
in a preferred embodiment of the present invention, in step S7, the dry etching is to etch the polyimide layer by using oxygen plasma.
In a preferred embodiment of the present invention, in step S8, the noble metal coating layer is coated with a combination of nickel, palladium and gold.
In a preferred embodiment of the present invention, the thickness of nickel in the noble metal coating layer is 1.5 to 3.5 micrometers, the thickness of palladium is 0.15 to 0.35 micrometers, and the thickness of gold is 0.02 to 0.05 micrometers.
The invention has the beneficial effects that:
the embedded pad surface is replaced by a copper column structure, and the production process of the power element with large current, high voltage and high frequency is beneficial to the conductivity, heat dissipation and contact reliability. The passivation layer process using polyimide is more suitable for the environment with high temperature, high humidity and more vibration. The copper pillar is used to replace the copper pad surface to obtain the power device with better electric conduction and heat dissipation. The passivation process using polyimide is applied to power components, and the polyimide forms a buffer hard protection layer of the original packaging material. The copper pillar structure is used to replace the embedded copper/aluminum pad surface to obtain a better power device with electrical and thermal conductivity. The copper pillar structure is used for replacing the embedded pad surface to improve the reliability of long-term conduction of the contact. The passivation technology of the copper column and the polyimide is suitable for the environment with high temperature, high humidity and more vibration.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of step S1 after completion;
FIG. 2 is a schematic diagram of step S2 after completion;
FIG. 3 is a schematic diagram of step S3 after completion;
FIG. 4 is a schematic diagram of step S5 after completion;
FIG. 5 is a schematic diagram of step S6 after completion;
FIG. 6 is a schematic diagram of step S7 after completion;
FIG. 7 is a schematic diagram of step S8 after completion;
fig. 8 is a schematic diagram of step S9 after completion.
The reference numbers in the figures illustrate:
1 copper column, 2 noble metal coating, 3 silicon nitride layer, 4 polyimide layer, 5 lead frame, 6 tungsten column, 7 wafer substrate, 8 copper seed layer, 9 photoresist layer
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A processing method of a polyimide combined copper column element is characterized by comprising the following steps:
s0 depositing to form a silicon nitride layer 3 on the wafer substrate by plasma enhanced chemical vapor deposition process and completing etching, and completing tungsten plug through hole process and tungsten chemical vapor deposition to form a tungsten column 6 on the silicon nitride layer 3;
s1 depositing a copper seed layer 8 on the silicon nitride layer 3 and the tungsten pillar 6 by physical vapor deposition (pvdphysicai vapordeposotion), as shown in fig. 1;
s2 forming a mask pattern (exposing the space position of the copper pillar above the W-Plug tungsten pillar) on the copper seed layer 8 by using a photoresist coating technique, the mask pattern being a photoresist layer 9, and performing a yellow light process (exposing and developing the photoresist layer) on the photoresist layer 9, as shown in fig. 2;
s3 forming copper pillars 1(ECPCuPillar) on the tungsten pillars 6 by a single wafer electroplating process, wherein the height of the copper pillars 1 is 5 to 10um, as shown in fig. 3;
s4 removing the photoresist layer 9 on the copper seed layer 8 with organic solvent;
s5 wet etching the copper seed layer 8 (exposing the silicon nitride layer) on the silicon nitride layer 3 (under the photoresist outside the copper pillar) to remove the copper seed layer 8 under the pattern, as shown in fig. 4;
s6 coating Polyimide (Polyimide has photosensitivity) on the silicon nitride layer 3, making the thickness of the Polyimide layer 4 higher than the height of the copper pillar, and performing a yellow light process to make the Polyimide layer 4 cover the edge of the copper pillar 1 and wrap the top of the copper pillar 1, as shown in fig. 5;
s7, etching the polyimide layer 4 on the silicon nitride layer 3 by a dry method to expose the upper structure of the copper pillar 1, etching until the upper part of the copper pillar 1 is exposed to a depth of 0.5-2 um, curing the remained polyimide layer 4 at a temperature of 350-450 ℃, and curing the polyimide layer 4 to form a passivation protective layer, as shown in FIG. 6;
s8 forming the noble metal clad layer 2 of the copper pillar 1 by selective electroless plating, as shown in fig. 7; (the largest area of the upper layer and the periphery is plated with copper to achieve low resistance and good heat dissipation for connecting with a contact body of external conduction.)
S9 is to solder the lead frame 5 to the noble metal clad layer 2, and to form a eutectic alloy contact layer at the solder interface between the lead frame 5 and the noble metal clad layer 2, as shown in fig. 8. And finishing the passivation protective layer combining the copper column and the polyimide, and performing subsequent process and advanced packaging operation.
In step S1, the thickness of copper seed layer 8 is greater than
。
In step S3, a copper pillar 1 is formed on the tungsten pillar by a trench plating process.
In step S6, the distance between the polyimide layer 4 and the top of the copper pillar is greater than 0.1 um;
in step S7, the dry etching is to etch the polyimide layer 4 by using oxygen plasma.
In step S8, the noble metal clad layer 2 is clad with a combination of nickel, palladium, and gold. The thickness of nickel in the noble metal coating layer 2 is 1.5 to 3.5 microns, the thickness of palladium is 0.15 to 0.35 micron, and the thickness of gold is 0.02 to 0.05 micron.
The embedded pad surface is replaced by a copper column structure, and the production process of the power element with large current, high voltage and high frequency is beneficial to the conductivity, heat dissipation and contact reliability. The passivation layer process using polyimide is more suitable for the environment with high temperature, high humidity and more vibration. The passivation process using polyimide is applied to power components, and the polyimide forms a buffer hard protection layer of the original packaging material. The copper pillar structure is used to replace the embedded copper/aluminum pad surface to obtain a better power device with electrical and thermal conductivity. The copper pillar structure is used for replacing the embedded pad surface to improve the reliability of long-term conduction of the contact. The passivation technology of the copper column and the polyimide is suitable for the environment with high temperature, high humidity and more vibration.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (7)
1. A processing method of a polyimide combined copper column element is characterized by comprising the following steps:
s0, depositing and forming a silicon nitride layer (3) on the wafer substrate by a plasma enhanced chemical vapor deposition process and completing etching, and completing a tungsten plug through hole process and tungsten chemical vapor deposition on the silicon nitride layer (3) to form a tungsten column (6);
s1, depositing a copper seed layer (8) on the silicon nitride layer (3) and the tungsten column (6) by a physical vapor deposition process;
s2, generating a mask pattern on the copper seed layer (8) by using a photoresist coating technology, wherein the mask pattern is a photoresist layer (9), and performing a yellow light process on the photoresist layer (9);
s3, generating a copper pillar (1) above the tungsten pillar (6) by a single-chip electroplating process, wherein the height of the copper pillar (1) is 5-10 um;
s4 removing the photoresist layer (9) on the copper seed layer (8) by using an organic solvent;
s5, etching the copper seed layer (8) on the silicon nitride layer (3) by a wet etching method to remove the copper seed layer (8) under the pattern;
s6, coating polyimide on the silicon nitride layer (3), wherein the thickness of the polyimide layer (4) is higher than the height of the copper column, and performing a yellow light process to enable the polyimide layer (4) to cover the edge of the copper column (1) and wrap the top of the copper column (1);
s7, etching the polyimide layer (4) on the silicon nitride layer (3) by a dry method to expose the upper structure of the copper pillar (1), etching until the upper part of the copper pillar (1) is exposed to a depth of 0.5-2 um, curing the remained polyimide layer (4) at a temperature of 350-450 ℃, and curing the polyimide layer (4) to form a passivation protective layer;
s8 forming a noble metal coating layer (2) of the copper pillar (1) in a selective chemical plating mode;
s9, welding a lead frame (5) on the noble metal coating layer (2), and forming a eutectic alloy contact layer at the welding contact surface of the lead frame (5) and the noble metal coating layer (2).
2. The method of claim 1, wherein the polyimide bonded copper pillar comprises: in step S1, the thickness of the copper seed layer (8) is greater than
3. The method of claim 1, wherein the polyimide bonded copper pillar comprises: in step S3, a copper pillar (1) is formed on the tungsten pillar by a trench plating process.
4. The method of claim 1, wherein the polyimide bonded copper pillar comprises: in step S6, the polyimide layer (4) wraps the copper pillar top by a distance greater than 0.1 um.
5. The method of claim 1, wherein the polyimide bonded copper pillar comprises: in step S7, the dry etching is to etch the polyimide layer (4) by using oxygen plasma.
6. The method of claim 1, wherein the polyimide bonded copper pillar comprises: in step S8, the noble metal coating layer (2) is coated with a combination of nickel, palladium, and gold.
7. The method as claimed in claim 6, wherein the polyimide combined copper pillar comprises: the thickness of nickel in the noble metal coating layer (2) is 1.5-3.5 microns, the thickness of palladium is 0.15-0.35 microns, and the thickness of gold is 0.02-0.05 microns.
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| US20100148361A1 (en) * | 2008-12-17 | 2010-06-17 | United Test Center Inc. | Semiconductor device and method for fabricating the same |
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| CN102270610A (en) * | 2010-06-02 | 2011-12-07 | 台湾积体电路制造股份有限公司 | Integrated circuit device and packaging assembly |
| CN105448755A (en) * | 2016-01-15 | 2016-03-30 | 中芯长电半导体（江阴）有限公司 | A packaging method for copper column salient points and a packaging structure |
| CN107799491A (en) * | 2016-09-01 | 2018-03-13 | 半导体元件工业有限责任公司 | Semiconductor copper metallization structure |
| CN108122854A (en) * | 2016-11-28 | 2018-06-05 | 矽品精密工业股份有限公司 | Substrate structure and method for fabricating the same |
| CN109390306A (en) * | 2017-08-02 | 2019-02-26 | 矽品精密工业股份有限公司 | Electronic package |
-
2020
- 2020-04-16 CN CN202010300158.6A patent/CN111446178A/en active Pending
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|---|---|---|---|---|
| US20100148361A1 (en) * | 2008-12-17 | 2010-06-17 | United Test Center Inc. | Semiconductor device and method for fabricating the same |
| CN102013421A (en) * | 2009-09-03 | 2011-04-13 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
| CN102270610A (en) * | 2010-06-02 | 2011-12-07 | 台湾积体电路制造股份有限公司 | Integrated circuit device and packaging assembly |
| CN105448755A (en) * | 2016-01-15 | 2016-03-30 | 中芯长电半导体（江阴）有限公司 | A packaging method for copper column salient points and a packaging structure |
| CN107799491A (en) * | 2016-09-01 | 2018-03-13 | 半导体元件工业有限责任公司 | Semiconductor copper metallization structure |
| CN108122854A (en) * | 2016-11-28 | 2018-06-05 | 矽品精密工业股份有限公司 | Substrate structure and method for fabricating the same |
| CN109390306A (en) * | 2017-08-02 | 2019-02-26 | 矽品精密工业股份有限公司 | Electronic package |
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