TWI491005B - 具有金紅石結晶相二氧化鈦介電膜之半導體元件的製作方法 - Google Patents

具有金紅石結晶相二氧化鈦介電膜之半導體元件的製作方法 Download PDF

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TWI491005B
TWI491005B TW102106095A TW102106095A TWI491005B TW I491005 B TWI491005 B TW I491005B TW 102106095 A TW102106095 A TW 102106095A TW 102106095 A TW102106095 A TW 102106095A TW I491005 B TWI491005 B TW I491005B
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titanium dioxide
crystalline phase
electrode
dielectric film
rutile crystalline
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TW201428922A (zh
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Chun I Hsieh
Daniel Damjanovic
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Nanya Technology Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
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    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma

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Description

具有金紅石結晶相二氧化鈦介電膜之半導體元件的製作方法
本發明係關於一種半導體元件,特別是有關於一種改良的高介電常數(high-k)介電層,使用這種介電層的電容結構,並例示其製造方法。
隨著動態隨機存取記憶體的金屬-絕緣-金屬電容的微縮,記憶體製程中因此有必要導入高介電常數介電材,例如,二氧化鈦。已知二氧化鈦具有不同的結晶相,其介電常數也不同,其中兩種已知的二氧化鈦結晶相是銳鈦礦(anatase)及金紅石(rutile)。由於金紅石二氧化鈦具有較高的介電常數(k>90),因此在電容介電薄膜製程中是較希望被增加的成分。
二氧化鈦介電層通常利用原子層沈積(atomic layer deposition,ALD)法形成。然而,在原子層沈積過程中,二氧化鈦往往是以銳鈦礦結晶相為主。為了要形成具有金紅石結晶相及低漏電的二氧化鈦介電層,仍需要再以摻質摻雜、後退火(600℃或更高溫)處理以及/或結合模版層進行的臭氧原子層沈積才能達到。前述摻質摻雜方法的問題是高成本、低產出率,且不容易控制其分佈。前述後退火方法的缺點是額外的熱預算及機械應力可能影響電晶體元件。前述的結合模版層進行的臭氧原子層沈積法,其問題在於沈積速率過慢(單一ALD循環約0.4Å),且可能有蝕刻或氧化下層之風險。
另外一種沈積二氧化鈦介電層的作法是利用水基(water-based)原子層沈積法,其在ALD循環中以水蒸氣作為氧化劑。這種水基原子層沈積法的沈積速率較前述臭氧原子層沈積法快,因此具有高產出率,然而,以水基原子層沈積法形成的二氧化鈦其結晶相是以銳鈦礦為主。為了在水基原子層沈積過程中形成金紅石結晶相的二氧化鈦,必須沈積至少厚達10nm的二氧化鈦,或者以相對較高的製程溫度進行。
由上可知,業界目前仍需要改良的方法來沈積高介電常數材料,例如,金紅石結晶相的二氧化鈦,且該方法具有高沈積/成長速率,同時能保持低漏電特性,並且避免上述先前技藝的諸多缺點。
根據本發明實施例,本發明提供一種電容結構,包含有一第一電極,設於一基材上;一二氧化鈦介電層,直接形成在該第一電極上,其中該二氧化鈦介電層僅單純具有金紅石結晶相;以及一第二電極,位於該二氧化鈦介電層上。根據本發明實施例,在該第一電極與該二氧化鈦介電層之間不需要模版層、晶種層或預處理層。此外,也不需要對該二氧化鈦介電層進行任何的摻質摻雜處理。
為讓本發明之上述目的、特徵及優點能更明顯易懂,下文特舉較佳實施方式,並配合所附圖式,作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用,並非用來對本發明加以限制者。
在下文中,將參照附圖說明細節,該些附圖中之內容亦構成說明書細節描述的一部份,並且以可實行該實施例之特例描述方式來繪示。下文實施例已描述足夠的細節俾使該領域之一般技藝人士得以具以實施。當然,亦可採行其他的實施例,或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此,下文之細節描述不應被視為是限制,反之,其中所包含的實施例將由隨附的申請專利範圍來加以界定。
第1圖為依據本發明實施例所繪示的部分電容結構的剖面示意圖。如第1圖所示,電容結構20設於一基材10上,例如矽基材。當然,基材10也可能是其他的半導體基材,在此不設限。電容結構20包含有一第一電極22、一第二電極26,以及一高介電常數介電層24,其介於第一電極22與第二電極26之間。根據本發明實施例,前述高介電常數介電層24係直接接觸到第一電極22,故並無任何模版層(template layer)、晶種層(seed layer)或預處理層(pre-treated layer)介於其間。在其他實施例中,形成高介電常數介電層24之前,可選擇在第一電極22上形成如氧化鋁(Al2O3)等介電層。
前述第一電極22可以是貴金屬材料,例如,釕(Ru),其具有六方最密堆積(hexagonal close-packed,HCP)晶體結構。在另一實施例中,第一電極22可以是由氮化鈦所構成者。前述第一電極22可以利用任何適合的方法形成,例如,化學氣相沈積(chemical vapor deposition,CVD)法、原子層沈積(atomic layer deposition,ALD)法、物理氣相沈積(physical vapor deposition,PVD)法或濺鍍(sputtering)法。根據本發明實施例,前述直接沈積在第一電極22上的高介電常 數介電層24為金紅石結晶相的二氧化鈦。根據本發明實施例,高介電常數介電層24的厚度約為7nm或更薄。根據本發明實施例,高介電常數介電層24中不用摻雜如鋁等摻質。前述第二電極26可以是貴金屬材料或其他合適的導電材料,例如金屬氧化物或金屬氮化物。舉例來說,第二電極26可以是釕(Ru)、鉑(Pt)、銥(Ir)、氧化釕(RuO2)、氧化銥(IrO2)、氮化鈦(TiN)、氮化鉭(TaN)、氮化鎢(WN)等等。
請同時參閱第2圖及第1圖,第2圖例示形成電容結構20的流程圖。如第2圖所示,製程流程100包括四個連續的主要步驟102~108。在步驟102中,第一電極22。例如釕或氮化鈦,被沈積到基材10上。接著進行步驟104,進行一水基原子層沈積(water-based ALD)法,於第一電極22上沈積一過渡非晶相二氧化鈦層(未顯示於第1圖)。根據本發明實施例,前述過渡非晶相二氧化鈦層的厚度約為7nm或更薄。前述水基原子層沈積法可包含有複數個ALD循環,而各ALD循環包含有:(1)於一反應腔供應一鈦前趨物(鈦脈衝);(2)以鈍氣吹除該反應腔;(3)於該反應腔供應供應水蒸氣(水脈衝);以及(4)再次以鈍氣吹除該反應腔。根據本發明實施例,反應溫度可以介於150℃至450℃之間,例如,285℃。當鈦前趨物,例如四氯化鈦(TiCl4)供應到反應腔時,部分鈦前趨物被吸附到基材10的顯露表面。吹除氣體,例如氬氣接著將未被吸附的鈦前趨物移除,然後使水蒸氣(作為氧化劑)與吸附到基材10表面的鈦前趨物反應,如此形成單一原子層的二氧化鈦。根據本發明實施例,在前述水基原子層沈積過程中,僅有水蒸氣提供作為氧化劑,以增加沈積或成長速 率。
接著,步驟106,在完成前述水基原子層沈積之後,非晶相的二氧化鈦層接著以氧氣電漿處理,藉以將非晶相的二氧化鈦層全部轉換成金紅石結晶相二氧化鈦。根據本發明實施例,前述的氧氣電漿處理可以是非現場(ex-situ)處理。例如,前述的氧氣電漿處理可以是遠端電漿技術,例如感應耦合電漿(inductively coupled plasma,ICP)或去耦合電漿(de-coupled plasma,DCP)。以氧氣電漿處理採用感應耦合電漿為例,電漿產生器可以使用500瓦(W)至2500瓦的交流功率(AC power)。以氧氣電漿處理採用去耦合電漿為例,電漿產生器可以使用大於500瓦的交流功率。前述遠端氧氣電漿可以含有離子態的氧,以及載氣,如氬氣或氮氣。根據本發明實施例,經過前述的氧氣電漿處理後,可以使二氧化鈦層中的氧含量增加。在某些實施例中,前述的氧氣電漿處理可以是現場(in-situ)處理,例如,採用電漿加強ALD機台。最後,進行步驟108,於金紅石結晶相二氧化鈦上形成第二電極或上電極。
本發明的優點至少包括:不需要於第一電極或下電極表面形成模版層或預處理層。此外,可以省略先前技藝中的摻質摻雜或後退火處理。由於水基原子層沈積法具有較高的沈積或成長速率,可以得到較高的產出率。
第3A圖及第3B圖顯示水基原子層沈積法沈積的二氧化鈦的x射線繞射光譜(相對強度對2 theta作圖而光譜區間為2 theta=20至2 theta=35之間)。從第3A圖可看出,在進行電漿處理之前,7nm厚的二氧化鈦層為非晶相。而進行電漿處理之後,如第3B圖所示, 7nm厚的二氧化鈦層被全部轉換成金紅石結晶相二氧化鈦。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
10‧‧‧基材
20‧‧‧電容結構
22‧‧‧第一電極
24‧‧‧高介電常數介電層
26‧‧‧第二電極
100‧‧‧製程流程
102‧‧‧步驟
104‧‧‧步驟
106‧‧‧步驟
108‧‧‧步驟
第1圖為依據本發明實施例所繪示的部分電容結構的剖面示意圖。
第2圖例示形成第1圖中電容結構的流程圖。
第3A圖及第3B圖顯示水基原子層沈積法沈積的二氧化鈦的x射線繞射光譜。
10‧‧‧基材
20‧‧‧電容結構
22‧‧‧第一電極
24‧‧‧高介電常數介電層
26‧‧‧第二電極

Claims (6)

  1. 一種具有金紅石結晶相二氧化鈦介電膜之半導體元件的製作方法,包含有:提供一基材;於該基材上沉積一第一電極;進行一水基原子層沈積(water-based ALD)法,於該第一電極上沈積一過渡非晶相二氧化鈦層;以氧氣電漿處理該過渡非晶相二氧化鈦層,將該過渡非晶相二氧化鈦層全部轉換成一金紅石結晶相二氧化鈦層;以及於該金紅石結晶相二氧化鈦層上沉積一第二電極。
  2. 如申請專利範圍第1項所述的具有金紅石結晶相二氧化鈦介電膜之半導體元件的製作方法,其中前述水基原子層沈積法包含有複數個原子層沈積(ALD)循環,而各ALD循環包含有以下四個連續步驟:(1)於一反應腔供應一鈦前趨物;(2)以鈍氣吹除該反應腔;(3)於該反應腔供應水蒸氣;以及(4)再次以鈍氣吹除該反應腔。
  3. 如申請專利範圍第2項所述的具有金紅石結晶相二氧化鈦介電膜之半導體元件的製作方法,其中所述水蒸氣作為氧化劑,並與該鈦前趨物反應,形成單一原子層的二氧化鈦。
  4. 如申請專利範圍第2項所述的具有金紅石結晶相二氧化鈦介電膜之半導體元件的製作方法,其中該鈦前趨物為四氯化鈦(TiCl4)。
  5. 如申請專利範圍第1項所述的具有金紅石結晶相二氧化鈦介電膜之半導體元件的製作方法,其中水基原子層沈積法的反應溫度介於150℃至450℃之間。
  6. 如申請專利範圍第1項所述的具有金紅石結晶相二氧化鈦介電膜之半導體元件的製作方法,其中該第一電極係直接接觸該金紅石結晶相二氧化鈦層。
TW102106095A 2013-01-02 2013-02-21 具有金紅石結晶相二氧化鈦介電膜之半導體元件的製作方法 TWI491005B (zh)

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US13/732,442 US20140185182A1 (en) 2013-01-02 2013-01-02 Semiconductor device with rutile titanium oxide dielectric film

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