TWI487097B - Solid state camera device - Google Patents

Solid state camera device Download PDF

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TWI487097B
TWI487097B TW101141320A TW101141320A TWI487097B TW I487097 B TWI487097 B TW I487097B TW 101141320 A TW101141320 A TW 101141320A TW 101141320 A TW101141320 A TW 101141320A TW I487097 B TWI487097 B TW I487097B
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photodiode
mos capacitor
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Tomoyasu Furukawa
Tomohiro Saito
Yusuke Nonaka
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Hitachi Ltd
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    • H01—ELECTRIC ELEMENTS
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
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    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
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Description

固態攝像裝置
本發明係關於使用光電轉換效應而獲得畫像、位置資訊的CMOS感測器，CCD感測器等之固態攝像裝置，特別是關於於單位畫素內具備MOS容量，進行電荷-電壓轉換的固態攝像裝置之SN比提升與動態範圍之擴大技術。
以CMOS感測器，CCD感測器為代表的固態攝像裝置係廣泛利用於攝錄影機或數位潛像相機等。
於使用CMOS感測器的固態攝像裝置，光電轉換元件PD及進行其之選擇的開關元件，或信號電荷讀出用的開關元件係使用CMOS電晶體。又，控制電路，信號處理電路等之周邊電路，係使用MOS電晶體或CMOS電晶體，具有光電轉換元件PD與上述開關元件、周邊電路可藉由一連串之構成製造於同一晶片上之優點。
該固態攝像裝置，係將設有光電轉換元件(光二極體：PD)的複數個畫素配置於半導體基板上者，使射入各畫素的光藉由光二極體進行光電變換而產生電荷並收集，將該電荷傳送至浮置擴散(FD)部，使該FD部之電位變動藉由MOS電晶體予以檢測出，將其轉換為電氣信號，藉由放大而輸出影像信號者(例如專利文獻1)。
[先行技術文獻]
[專利文獻]
[專利文獻1]特開2006-148284號公報
為了影像信號之光感度提升，將FD部之容量抑制於較小，而提高信號電荷轉換為信號電壓時之電荷電壓轉換效率乃較好者。經由光電轉換獲得的電荷Q，在電荷儲存用的FD部之容量設為C及FD部之信號電壓為V時，係成立△V=△Q/C之關係，因此電荷Q之變化伴隨的信號電壓V之變化，係隨著容量C越小而變為越大。但是，如此而提高該電荷電壓轉換效率時，對應於此會提高攝像之感度，因此暗電荷引起的雜訊成分有導致SN比降低之傾向。於此，暗電荷係指光之射入以外之原因產生的電荷，熱雜訊為主要原因。另外，FD部之容量抑制於較小的問題為，強光射入時儲存於PD的信號電荷無法完全傳送至FD部。又，作為該對策，而將PD之飽和信號量減少時，無法確保亮度高的部分之對比，動態範圍被縮小。增大FD部之容量，擴大PD之面積，而取得大的動態範圍，則暗電流PD和面積呈比例變大。因此，SN比之提升與動態範圍之擴大欲同時實現時，需要抑制暗電荷之產生。
藉由對動作中之固態攝像元件內之PN接合施加逆偏壓，使存在於擴散層的多數載子跨越阱之電位障壁，流入 PD，而防止暗電荷之增加。
又，電荷電壓轉換部之元件由包含MOS電容量的元件構成時，藉由設為和阱同一導電型的增強型MOS電容量，使流入PD，可防止暗電荷之增加之同時，無須配置用於連接MOS電容量之擴散層的配線，佈局面積可以縮小。
可以同時實現固態攝像元件之SN比之提升與動態範圍之擴大。
 [實施例1]
以下，參照圖面詳細說明本發明之實施形態。
圖1係表示電荷電壓轉換部之元件為由含有MOS電容量的元件構成時之CMOS影像感測器(畫素部)之電路圖。含有該MOS電容量的畫素部之電路構成，例如係記載於專利文獻1。又，本電路僅為一例，但不限定於該電路構成。使用圖2之時序圖說明本電路之動作。
於重置期間，重置線9及讀出線8成為High(高電位)，重置MOS2及傳送MOS1成為導通而使光二極體PD6及浮置擴散FD7之電荷被放出。之後，重置線9及讀出線8成為Low，重置MOS2及傳送MOS1成為非導通。於曝光期間，光之照射產生的光電荷使電荷被儲存於光二極體 PD6。接著，讀出線8成為High而使傳送MOS1導通，如此則，儲存於光二極體PD6的電荷將被傳送至浮置擴散FD7及MOS電容量4。浮置擴散FD7係發揮電容器之機能，浮置擴散FD7及MOS電容量4係將和光二極體PD6之光照射量對應的電荷予以儲存。於讀出期間，選擇線10成為High，使選擇MOS5成為導通。於放大MOS3係連接著定電流源，於源極．汲極間流入定電流。又，放大MOS3之閘極電極係連接於浮置擴散FD7及MOS電容量4，因此和儲存電荷量對應的閘極電壓會被施加於放大MOS3，和儲存電荷量對應的電位會出現於放大MOS3之源極。以該輸出作為畫素資訊，經由選擇MOS5被讀出至信號線11。讀出後，再度使重置MOS2及傳送MOS1導通，進行光二極體PD6及浮置擴散FD7儲存的電荷之重置，準備次一曝光。
於此，並聯連接於放大MOS3的MOS電容量4，係在強光射入時，為了將儲存於光二極體PD6的信號電荷全部傳送的附加容量。設定光二極體PD之光電轉換產生之電荷△Q，放大MOS3之閘極容量C1，浮置擴散7之容量C2，MOS電容量4之容量C3時，△Q引起之電壓變化△V，可以△V=△Q/(C1+C2+C3)之關係表示。
圖3係表示MOS電容量之容量-電壓依存性。橫軸為施加於電容量的電壓，縱軸為容量。成為附加容量的MOS電容量4，在轉用通常之MOS電晶體構造時，係如波形51所示，容量-電壓依存性係顯現於畫素之動作電壓(例如 3.3V)之範圍。因此，如圖4所示，CMOS感測器之輸出特性之直線性劣化。電壓依存性不存在時，係如波形60所示，感測器輸出電壓係和射入光量呈比例，相對於此，如電壓依存性之波形61所示，感測器輸出電壓對於射入光量呈非線形性。因此，欲縮小容量-電壓依存性時，就MOS電容量4而言，若為空乏型(depletion type,D型)則使用具有比動作電壓之範圍更低臨限值電壓(例如-50V)之空乏型(D型)MOS電容量，又、若為增強型(enhancement type，E型)則使用具有比起動作電壓之範圍更高臨限值電壓(例如50V)之增強型(E型)MOS電容量。亦即，若為空乏型，則設為MOS電容量在MOS電晶體之儲存區域，若為增強型(E型)，則設為在飽和區域動作。於本實施例，係使用D型之MOS電容量的例。特別是，將D型之MOS電容量之源極與汲極短路，於源極與汲極與阱構成的PN接合施加逆偏壓而加以控制為其特徵。
又，放大MOS3之閘極容量C1，浮置擴散7之容量C2雖具有電壓依存性，但就容量而言MOS電容量之容量C3比起其他二者較大，因此於畫素之動作電壓之範圍，感測器輸出電壓對於射入光量可以保有大略線形性。
圖5係表示D型之MOS電容量與PD部之重要部分斷面構造。於半導體基板1，形成由絕緣體(一般為由氧化膜形成)構成的元件分離區域15，藉由P型雜質添加而形成P阱14。接著，為調整構成畫素電路的電晶體之臨限值而進行雜質添加。作為該臨限值調整之雜質添加之一連 串工程之一部分，係進行N型雜質23之添加而將MOS電容量之臨限值設為空乏型。
之後之工程，係形成閘極電極18、22及雜質區域16、17、19、20、21、24。閘極電極18為傳送MOS1之閘極，閘極電極22為D型之MOS電容量4之閘極。雜質區域17為N型光二極體PD，雜質區域16為光二極體PD表面P型保護層。又，雜質區域19、20、21為N+ 擴散層，雜質區域19為浮置擴散FD，雜質區域20為D型之MOS電容量4之源極，雜質區域21為D型之MOS電容量4之汲極，雜質區域24為P+ 擴散層。
如圖1所示，雜質區域19與D型之MOS電容量4之閘極電極22及放大MOS係被連接，而構成接受光二極體PD所傳送的電荷，進行電荷電壓轉換的FD容量。
又，D型之MOS電容量4之源極20與汲極21係被短路，被施加電源電壓。P阱係連接於GND(接地電位)。因此於D型之MOS電容量之源極20(N+ )及汲極21(N+ )與P阱14之間形成PN接合，而且於D型之MOS電容量之源極20及汲極21，於PN接合係被施加逆偏壓的電源電位，存在於源極與汲極的多數載子(電子)受到熱能激發，而不會返回光二極體PD。
圖6係表示比較例，亦即對D型之MOS電容量之源極及汲極施加GND(接地電位)之例。又，除此以外均和圖5為同一。該情況下，D型之MOS電容量4之源極20及汲極21與P阱14之間之PN接合成為無偏壓狀態。因 此，於源極20及汲極21被熱能激發的電子會通過P阱14而返回光二極體PD(雜質區域17)而使暗電流增大。相對於此，藉由圖5之構造之使用時，結果，暗電流可以改善為1/10。
又，於實施例1，光二極體PD為N型，阱為P型，D型之MOS電容量之構成為N型，但可為將個別之導電型替換之構成。亦即，光二極體PD為P型，阱為N型，D型之MOS電容量之構成設為P型亦同樣可以形成。
[實施例2]
以下說明第2實施例之畫素構造。圖7為E型之MOS電容量4與PD部之重要部分斷面構造，圖8為圖7之構造所對應的CMOS影像感測器(畫素部)之電路圖。
和第1構成例同樣，於半導體基板1，形成由絕緣體(一般為由氧化膜形成)構成的元件分離區域15，藉由P型雜質添加而形成P阱14。接著，為調整構成畫素電路的電晶體之臨限值而進行雜質添加。作為該臨限值調整之雜質添加之一連串工程之一部分，係進行P型雜質27之添加而將MOS電容量4之臨限值設為增強型。
之後之工程，係形成閘極電極18、22及雜質區域16、17、19、20、21、24。閘極電極18為傳送MOS1之閘極，閘極電極22為E型之MOS電容量4’之閘極。雜質區域17為N型光二極體PD，雜質區域16為光二極體PD表面P型保護層。又，雜質區域19為N+ 擴散層，雜質區 域17、25、26為P+ 擴散層，雜質區域25為E型之MOS電容量4’之源極，雜質區域26為E型之MOS電容量4’之汲極。
如圖8所示，雜質區域19(浮置擴散FD)與E型之MOS電容量4’之閘極及放大MOS3係被連接，而構成接受光二極體PD所傳送的電荷，進行電荷電壓轉換的FD容量。
又，E型之MOS電容量4’之源極25與汲極26係被短路，被施加GND電壓(接地電壓)。又，P阱14係連接於GND電壓(接地電位)。構成MOS電容量4’的源極25與汲極26及臨限值調整層27，均由和P阱同一之P型構成，於源極25與汲極26與P阱14之間不存在PN接合。又，成為信號電荷之電子，於源極25與汲極26為少數載子，熱激發產生的電荷很少。因此，返回雜質區域19的電荷幾乎不存在。藉由適用圖7之構造，亦可獲得暗電流改善為1/10之結果。又，圖8之動作波形係和圖2同一。
於圖7之構成，構成E型之MOS電容量的源極25與汲極26，均由和P阱14為同一之導電型構成。圖9為更進一步縮小佈局面積之變形例，構成MOS電容量4’的源極25與汲極26，並未被配線層短路，可於基板內實施短路，亦即設為浮置狀態。如此則，畫素之佈局面積可以縮小。
結果，可以同時實現SN比之提升與動態範圍之擴大。
1‧‧‧傳送MOS
2‧‧‧重置MOS
3‧‧‧放大MOS
4，4’‧‧‧MOS電容量
5‧‧‧選擇MOS
6‧‧‧光二極體PD
7‧‧‧浮置擴散FD
8‧‧‧讀出線
9‧‧‧重置線
10‧‧‧選擇線
11‧‧‧信號線
12‧‧‧電源線
13‧‧‧GND線
14‧‧‧P阱
15‧‧‧元件分離區域
16‧‧‧光二極體PD表面P型保護層
17‧‧‧N型光二極體PD
18‧‧‧傳送MOS閘極
19‧‧‧浮置擴散FD
20‧‧‧D型之MOS電容量之源極
21‧‧‧D型之MOS電容量之汲極
22‧‧‧D型之MOS電容量之閘極
23‧‧‧D型之MOS電容量臨限值調整層
24‧‧‧P+ 擴散層
25‧‧‧E型之MOS電容量之源極
26‧‧‧MOS電容量之汲極
27‧‧‧E型之MOS電容量臨限值調整層
[圖1]實施例1之固態攝像裝置之畫素電路構成圖。
[圖2]CMOS影像感測器之動作時序圖。
[圖3]含有MOS電容量的元件之容量特性圖。
[圖4]CMOS影像感測器之輸出特性圖。
[圖5]實施例1之重要部分斷面圖。
[圖6]對圖5之比較例。
[圖7]實施例2之重要部分斷面圖。
[圖8]實施例2之固態攝像裝置之畫素電路構成圖。
[圖9]實施例2之重要部分斷面圖(變形例)。
1‧‧‧傳送MOS
14‧‧‧P阱
15‧‧‧元件分離區域
16‧‧‧光二極體PD表面P型保護層
17‧‧‧N型光二極體PD
18‧‧‧傳送MOS閘極
19‧‧‧浮置擴散FD
20‧‧‧D型之MOS電容量之源極
21‧‧‧D型之MOS電容量之汲極
22‧‧‧D型之MOS電容量之閘極
23‧‧‧D型之MOS電容量臨限值調整層
24‧‧‧P+ 擴散層。

Claims (1)

  1. 一種固態攝像裝置，係具有：P型之半導體區域；N型之光二極體，形成於上述半導體區域；及畫素，係具有：將上述光二極體產生的電子予以儲存的N型浮置擴散及上述浮置擴散(floating diffusion)之附加電容、亦即增強型(enhancement type)之MOS電容；上述MOS電容，於固態攝像裝置之動作電壓之範圍係呈飽和特性，為了減低是增強型之上述MOS電容的電壓依存性，使用具有比動作電壓的範圍還高的臨限值電壓之增強型之MOS電容，於上述半導體區域，被施加有接地電壓，於上述MOS電容之具有P型之源極/汲極區域，係被施加有接地電壓，或上述MOS電容之具有P型之源極/汲極區域，係被設為浮置狀態(floating)。
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