TWI483381B - Light emitting diode having plurality of light emitting cells and method of fabricating the same - Google Patents

Description

Light-emitting diode having a plurality of light-emitting units and method of manufacturing the same

The present invention relates to a light-emitting diode and a method of fabricating the same, and more particularly to a light-emitting diode having a plurality of light-emitting units, and a wire connecting the light-emitting units, and a dielectric layer protecting the light-emitting unit, and manufacturing thereof method.

Since the development of blue light-emitting diodes of GaN substrates, many different attempts have been made to improve the luminous efficacy of light-emitting diodes, and different structural improvements have been proposed for different applications. Blue or ultraviolet light-emitting diodes of GaN substrates are widely used in many fields, such as natural color light-emitting diode devices, light-emitting diode traffic signs, white light-emitting diodes, etc., and are expected to be used. It replaces the white fluorescent lamp in the general field of illumination.

In general, a light-emitting diode can emit light by applying a forward current and a supply of a direct current. Considering the forward current operating characteristics of the light-emitting diodes, some light-emitting diodes having a plurality of mutually parallel-connected light-emitting units or operating with a bridge rectifier by an AC power source have been developed. In addition, a plurality of light emitting diodes having a plurality of light emitting units formed on a single substrate and connected in series and connected in parallel to each other by a high voltage direct current power source are further developed. It emits light with high output and high performance. In these light-emitting diodes, these light-emitting units are formed on a single substrate and are connected to each other through a wire to emit light having high output and high efficiency by an alternating current or direct current power source.

An example of a "light-emitting device with light-emitting elements" (WO 2004/023568 A1) issued by Sakai et al. discloses an example of a light-emitting diode having a plurality of light-emitting units connected to a high-voltage alternating current or direct current power source.

These light-emitting units are connected to each other by Air-bridge Wires to provide a light-emitting diode that can be operated by an AC or DC current source.

However, the interconnection of the light-emitting units by the empty bridge wires may cause the reliability of the wires to decrease. This problem is caused by the insulation of the wires or the resistance of the wires due to external moisture or impact. In order to avoid these problems, wire bonding technology based on the Step-cover Process is adopted. The so-called stage covering process is a process of forming a wire on a dielectric layer covering the light emitting unit. As a result, since the wires are placed on the dielectric layer, they are more stable than the empty wires.

However, the wires formed by the stage-covering process are still exposed to the outside world and are still subject to moisture or external impacts leading to insulation. In a light-emitting diode having a plurality of light-emitting units, some wires are included, and if one of the wires becomes insulated, the light-emitting diodes cannot be used. In addition, since a plurality of wires are used in the light-emitting diode, moisture may invade the light-emitting unit along the wires, and thus the light-emitting efficiency of the light-emitting unit will be impaired.

On the other hand, when the light-emitting diode is used in practical applications, such as a conventional light source or a similar light source, it is necessary to recognize the diversity of colors such as white light through ultraviolet light conversion, or Blue light is converted to light having a higher wavelength by a fluorescent material. Traditionally, epoxies contain the above-described fluorescent materials, which are encapsulated in a package that emits short wavelengths. Light on the light-emitting diode. For these white light emitting diodes, a color conversion layer having a fluorescent material can be formed in the packaging process, and the process of the process and the LED chip are independent of each other, which makes the packaging process more complicated. Complex and leads to high failure rates in the packaging process. The cost loss caused by errors occurring during the packaging process is significantly higher than the cost loss caused by errors occurring during the LED wafer fabrication process.

The present invention is to solve the above-mentioned conventional problems and other problems, and an aspect of the present invention is to provide a light-emitting diode which can prevent the breakage of a wire and the resistance of a wire by intrusion of moisture or external impact. The increase or the efficiency of the light-emitting unit is lowered, and the manufacturing method of the light-emitting diode is also provided.

Another aspect of the present invention is to provide a light emitting diode including a dielectric layer to protect a wire and a light emitting unit, and having a bonding force between the dielectric layer and the underlying layer formed under the dielectric layer. And a method of manufacturing the light emitting diode.

Still another aspect of the present invention is to provide a light emitting diode comprising a fluorescent material capable of converting a wavelength of light emitted by a light emitting unit at a wafer level, and a method of manufacturing the light emitting diode.

According to one aspect, a light emitting diode includes: a plurality of light emitting units disposed apart from each other on a single substrate, and each of the light emitting units includes a lower semiconductor layer and an upper semiconductor layer, the upper semiconductor layer being located on the lower semiconductor layer On a region, and an active layer is located on the upper semiconductor layer and the lower semiconductor Between the layers; a first dielectric layer covering the entire surface of the light emitting unit, and having a plurality of openings formed on other regions of the lower semiconductor layer and on the upper semiconductor layer; a plurality of wires are formed on the first dielectric layer, And connecting adjacent light emitting units to each other through the opening; and a second dielectric layer covering the first dielectric layer and the wires. Here, the first dielectric layer and the second dielectric layer are formed of the same material, and the thickness of the first dielectric layer is thicker than the second dielectric layer.

Since the second dielectric layer covers the wires and the light-emitting unit, the wires and the light-emitting unit can be protected from moisture intrusion or impact from the outside. In addition, since the first dielectric layer and the second dielectric layer are formed of the same material, the bonding force between the first dielectric layer and the second dielectric layer can be improved, and the second dielectric layer can be avoided. Cracks occur. In addition, since the thickness of the first dielectric layer is thicker than that of the second dielectric layer, separation of the second dielectric layer can be avoided.

The first dielectric layer has a thickness of 4500 Å to 1 μm and the second dielectric layer has a thickness greater than 500 Å. If the thickness of the first dielectric layer is less than 4500 Å, an electrical disconnection may occur between the wires and the light-emitting unit. On the other hand, although the electrical disconnection between the wire and the light-emitting unit can be easily avoided by increasing the thickness of the first dielectric layer, if the first dielectric layer is too thick, the light conduction is impaired and the light is reduced. Luminous efficiency. Therefore, the first dielectric layer is preferably not more than 1 μm thick. In contrast, if the thickness of the second dielectric layer is less than 500 Å, it is difficult to protect the light-emitting diode from moisture intrusion from the outside.

Here, the thickness of the first dielectric layer and the second dielectric layer can be referred to when The thickness of the first dielectric layer and the second dielectric layer formed on a planar substrate is not limited thereto. Generally, the actual thickness of the first dielectric layer and the second dielectric layer in the light emitting diode is thinner than the above thickness.

The first dielectric layer and the second dielectric layer may be formed of a ruthenium oxide layer or a tantalum nitride layer formed by plasma enhanced CVD. The ruthenium oxide layer or the tantalum nitride layer can be deposited at a temperature between 200 and 300 °C.

In particular, the second dielectric layer is deposited over a temperature range between -20 and +20% of the deposition temperature of the first dielectric layer. In plasma enhanced CVD, the quality of the deposited layer varies significantly depending on the deposition temperature. Therefore, the first dielectric layer and the second dielectric layer can be deposited at substantially the same temperature to improve the bonding force between the first dielectric layer and the second dielectric layer.

In another aspect, the wire can have a multilayer structure including a lower layer connecting the first dielectric layer and an upper layer connecting the second dielectric layer. The lower layer may be a Cr layer or a Ti layer, and the upper layer may also be a Cr layer or a Ti layer. In particular, when the first dielectric layer is an oxide layer or a nitride layer, the Cr layer or the Ti layer can be strongly bonded to the first dielectric layer. Further, by heat-treating the Cr layer or the Ti layer, the bonding force can also be improved. Further, an Au layer, an Au/Ni layer, or an Au/Al layer may be disposed between the upper layer and the lower layer.

The first dielectric layer and the second dielectric layer may be formed using a polymer such as spin-on-glass (SOG) or benzocyclobutene (BCB). Since these layers can be formed by spin coating, the layers can be fabricated using a very simple process. Additionally, the second dielectric layer can contain a phosphor in at least a portion of the region. Therefore, white light or other colored light can be obtained at the wafer level.

Alternatively, a phosphor layer may be formed on the second dielectric layer. The phosphor layer can also be applied to the second dielectric layer by, for example, a mixture of a resin and a phosphor, or by application of electrophoresis.

In another aspect, the transparent electrode layer can be disposed between the first dielectric layer and the upper semiconductor layer. The transparent electrode layer can be formed by indium tin oxide (ITO) or a transparent metal. When the transparent electrode layer is formed of a transparent metal, it may be a metal selected from at least a combination of Au, Ni, Pt, Al, Cr, and Ti.

The wire may be electrically connected to the upper semiconductor layer through the transparent electrode layer. The transparent electrode layer may have a plurality of openings through which the upper semiconductor layer is exposed, and the openings are filled with wires.

According to another aspect of the present invention, a method of fabricating a light emitting diode includes: forming a plurality of light emitting cells separated from each other on a single substrate, and each of the light emitting cells includes a lower semiconductor layer and an upper semiconductor layer Located on a region of the lower semiconductor layer, and an active layer between the upper semiconductor layer and the lower semiconductor layer; forming a first dielectric layer covering the entire surface of the light emitting unit, and on the other regions of the lower semiconductor layer and the upper semiconductor Forming a plurality of openings on the layer; forming a plurality of wires on the first dielectric layer, and electrically connecting adjacent light emitting units to each other through the opening; and forming a second dielectric layer covering the first dielectric layer and On the wire. The first dielectric layer and the second dielectric layer are formed of the same material, and the thickness of the first dielectric layer is thicker than the thickness of the second dielectric layer.

Therefore, the present invention can protect the wire and the light emitting unit from external moisture or impact, and can improve the first dielectric layer and the second dielectric The bonding force between the layers.

The first dielectric layer has a thickness of 4500 Å to 1 μm and the second dielectric layer has a thickness greater than 500 Å. The first dielectric layer and the second dielectric layer are a hafnium oxide layer or a tantalum nitride layer deposited by a plasma enhanced CVD method at a temperature between 200 and 300 °C. Further, the second dielectric layer is deposited in a temperature range between -20 and +20% of the deposition temperature of the first dielectric layer.

In another aspect, the wire includes a lower layer connecting the first dielectric layer and an upper layer connecting the second dielectric layer. Here, the lower layer may be a Cr layer or a Ti layer, and the upper layer may also be a Cr layer or a Ti layer. Furthermore, the wires may be heat treated prior to forming the second dielectric layer to improve interfacial bonding characteristics between the wires and the first dielectric layer. Here, the wires can be heat treated at a temperature between 300 and 500 °C.

In some embodiments disclosed, the first dielectric layer and the second dielectric layer can be formed from a polymer. Further, the second dielectric layer may contain a phosphor.

In other embodiments disclosed, a phosphor layer can be formed on the second dielectric layer. The phosphor layer may also be applied to the second dielectric layer by application of electrophoresis, or for example, a mixture of a resin and a phosphor, which is dispersed in a resin by a phosphor.

The step of forming a plurality of light emitting units includes forming a transparent electrode layer on the upper semiconductor layer. The transparent electrode layer is heat treated at a temperature between 500 and 800 °C. The transparent electrode layer has an opening through which the upper semiconductor layer can be exposed, and the opening is filled with a wire.

The above described features and advantages of the present invention will be more apparent from the following description.

In the following description, the present invention will be described in detail with reference to the accompanying drawings. The present invention will be fully appreciated by those skilled in the art from this disclosure. It will be apparent that the system, process or implement of the present invention is subject to change without departing from the scope of the invention. It should also be noted that the drawing is not based on precise dimensions, and some dimensions are enlarged to make the description of the schema clear. In addition, in the description and drawings, like elements are recited as similar element symbols.

1 is a cross-sectional view of a light emitting diode in accordance with an embodiment of the present invention.

Referring to FIG. 1 , the light emitting diode provided in this embodiment includes a substrate 51 , a plurality of light emitting units 56 , a first dielectric layer 63 , a wire 65 , and a second dielectric layer 67 , and additionally includes a buffer layer 53 and a transparent layer. Electrode layer 61 and phosphor layer 69. The substrate 51 may be an insulating substrate such as a sapphire substrate.

The plurality of light emitting units 56 are disposed apart from each other on the single substrate 51. Each of the light emitting units 56 includes a lower semiconductor layer 55, an upper semiconductor layer 59 disposed on a partial region of the lower semiconductor layer 55, and an active layer 57 interposed between the upper and lower semiconductor layers. The upper semiconductor layer 59 and the lower semiconductor layer 55 may be n-type and p-type semiconductor layers, respectively, or in an opposite configuration.

The lower semiconductor 55, the active layer 57, and the upper semiconductor layer 59 may be formed of a material of a Ga-N substrate, that is, (Al, In, Ga)N. The composition of the active layer 57 determines that the emitted light has a desired wavelength, such as ultraviolet light or blue light. The materials of the lower and upper semiconductor layers 55 and 59 are required to have a higher band gap energy than the active layer 57.

The lower semiconductor layer 55 and/or the upper semiconductor layer 59 may form a single layer structure as shown or form a multilayer structure. Additionally, active layer 57 can have a single or multiple quantum well structures.

The buffer layer 53 may be placed between the light emitting unit 56 and the substrate 51. The buffer layer 53 is for reducing the lattice misalignment between the substrate 51 and the lower semiconductor layer 55.

The first dielectric layer 63 covers the entire surface of the light emitting unit 56. The first dielectric layer 63 has a plurality of openings formed on other regions of the lower semiconductor layer 55, and these regions are adjacent to the region having the semiconductor layer 55 under the upper semiconductor layer 59, and a plurality of openings are formed in the upper semiconductor On layer 59. These openings are separated from each other such that the sidewalls of the light emitting unit 56 are covered by the first dielectric layer 63. The first dielectric layer 63 also covers the area of the substrate 51 between the light emitting units 56. The first dielectric layer 63 may be a tantalum oxide layer (SiO ₂ ) or an oxynitride layer, and may be formed by plasma enhanced CVD at 200 to 300 ° C. Here, the first dielectric layer 63 has a thickness of 4,500 Å to 1 μm. If the thickness of the first dielectric layer 63 is less than 4500 Å, the thickness of the first dielectric layer 63 may be relatively reduced on the low side of the light emitting unit due to the layer covering characteristics, and electrical insulation may be formed in the light emitting unit 56 and Occurs between the wires 65 on the first dielectric layer 63. On the other hand, although electrical insulation between the wire 65 and the light emitting unit 56 can be easily avoided by increasing the thickness of the first dielectric layer 63, the first dielectric layer 63 is too thick to impair light conduction, thereby reducing light emission. effectiveness. Therefore, the thickness of the first dielectric layer is preferably not more than 1 μm.

On the other hand, a wire 65 is formed on the first dielectric layer 63. The wires 65 are electrically connected to the lower and upper semiconductor layers 55 and 59 through the openings. In addition, guide Line 65 can also interconnect the lower semiconductor layer 55 and the upper semiconductor layer 59 of adjacent light emitting cells 56 to form a series array of light emitting cells 56. Multiple series arrays can be formed and interconnected in anti-parallel, operating with an AC power source. In addition, a bridge rectifier (not shown) can form a series array connected to the light unit 56, so that the bridge rectifier can drive the light units 56 by an alternating current source. The bridge rectifier can be formed by connecting a plurality of light-emitting units 56 of the same structure, and the light-emitting units are connected to each other by wires 65.

The wires 65 may be selected to connect the lower semiconductor layer 55 or the upper semiconductor layer 59 of the light-emitting units adjacent to each other. In this way, the plurality of light emitting units 56 can be connected to each other in series or in parallel.

The wire 65 may be formed of a conductive material such as a metal or tantalum doping material such as a polysilicon material. In particular, the wires 65 may form a multilayer structure and may include a lower layer 65a of Cr or Ti, and an upper layer 65c of Cr or Ti. Further, an intermediate layer 65b of Au, Au/Ni or Au/Al is disposed between the lower layer 65a and the upper layer 65c.

On the other hand, the transparent electrode layer 61 may be disposed between the upper semiconductor layer 59 and the first dielectric layer 63. The transparent electrode layer 61 can be exposed through an opening formed in the upper semiconductor layer 59. The transparent electrode layer 61 allows light generated from the active layer 57 to penetrate, and can supply a current to the upper semiconductor layer 59 in a dispersed manner. The wire 65 may be connected to expose the transparent electrode layer 61 through the opening to electrically connect the upper semiconductor layer 59. Further, the transparent electrode layer 61 may have an opening through which the upper semiconductor layer 59 may be exposed, and the wire 65 fills the opening in the transparent electrode layer 61.

The second dielectric layer 67 covers the wires 65 and the first dielectric layer 63. The second dielectric layer 67 protects the wires 65 from moisture and the like, and also protects the wires 65 and the light-emitting unit 56 from external impact damage.

The second dielectric layer 67 may be formed of tantalum oxide (SiO ₂ ) or tantalum nitride, which is the same material as the first dielectric layer 63. Like the first dielectric layer 63, the second dielectric layer 67 can also be formed by plasma enhanced CVD at a temperature of 200 to 300 °C. When the first dielectric layer 63 is formed by plasma enhanced CVD, the second dielectric layer 67 may be formed at a temperature in the range of -20 to +20% of the deposition temperature of the first dielectric layer 63. Preferably, the deposition temperature of the second dielectric layer 67 is the same as the deposition temperature of the first dielectric layer 63.

This can be confirmed by Figure 2, which is a graph showing the passivity reliability test of samples sampled at deposition temperatures of the first and second dielectric layers. In the reliability test, a ruthenium oxide layer was deposited as a first dielectric layer 63 at 250 ° C to prepare a sample, and when the temperature of the deposition was changed, another ruthenium oxide layer was deposited as the second dielectric layer 67. The reliability test was carried out for 1000 hours. In this test, 20 samples were made using different deposition temperatures of the second dielectric layer 67, and each sample was tested under wet conditions. Referring to FIG. 2, when the second dielectric layer 67 is deposited at a temperature within a temperature range of -20 to +20% of the deposition temperature (250 ° C) of the first dielectric layer 63, the sample may be better. Reliability. On the other hand, when the deposition temperature of the second dielectric layer 67 exceeds the above range, the reliability is rapidly lowered. Further, when the first and second dielectric layers 63, 67 are deposited at the same temperature, the success rate is 100%, which is the highest reliability.

In addition, the second dielectric layer 67 is thinner than the first dielectric layer 63 and has a thickness of 500 Å or more. Since the second dielectric layer 67 is thinner than the first dielectric layer 63, the second dielectric layer 67 can avoid separation from the first dielectric layer 63. If the thickness of the second dielectric layer 67 is less than 500 Å, the wire and the light-emitting unit cannot be protected under the influence of external impact and moisture.

The phosphor layer 69 may be contained in a resin or deposited in electrophoresis. The phosphor layer 69 covers the second dielectric layer 67 and converts the wavelength of the light emitted by the light emitting unit 56.

3 to 9 are cross-sectional views showing a method of fabricating a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 3, a lower semiconductor layer 55, an active layer 57, and an upper semiconductor layer 59 are formed on the substrate 51. Further, the buffer layer 53 may be formed on the substrate 51 before the lower semiconductor layer 55 is formed.

The material of the substrate 51 may include, but is not limited to, sapphire (Al ₂ O ₃ ), tantalum carbide (SiC), zinc oxide (ZnO), bismuth (Si), gallium arsenide (GaAs), gallium phosphide (GaP), Lithium aluminum compound (LiAl ₂ O ₃ ), boron nitride (BN), aluminum nitride (AlN), or gallium nitride (GaN), and other materials may be selected depending on the semiconductor layer formed thereon.

The buffer layer 53 is formed to dissolve the lattice misalignment between the substrate 51 and the semiconductor layer 55, and may be formed of, for example, gallium nitride (GaN) or aluminum nitride (AlN). If the substrate 51 is a conductive substrate, the buffer layer 53 may be formed of an insulating or semi-insulating layer, and may be formed of AlN or semi-insulating GaN.

The lower semiconductor layer 55, the active layer 57, and the upper semiconductor layer 59 may be composed of The material of the GaN matrix, that is, (Al, In, Ga)N, is formed. The lower semiconductor layer 55, the upper semiconductor layer 59, and the active layer 57 may be intermittently or continuously formed by organometallic vapor phase chemical deposition (MOCVD), molecular beam epitaxy, mixed vapor epitaxy (HVPE), or the like. grow into.

Here, the upper and lower semiconductor layers 59, 55 may be n-type and p-type semiconductor layers, respectively, or in an opposite configuration. In the synthetic semiconductor layer of the GaN matrix, the n-type semiconductor layer may be formed by hetero-doping, such as doping Si, and the p-type semiconductor layer may also be formed by hetero-doping, such as doping Mg.

Referring to FIG. 4, the light emitting unit 56 is formed separately from each other by patterning the upper semiconductor layer 59, the active layer 57, and the lower semiconductor layer 55. In this step, the upper semiconductor layer 59 is on a region of the lower semiconductor layer 55, and the other regions of the lower semiconductor layer 55 are exposed. In addition, the buffer layer 53 between the light emitting units 56 is removed to expose the substrate 51.

Referring to FIG. 5, a transparent electrode layer 61 is formed over the semiconductor layer 59 above the light emitting unit 56. The transparent electrode layer 61 can be formed using an oxidized metal such as ITO or a transparent metal. In the case of a transparent metal, the transparent electrode layer 61 may be selected from a combination including at least Au, Ni, Pt, Al, Cr, and Ti, or an alloy thereof.

The transparent electrode layer 61 may have an opening 61a, and the upper semiconductor layer 59 may be exposed through the opening 61a. Although the transparent electrode layer 61 may be formed on the light emitting unit 56 by deposition, the transparent electrode layer 61 may be formed on the upper semiconductor layer 59 before the formation of the light emitting unit 56, and then before the upper semiconductor layer 59 is patterned First patterned.

The transparent electrode layer 61 can be heated to 500 to 800 ° C, and the upper half Conductor layer 59 forms an ohmic contact.

Referring to FIG. 6, a first dielectric layer 63 is formed overlying the substrate 51 having the light emitting unit 56. The first dielectric layer 63 covers the side walls and the upper surface of the light emitting unit 56, and covers the upper surface of the region of the substrate 51 between the light emitting units 56. The first dielectric layer 63 may, for example, form a hafnium oxide layer or a tantalum nitride layer by plasma enhanced CVD. In this case, the first dielectric layer 63 may be deposited between 200 and 300 ° C and has a thickness of 4,500 Å to 1 μm.

Next, the first dielectric layer 63 is patterned to form an opening 63a on the upper semiconductor layer 59, and an opening 63b is formed on other regions of the lower semiconductor layer 55. When the transparent electrode layer 61 is formed, the transparent electrode layer 61 is exposed through the opening 63a. When the transparent electrode layer 61 has the opening 61a, the opening 61a of the transparent electrode layer 61 is exposed through the opening 63a of the first dielectric layer 63.

Referring to FIG. 7, a wire 65 is formed on the first dielectric layer 63 having the opening 63a. The wires 65 are electrically connected to the lower semiconductor layer 55 and the upper semiconductor layer 59 through the openings 63a and 63b, and the adjacent light emitting cells 56 are connected to each other.

The wire 65 can be formed by electroplating, general electron beam deposition, CVD, or physical vapor deposition (PVD).

Further, the wires 65 may be formed of a conductive material such as a metal or tantalum doping material such as polysilicon. In particular, the wires 65 may form a multilayer structure and may include a lower layer 65a such as Cr or Ti, and an upper layer 65c of Cr or Ti (as shown in FIG. 1). In addition, an intermediate layer 65b of Au, Au/Ni, or Au/Al is disposed between the lower layer 65a and the upper layer 65c (eg, Figure 1). The wire 65 may be heat-treated at 300 to 500 ° C to reinforce the bonding force between the wire 65 and the first dielectric layer 63.

Referring to FIG. 8, a second dielectric layer 67 is formed overlying the substrate 51, and the substrate 51 has wires 65 formed thereon. The second dielectric layer 67 covers the wires 65 and the first dielectric layer 63. The material of the second dielectric layer 67 may be the same as the first dielectric layer 63, such as yttrium oxide (SiO ₂ ) or tantalum nitride, and the second dielectric layer 67 may be reinforced by plasma CVD at 200~300. Formed between °C. In particular, the second dielectric layer 67 is formed over a temperature range between -20 and +20% of the deposition temperature of the first dielectric layer 63.

Referring to FIG. 9, a phosphor layer 69 may be formed on the second dielectric layer 67. The phosphor layer 69 may be coated on the second dielectric layer 67 using a mixture of a resin and a phosphor, wherein the above mixture may be prepared by dispersing a phosphor into the resin or by electrophoresis. The result is configured as a wafer-level light-emitting diode with a fluorescent material.

FIG. 10 is a cross-sectional view showing a light emitting diode according to another embodiment of the present invention. In this light-emitting diode, a polymer is used as the first and second dielectric layers.

Referring to FIG. 10, the light emitting diode may include a substrate 51, a plurality of light emitting units 56, a first dielectric layer 83, a wire 85, and a second dielectric layer 87, and may further include a buffer layer 53 and a transparent electrode layer 61. . Here, the substrate 51, the light-emitting unit 56, and the transparent electrode layer 61 are all the same as those of the above-described embodiment, and thus the description will be omitted below.

The first dielectric layer 83 may be formed of SOG, BCG or other transparent polymer to fill the space between the light emitting units 56. First dielectric layer 83 covers the other areas of the lower semiconductor layer 55. In this embodiment, the first dielectric layer 83 has a plurality of openings through which the lower semiconductor layer 55 can be exposed. In addition, the first dielectric layer 83 also exposes the upper semiconductor layer 59 or the transparent electrode layer 61. The sidewall of the light emitting unit 56 is covered by the first dielectric layer 83.

A wire 85 is formed on the first dielectric layer 83, which is electrically connected to the lower semiconductor layer 55 and the upper semiconductor layer 59. The wire 85 is electrically connected to the lower semiconductor layer 55 and the upper semiconductor layer 59 through the above-described openings. In addition, the wires 85 interconnect the lower semiconductor layer 55 and the upper semiconductor layer 59 of the adjacent light emitting cells 56 to form a series array of light emitting cells 56. Multiple series arrays can be formed and connected in reverse parallel to each other to operate through an AC power source. In addition, the series array of the light-emitting units 56 is also connected to a bridge rectifier (not shown), so the light-emitting unit 56 can be driven by the bridge rectifier through the AC power source. The bridge rectifier can be formed by connecting a plurality of light-emitting units, and the light-emitting units have the same structure, that is, the light-emitting units 56 are connected to each other by the wires 85.

Alternatively, the wires 85 may be connected to each other to the lower semiconductor layer 55 or the upper semiconductor layer 59 of the adjacent light-emitting unit 56. In this way, the light emitting units 56 can be connected to each other in series or in parallel.

The wire 85 may be formed of a conductive material such as a metal or a germanium doped material such as a polysilicon. In particular, the wires 85 may form a multilayer structure.

The second dielectric layer 87 covers the wires 85 and the first dielectric layer 83. The second dielectric layer 87 is formed using the same polymer as the first dielectric layer 83. therefore, The bonding force between the first dielectric layer 83 and the second dielectric layer 87 can be increased. In addition, the second dielectric layer 87 may be thinner than the first dielectric layer 83, which fills the space between the light emitting units 56.

On the other hand, the second dielectric layer 87 may contain a phosphor. Therefore, it is possible to provide the ability of the light-emitting diode to have a wafer-level conversion wavelength.

In this embodiment, since the first dielectric layer is formed of a polymer, the wire 85 and the second dielectric layer 87 can be formed on the relatively flat first dielectric layer 83, thereby enhancing the wire. Reliability.

11 to 13 are cross-sectional views showing a method of fabricating a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 11, on the substrate 51, a plurality of light-emitting units 56 and transparent electrode layers 61 separated from each other may be formed as described above in FIGS. 3 to 5. Each of the light emitting units 56 includes a lower semiconductor layer 55, an active layer 57, and an upper semiconductor layer 59. The transparent electrode layer 61 has a plurality of openings 61a through which the upper semiconductor layer 59 can be exposed.

Referring to FIG. 12, a first dielectric layer 83 is formed overlying the light emitting unit 56 and the transparent electrode layer 61. The first dielectric layer 83 is formed of a polymer and fills the space between the light emitting units 56 when covering the entire surface of the light emitting unit 56.

Referring to FIG. 13, the first dielectric layer 83 removes portions by etching and exposes the transparent electrode layer 61. Next, a wire 85 is formed on the first dielectric layer 83 and the light emitting unit 56. Conductor 85 can be formed using any of the materials described above with respect to FIG.

Next, the second dielectric layer 87 (shown in FIG. 10) is formed to cover Line 85 and first dielectric layer 83. The second dielectric layer 87 is formed using the same polymer as the first dielectric layer 83, and may contain a phosphor.

On the other hand, when the second dielectric layer 87 is thicker than the first dielectric layer 83, the light transmittance is lowered, and when externally impacted, the first dielectric layer 83 or the second dielectric layer 87 is removed from the external dielectric layer 87. The illumination unit 56 begins to form a separation. Therefore, the second dielectric layer 87 needs to be thinner than the first dielectric layer 83 (here, the thickness of the first dielectric layer 83 is the space between the light-emitting units 56).

In the present embodiment, the phosphor is added to the second dielectric layer 87, but may also be added to the first dielectric layer 83. In addition, an increased phosphor layer can also be formed on the second dielectric layer 87.

According to the disclosed embodiment, the first and second dielectric layers are formed of the same material, and the first dielectric layer is formed thicker than the second dielectric layer, thereby enhancing the first and second Bonding forces between the dielectric layers to prevent splitting of the second dielectric layer. In addition, the second dielectric layer covers the wires and the light-emitting unit, thereby protecting the moisture intrusion of the light-emitting diodes, and protecting the wires and the light-emitting unit from external impact.

In addition, the Cr layer or the Ti layer provided as the lower layer and the upper layer of the wire exhibits a high bonding force with the corresponding dielectric layer, and can also promote the bonding force between the wire and the dielectric layer, thereby protecting The second dielectric layer splits.

In addition, the second dielectric layer contains a phosphor or a phosphor layer is formed on the second dielectric layer to obtain white light or other colors of light at the wafer level, thereby simplifying the packaging process.

Although the invention has been disclosed above by way of example, it is not intended to be limiting The scope of the present invention is defined by the scope of the appended claims, and the scope of the invention is defined by the scope of the appended claims. Prevail.

51‧‧‧Substrate

53‧‧‧buffer layer

55, 59‧‧‧ semiconductor layer

56‧‧‧Lighting unit

57‧‧‧Active layer

61‧‧‧Transparent electrode layer

61a, 63a, 63b‧‧‧ openings

63, 67, 83, 87‧‧‧ dielectric layers

65, 85‧‧‧ wires

65a‧‧‧Under

65b‧‧‧ Middle

65c‧‧‧Upper

69‧‧‧phosphor layer

1 is a cross-sectional view of a light emitting diode in accordance with an embodiment of the present invention.

2 is a graph showing reliability tests of deposition temperatures and reliability pass rates for the first and second dielectric layers.

3 to 9 are cross-sectional views showing a method of fabricating a light emitting diode according to an embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a light emitting diode according to another embodiment of the present invention.

11 to 13 are cross-sectional views showing a method of fabricating a light emitting diode according to another embodiment of the present invention.

51‧‧‧Substrate

53‧‧‧buffer layer

55, 59‧‧‧ semiconductor layer

56‧‧‧Lighting unit

57‧‧‧Active layer

61‧‧‧Transparent electrode layer

63, 67‧‧‧ dielectric layer

65‧‧‧Wire

65a‧‧‧Under

65b‧‧‧ Middle

65c‧‧‧Upper

69‧‧‧phosphor layer

Claims (28)

A light emitting diode comprising: a plurality of light emitting units disposed apart from each other on a single substrate, wherein each light emitting unit comprises a lower semiconductor layer and an upper semiconductor layer, and the upper semiconductor layer is located in a region of the lower semiconductor layer And an active layer is located between the upper semiconductor layer and the lower semiconductor layer; a first dielectric layer covering the entire surface of the light emitting units and having a plurality of openings formed in other regions of the lower semiconductor layer Upper and upper semiconductor layers; a plurality of wires formed on the first dielectric layer and electrically connected to adjacent light-emitting units through the openings; and a second dielectric layer overlying the a first dielectric layer and the plurality of dielectric layers, wherein the first dielectric layer and the second dielectric layer are formed of the same material, and the first dielectric layer has a thickness greater than that of the second dielectric layer The thickness is also thick. The light-emitting diode of claim 1, wherein the first dielectric layer has a thickness of 4500 Å to 1 μm, and the second dielectric layer has a thickness greater than 500 Å. The illuminating diode of claim 2, wherein the first dielectric layer and the second dielectric layer are yttria layers, which are reinforced by plasma to a temperature between 200 and 300 ° C. Perform deposition. The light-emitting diode of claim 3, wherein the second dielectric layer is deposited in a temperature range between -20 and +20% of a deposition temperature of the first dielectric layer. The light-emitting diode of claim 2, wherein the wires have a multilayer structure including a lower layer connecting the first dielectric layer and an upper layer connecting the second dielectric layer, The upper layer and the lower layer are a Cr layer or a Ti layer. The light-emitting diode according to claim 5, wherein an Au layer, an Au/Ni layer or an Au/Al layer is further disposed between the upper layer and the lower layer. The light-emitting diode of claim 2, wherein the first dielectric layer and the second dielectric layer are formed of tantalum nitride. The light-emitting diode of claim 1, wherein the first dielectric layer and the second dielectric layer are formed of a polymer. The light-emitting diode of claim 8, wherein the second dielectric layer contains a phosphor at least in a portion thereof. The light-emitting diode of claim 1, wherein a phosphor layer is further disposed on the second dielectric layer. The light-emitting diode according to claim 1, wherein a plurality of transparent electrode layers are further disposed between the first dielectric layer and the upper semiconductor layer. The light-emitting diode according to claim 11, wherein the transparent electrode layers are formed of ITO. The light-emitting diode according to claim 11, wherein the transparent electrode layers comprise at least one metal selected from the group consisting of Au, Ni, Pt, Al, Cr and Ti. The light-emitting diode according to claim 11, wherein The transparent electrode layers have a plurality of openings, and the upper semiconductor layers are exposed through the openings of the transparent electrode layers, and the wires fill the openings of the transparent electrode layers. A manufacturing method of a light emitting diode, comprising the steps of: forming a plurality of light emitting units, which are disposed apart from each other on a single substrate, and each of the light emitting units includes a lower semiconductor layer and an upper semiconductor layer, and the upper semiconductor layer is located A region of the lower semiconductor layer and an active layer are located between the upper semiconductor layer and the lower semiconductor layer; forming a first dielectric layer covering the entire surface of the light emitting units and having a plurality of openings formed therein And forming a plurality of wires on the first dielectric layer, and electrically connecting adjacent light-emitting units to each other through the openings; and forming a second dielectric layer An electrical layer covering the first dielectric layer and the wires, wherein the first dielectric layer and the second dielectric layer are formed of the same material, and the thickness of the first dielectric layer is greater than The thickness of the second dielectric layer is also thick. The method for fabricating a light-emitting diode according to claim 15, wherein the first dielectric layer has a thickness of 4500 Å to 1 μm, and the second dielectric layer has a thickness greater than 500 Å. The method for fabricating a light-emitting diode according to claim 16, wherein the first dielectric layer and the second dielectric layer are ruthenium oxide layers, which are enhanced by plasma to CVD at 200 to 300 ° C. Temperature between product. The method for fabricating a light-emitting diode according to claim 17, wherein the second dielectric layer is performed within a temperature range of -20 to +20% of a deposition temperature of the first dielectric layer. Deposition. The method for manufacturing a light-emitting diode according to claim 16, wherein the wires have a multi-layer structure including a lower layer connecting the first dielectric layer, and a second dielectric layer An upper layer and the lower layer are a Cr layer or a Ti layer. The method for manufacturing a light-emitting diode according to claim 19, further comprising heating the wires to form the wires and the first dielectric layer before forming the second dielectric layer Inter-joining characteristics. The method for producing a light-emitting diode according to claim 20, wherein the wires are heat-treated at a temperature between 300 and 500 °C. The method for fabricating a light-emitting diode according to claim 16, wherein the first dielectric layer and the second dielectric layer are ruthenium oxide layers formed by plasma enhanced CVD. The method of manufacturing a light-emitting diode according to claim 15, wherein the first dielectric layer and the second dielectric layer are formed of a polymer. The method for producing a light-emitting diode according to claim 23, wherein the second dielectric layer contains a phosphor. The method for fabricating a light-emitting diode according to claim 15, further comprising forming a phosphor layer on the second dielectric layer. The method of manufacturing a light-emitting diode according to claim 15, wherein the step of forming a plurality of light-emitting units comprises forming a transparent electrode layer on the upper semiconductor layer. The method for producing a light-emitting diode according to claim 26, wherein the transparent electrode layer is heat-treated at a temperature between 500 and 800 °C. The method for manufacturing a light-emitting diode according to claim 26, wherein the transparent electrode layer has an opening, and the upper semiconductor layer is exposed through an opening of the transparent electrode layer, and the wires are filled The opening of the transparent electrode layer.