JPH03284886A - Semiconductor element and forming method therefor - Google Patents
Semiconductor element and forming method thereforInfo
- Publication number
- JPH03284886A JPH03284886A JP2174061A JP17406190A JPH03284886A JP H03284886 A JPH03284886 A JP H03284886A JP 2174061 A JP2174061 A JP 2174061A JP 17406190 A JP17406190 A JP 17406190A JP H03284886 A JPH03284886 A JP H03284886A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor
- electrode
- substrate
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 238000000034 method Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000002184 metal Substances 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 238000002161 passivation Methods 0.000 claims abstract description 21
- 230000001681 protective effect Effects 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 abstract description 43
- 229910052760 oxygen Inorganic materials 0.000 abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 7
- 239000001301 oxygen Substances 0.000 abstract description 7
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 abstract description 5
- 239000011247 coating layer Substances 0.000 abstract description 5
- 229910017604 nitric acid Inorganic materials 0.000 abstract description 5
- 239000011347 resin Substances 0.000 abstract description 5
- 229920005989 resin Polymers 0.000 abstract description 5
- 229910052697 platinum Inorganic materials 0.000 abstract description 4
- 230000001747 exhibiting effect Effects 0.000 abstract description 3
- 229910052737 gold Inorganic materials 0.000 abstract description 3
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000007738 vacuum evaporation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 235000013842 nitrous oxide Nutrition 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- BSWGGJHLVUUXTL-UHFFFAOYSA-N silver zinc Chemical compound [Zn].[Ag] BSWGGJHLVUUXTL-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体素子およびその形成方法に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor device and a method for forming the same.
（従来の技術）
従来、発光ダイオードなどの半導体素子は、第３図に示
すように、例えばｎ型シリコン基板などから成る半導体
基板１上に、ｎ型ＧａＡｓ膜とｐ型ＧａＡｓ膜とから成
る半導体膜２、若しくはｎ型ＧａＡｓ膜、ｎ型ＡｌＧａ
Ａｓ膜、ｐ型ＡｌＧａＡｓ膜、およびｐ型ＧａＡｓ膜な
どから成る半導体膜２を形成して、半導体膜２の周辺部
に窒化シリコン（Ｓｉ、Ｎア）膜または酸化シリコン（
Ｓｔ、Ｏア）膜などから成るパッシベーション膜３を形
成して、半導体基板ｌの裏面側に裏面電極４を形成して
、半導体膜２上に表面電極５を形成して構成されていた
。(Prior Art) Conventionally, as shown in FIG. 3, semiconductor devices such as light emitting diodes have been manufactured using a semiconductor device made of an n-type GaAs film and a p-type GaAs film on a semiconductor substrate 1 made of, for example, an n-type silicon substrate. Film 2, or n-type GaAs film, n-type AlGa
A semiconductor film 2 made of an As film, a p-type AlGaAs film, a p-type GaAs film, etc. is formed, and a silicon nitride (Si, Na) film or a silicon oxide (Si) film is formed around the semiconductor film 2.
A passivation film 3 made of a St, O, etc. film was formed, a back electrode 4 was formed on the back side of the semiconductor substrate l, and a front electrode 5 was formed on the semiconductor film 2.
なお、従来の半導体素子には、第３図の６に相当する部
分はない。Note that the conventional semiconductor device does not have a portion corresponding to 6 in FIG. 3.
このような半導体素子は、第２図に示すような工程で形
成されていた。Such a semiconductor element has been formed by a process as shown in FIG.
すなわち、半導体基板１の表面側全面に半導体膜２を例
えばエピタキシャル成長法などで形成して、周辺部をＨ
２ＳＯ，／Ｈ２０□溶液などてメサエッチングして断面
台形状に形成する。That is, the semiconductor film 2 is formed on the entire surface side of the semiconductor substrate 1 by, for example, an epitaxial growth method, and the peripheral portion is
Mesa etching is performed using 2SO, /H20□ solution, etc. to form a trapezoidal cross section.
次に、半導体膜２上に、窒化シリコン（ＳｉｘＮア）膜
または酸化シリコン（Ｓｉ、Ｏア）膜などから成るパッ
シベーション膜３を形成する。Next, a passivation film 3 made of a silicon nitride (SixN) film or a silicon oxide (Si, O) film is formed on the semiconductor film 2.
次に、パッシベーション膜３の半導体膜２上と半導体基
板１の裏面側をＨＦ／ＮＨ，Ｆ溶液などを使ったフォト
リソ技術でエツチング除去して整形する。Next, the top of the semiconductor film 2 of the passivation film 3 and the back side of the semiconductor substrate 1 are removed and shaped by photolithography using a HF/NH, F solution or the like.
次に、パッシベーション膜３上に、半導体膜２の最上層
であるｐ型ＧａＡｓ膜などとオーミック性を示すＡｇま
たはＡｇ−Ｚｎ膜などから成る表面金属層を形成する。Next, a surface metal layer consisting of a p-type GaAs film or the like which is the uppermost layer of the semiconductor film 2 and an Ag or Ag--Zn film exhibiting ohmic properties is formed on the passivation film 3.
次に、半導体膜２上部分を残してＨＮＯ３溶液などを使
ったフォトリソ技術でエツチング除去することにより、
表面電極５を形成する。この際に、エツチング液の作用
で、半導体基板１の裏面側に酸素などが付着する。Next, the upper part of the semiconductor film 2 is removed by etching using a photolithography technique using HNO3 solution, etc.
A surface electrode 5 is formed. At this time, oxygen and the like adhere to the back side of the semiconductor substrate 1 due to the action of the etching solution.
次に、次工程で使用するＨＦ溶液から表面電極５を保護
するために、半導体基板１の表面側全面に樹脂（レジス
ト膜）などから成るコート層を形成する。Next, in order to protect the surface electrode 5 from the HF solution used in the next step, a coating layer made of resin (resist film) or the like is formed over the entire surface side of the semiconductor substrate 1.
次に、次工程で形成する裏面電極４とオーミックコンタ
クトを取るために、半導体基板ｌの裏面側に吸着した酸
素をＨＦ溶液などで除去する。Next, in order to establish ohmic contact with the back electrode 4 to be formed in the next step, oxygen adsorbed on the back side of the semiconductor substrate 1 is removed using an HF solution or the like.
次に、Ａ１膜などから成る裏面電極４を形成する。Next, a back electrode 4 made of an A1 film or the like is formed.
最後に、表面側に形成していた樹脂などから成るコート
層を剥離液で除去して完成する。Finally, the coating layer made of resin or the like formed on the surface side is removed with a stripping solution to complete the process.
（発明が解決しようとする問題点）
ところか、この従来の半導体素子の形成方法では、半導
体基板ｌの表面側にＡｇまたはＡｇ／Ｚｎ膜などから成
る表面金属層を形成した後にＨＮＯ３溶液などを使用し
て表面電極５を形成することから、このＨＮＯ，溶液で
半導体基板１の裏面側に酸素か付着し半導体基板１と裏
面電極４とのオーミックコンタクトが取れなくなる。そ
のため、半導体基板ｌの裏面側にＡＩなどから成る裏面
電極４を蒸着する前に、半導体基板ｌの裏面側に付着し
た酸素をＨＦ／ＮＨ，Ｆ溶液などで除去しておかなけれ
ばならないという問題があった。(Problems to be Solved by the Invention) However, in this conventional method for forming a semiconductor element, after forming a surface metal layer made of Ag or Ag/Zn film on the surface side of the semiconductor substrate l, a HNO3 solution or the like is applied. Since the surface electrode 5 is formed using the HNO solution, oxygen adheres to the back surface side of the semiconductor substrate 1 due to this HNO solution, making it impossible to establish ohmic contact between the semiconductor substrate 1 and the back surface electrode 4. Therefore, before depositing the back electrode 4 made of AI or the like on the back side of the semiconductor substrate l, there is a problem that oxygen adhering to the back side of the semiconductor substrate l must be removed using an HF/NH, F solution, etc. was there.
また、裏面電極４を形成する前に、半導体基板１の裏面
側に付着した酸素などをＨＦ／ＮＨ，Ｆ溶液などで除去
するが、今度はこのエツチング液で表面電極５およびパ
シベーション膜３が犯されるのを防ぐために、半導体基
板１の表面側を樹脂などでコートして保護しなけれなら
ず、このコート層の形成と除去か必要であるという問題
もあった。In addition, before forming the back electrode 4, oxygen adhering to the back side of the semiconductor substrate 1 is removed using a HF/NH, F solution, etc., but this time, the front electrode 5 and the passivation film 3 are not damaged by this etching solution. In order to prevent this from occurring, the front surface of the semiconductor substrate 1 must be protected by coating with a resin or the like, and there is also the problem that it is necessary to form and remove this coating layer.
本発明は、このような問題点に鑑みて案出されたもので
あり、工程を簡略化した半導体素子の製造方法を提供す
ることを目的とするものである。The present invention has been devised in view of such problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device with simplified steps.
（問題点を解決するための手段）
本発明によれば、半導体基板上に、外周部にパッシベー
ション膜が被着された半導体膜を形成して、この半導体
膜上に表面電極を形成するとともに、上記半導体基板の
裏面側に裏面電極と保護金属層を形成して成る半導体素
子、および半導体基板上に形成された半導体膜の外周部
にパッシベーション膜を形成して、この半導体基板の表
面側に裏面電極と保護金属層を形成するとともに、上記
半導体基板の表面側に表面金属層を形成し、表面金属層
の半導体膜上を除いてエツチング除去することにより表
面電極を形成する半導体素子の形成方法か提供され、そ
のことにより上記目的か達成される。(Means for Solving the Problems) According to the present invention, a semiconductor film having a passivation film attached to the outer periphery is formed on a semiconductor substrate, a surface electrode is formed on this semiconductor film, and a surface electrode is formed on the semiconductor film. A semiconductor element is formed by forming a back electrode and a protective metal layer on the back side of the semiconductor substrate, and a passivation film is formed on the outer periphery of the semiconductor film formed on the semiconductor substrate, and the back side is formed on the front side of the semiconductor substrate. A method for forming a semiconductor element, in which a surface metal layer is formed on the surface side of the semiconductor substrate, and a surface electrode is formed by forming an electrode and a protective metal layer, and etching away the surface metal layer except on the semiconductor film. provided, thereby achieving the above objectives.
（実施例） 以下、本発明を添付図面に基づき詳細に説明する。(Example) Hereinafter, the present invention will be explained in detail based on the accompanying drawings.
なお、半導体素子の構成は、従来例と路間−であるので
説明を省略する。Note that the configuration of the semiconductor element is different from that of the conventional example, so the explanation will be omitted.
第１図は、本発明に係る半導体素子の形成方法を説明す
るための工程図である。FIG. 1 is a process diagram for explaining a method for forming a semiconductor element according to the present invention.
まず、半導体膜２か被着形成された半導体基板１の表面
側に窒化シリコン（３２３Ｎ４ ）や酸化シリコン（Ｓ
ｉｎ２）などから成るパッシベーション膜３をプラズマ
ＣＶＤ法などて厚み１０００〜３０００Ａ程度に形成す
る。このパッシベーション膜３として窒化シリコン膜を
プラズマＣＶＤ法で形成する場合は、基板温度を１５０
〜４００℃にして、シランガスとアンモニアガスを１３
６：２４４の流量比に設定して、放電用電源の周波数を
１３ 、 ５６ ＭＨｚにして形成する。また、パッシ
ベーション膜３として酸化シリコン膜をプラズマＣＶＤ
法で形成する場合は、基板温度を１５０〜４００°Ｃに
して、シランガスと笑気ガスを１３６：２４４あるいは
３７：３５５の流量比に設定して形成する。First, silicon nitride (323N4) or silicon oxide (S
A passivation film 3 made of in2) or the like is formed to a thickness of about 1000 to 3000 Å by plasma CVD or the like. When forming a silicon nitride film as this passivation film 3 by the plasma CVD method, the substrate temperature is set to 150°C.
At ~400℃, add silane gas and ammonia gas to 13
The flow rate ratio is set to 6:244, and the frequency of the discharge power source is set to 13.56 MHz. In addition, a silicon oxide film was deposited as the passivation film 3 by plasma CVD.
When forming by the method, the substrate temperature is set to 150 to 400° C., and the flow rate ratio of silane gas and laughing gas is set to 136:244 or 37:355.
次に、パッシベーション膜３の最上部分を残してエツチ
ング除去する。このエツチングは、ＨＦ／ＮＨ４Ｆ溶液
などで行う。半導体基板１の裏面側に酸素などが吸着し
ていれば、このパッシベーション膜３の一部をエツチン
グ除去する際に除去される。Next, the passivation film 3 is etched away leaving only the uppermost portion. This etching is performed using a HF/NH4F solution or the like. If oxygen or the like is adsorbed on the back side of the semiconductor substrate 1, it will be removed when part of the passivation film 3 is etched away.
次に、半導体基板Ｉの裏面側に、裏面電極４を形成する
。この裏面電極４は、Ａ】など半導体基板ｌの裏面領域
とオーミック性を示す金属で形成され、真空蒸着法など
て厚み３０００人程度ロス成される。Next, a back electrode 4 is formed on the back side of the semiconductor substrate I. The back electrode 4 is formed of a metal such as A which exhibits ohmic properties with the back surface region of the semiconductor substrate 1, and is formed to a thickness of about 3000 by vacuum evaporation.
次に、裏面電極４上にＡｕまたはｐｔなどから成る保護
金属層６を厚み１００〜１０００人程度に形成すロスこ
の保護金属層６は、例えば電子ビーム蒸着法などにより
形成される。上述のＡ１はＨＮＯ，に犯されるが、Ａｕ
やＰｔは犯されないため、後工程でＨＮＯ３を使用する
エツチング工程かあってもこの保護金属層６が保護層と
なって裏面電極４は保護される。Next, a protective metal layer 6 made of Au or PT is formed on the back electrode 4 to a thickness of approximately 100 to 1000 layers. This protective metal layer 6 is formed by, for example, electron beam evaporation. A1 mentioned above is raped by HNO, but Au
Since Pt and Pt are not damaged, the protective metal layer 6 serves as a protective layer and the back electrode 4 is protected even if there is an etching process using HNO3 in the subsequent process.
次に、半導体基板１上に、後に表面電極５となる表面金
属層を厚み３０００人程度ロス着形成する。この表面金
属層は、半導体膜２の最上層とオーミック性を示すＡｇ
またはＡ ｇ ／ Ｚ ｎなどから成り、蒸着法などで
形成される。Next, a surface metal layer, which will later become the surface electrode 5, is formed on the semiconductor substrate 1 by loss deposition to a thickness of about 3,000 layers. This surface metal layer is made of Ag that exhibits ohmic properties with the top layer of the semiconductor film 2.
Alternatively, it is made of Ag/Zn, etc., and is formed by a vapor deposition method or the like.
なお、裏面電極４および保護金属層６の形成工程と表面
金属層の形成工程は、順序を入れ替えてもよい。Note that the order of the steps of forming the back electrode 4 and the protective metal layer 6 and the step of forming the front metal layer may be reversed.
また、裏面電極４、保護金属層６、および表面金属層を
同一の装置で形成すると、製造作業を簡略化できる。す
なわち、裏面電極４、保護金属層６、および表面金属層
は、それぞれ同一の真空蒸着装置で形成できる。Furthermore, if the back electrode 4, the protective metal layer 6, and the front metal layer are formed using the same device, manufacturing operations can be simplified. That is, the back electrode 4, the protective metal layer 6, and the front metal layer can be formed using the same vacuum evaporation apparatus.
最後に、表面金属層の半導体膜２上を残してＨＮＯ１溶
液などでエツチング除去して、表面電極５を形成して半
導体素子か完成する。上述のように、裏面電極４上には
保護金属層６か被着形成されていることから、このエツ
チング工程で裏面電極４は犯されることはない。Finally, the surface metal layer on the semiconductor film 2 is removed by etching with HNO1 solution, etc., and the surface electrode 5 is formed to complete the semiconductor element. As mentioned above, since the protective metal layer 6 is formed on the back electrode 4, the back electrode 4 is not damaged in this etching process.
このように形成した半導体素子は、表面電極５と裏面電
極４間に電流を流して、半導体膜２部分て電子と正孔を
再結合させて発光させる発光ダイオードなどとして用い
られる。The semiconductor element formed in this manner is used as a light emitting diode or the like that causes a current to flow between the front electrode 5 and the back electrode 4 to recombine electrons and holes in the semiconductor film 2 to emit light.
第４図は、第２の実施例を示す断面図である。FIG. 4 is a sectional view showing the second embodiment.
第２の実施例では、ｐ−型ＧａＡｓ基板から成る半導体
基板１１上に、ｐ−ＡｌＧａＡｓ層１２ａＳｎ−ＡＩＧ
ａＡｓ層１２ｂ、およびｎ−ＧａＡｓ層１２ｃを順次エ
ピタキシャル成長させて半導体膜１２を形成して、半導
体膜１２の外周部にパシベーション膜１３を形成し、ｎ
−ＧａＡｓ層１２ｄおよびパシベーション膜１３上にｎ
−ＧａＡｓ層１２ｄとオーミッ性を示すＡｕ−Ｇｅから
成る表面金属層を真空蒸着法やスパッタリング法で形成
するとともに、半導体基板１１の裏面側に、ｐ−型Ｇａ
Ａｓ基板１１とオーミックコンタクトが得られるＡｇ−
Ｚｎから成る裏面電極１４、およびＡＩから成る保護金
属層１６を真空蒸着法やスパッタリング法で形成する。In the second embodiment, a p-AlGaAs layer 12aSn-AIG is formed on a semiconductor substrate 11 made of a p-type GaAs substrate.
A semiconductor film 12 is formed by sequentially epitaxially growing an aAs layer 12b and an n-GaAs layer 12c, and a passivation film 13 is formed on the outer periphery of the semiconductor film 12.
- n on the GaAs layer 12d and the passivation film 13;
- A surface metal layer consisting of the GaAs layer 12d and Au-Ge exhibiting ohmic properties is formed by vacuum evaporation or sputtering, and a p-type Ga layer is formed on the back side of the semiconductor substrate 11.
Ag- that allows ohmic contact with the As substrate 11
A back electrode 14 made of Zn and a protective metal layer 16 made of AI are formed by vacuum evaporation or sputtering.
この場合、表面金属層、裏面電極１４、および保護金属
層１６は、同一バッチで形成できる。その後、Ａｕ−Ｇ
ｅがら成る表面金属層をｎ−ＧａＡｓ層１２ｄ上を残し
てＫＩ／Ｉ２または王水でフォトエツチングして表面金
属１５を形成する。この場合、裏面電極１４の裏面側に
は、ＡＩから成る保護金属層１６か被着されていること
から、不動態を造り、Ａｇ−Ｚｎから成る裏面電極１４
か犯されることはない。In this case, the front metal layer, the back electrode 14, and the protective metal layer 16 can be formed in the same batch. After that, Au-G
A surface metal layer 15 is formed by photo-etching the surface metal layer consisting of e with KI/I2 or aqua regia, leaving only the n-GaAs layer 12d. In this case, since the protective metal layer 16 made of AI is deposited on the back side of the back electrode 14, a passivity is created and the back electrode 14 made of Ag-Zn is coated.
or not be violated.
（発明の効果）
以上のように、本発明に係る半導体素子およびその形成
方法によれば、半導体基板上に形成された半導体膜の外
周部にパッシベーション膜を形成して、半導体基板の裏
面側に裏面電極と保護金属層を形成するとともに、半導
体基板の表面側に表面金属層を形成し、表面金属層の半
導体膜上を除いてエツチング除去することして表面電極
を形成することから、半導体基板裏面側のエツチング工
程や表面側に樹脂コート層を形成する必要かなくなり、
工程が著しく簡略化される。(Effects of the Invention) As described above, according to the semiconductor element and the method for forming the same according to the present invention, a passivation film is formed on the outer periphery of a semiconductor film formed on a semiconductor substrate, and a passivation film is formed on the back side of the semiconductor substrate. In addition to forming a back electrode and a protective metal layer, a surface metal layer is formed on the front side of the semiconductor substrate, and the surface metal layer is etched away except for the semiconductor film to form a front electrode. There is no need for side etching process or formation of a resin coating layer on the surface side.
The process is significantly simplified.
第１図は本発明に係る半導体素子の形成方法を説明する
ための工程図、第２図は従来の半導体素子の形成方法を
説明するための工程図、第３図は半導体素子の断面図、
第４図は本発明の第２の実施例を示す断面図である。
１、１１
２、１２
３、１３
４、１４
５、１５
６、１６
二半導体基板
：半導体膜
：パッシベーション膜
二表面電極
二表面電極
：保護金属層FIG. 1 is a process diagram for explaining a method for forming a semiconductor element according to the present invention, FIG. 2 is a process diagram for explaining a conventional method for forming a semiconductor element, and FIG. 3 is a cross-sectional view of a semiconductor element.
FIG. 4 is a sectional view showing a second embodiment of the present invention. 1, 11 2, 12 3, 13 4, 14 5, 15 6, 16 Two semiconductor substrates: Semiconductor film: Passivation film Two surface electrodes Two surface electrodes: Protective metal layer
Claims (2)
被着された半導体膜を形成して、この半導体膜上に表面
電極を形成するとともに、上記半導体基板の裏面側に裏
面電極と保護金属層を形成して成る半導体素子。(1) A semiconductor film with a passivation film attached to the outer periphery is formed on a semiconductor substrate, a surface electrode is formed on this semiconductor film, and a back electrode and a protective metal layer are formed on the back side of the semiconductor substrate. A semiconductor element formed by forming.
ッシベーション膜を形成して、この半導体基板の裏面側
に裏面電極と保護金属層を形成するとともに、上記半導
体基板の表面側に表面金属層を形成し、表面金属層の半
導体膜上を除いてエッチング除去することにより表面電
極を形成する半導体素子の形成方法。(2) A passivation film is formed on the outer periphery of the semiconductor film formed on the semiconductor substrate, a back electrode and a protective metal layer are formed on the back side of the semiconductor substrate, and a surface metal layer is formed on the front side of the semiconductor substrate. A method of forming a semiconductor element in which a surface electrode is formed by forming a layer and etching away the surface metal layer except for the semiconductor film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2174061A JPH03284886A (en) | 1990-03-30 | 1990-06-29 | Semiconductor element and forming method therefor |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8598290 | 1990-03-30 | ||
| JP2-85982 | 1990-03-30 | ||
| JP2174061A JPH03284886A (en) | 1990-03-30 | 1990-06-29 | Semiconductor element and forming method therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03284886A true JPH03284886A (en) | 1991-12-16 |
Family
ID=26426996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2174061A Pending JPH03284886A (en) | 1990-03-30 | 1990-06-29 | Semiconductor element and forming method therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03284886A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003163375A (en) * | 2001-11-29 | 2003-06-06 | Sanyo Electric Co Ltd | Nitride semiconductor element and its manufacturing method |
| JP2010114411A (en) * | 2008-11-06 | 2010-05-20 | Samsung Electro-Mechanics Co Ltd | Compound semiconductor light emitting element, and method for manufacturing the same |
| JP2010147463A (en) * | 2008-12-17 | 2010-07-01 | Seoul Semiconductor Co Ltd | Light-emitting diode having plurality of luminescence cells, and method of manufacturing the same |
| US8188496B2 (en) | 2008-11-06 | 2012-05-29 | Samsung Led Co., Ltd. | Semiconductor light emitting device including substrate having protection layers and method for manufacturing the same |
-
1990
- 1990-06-29 JP JP2174061A patent/JPH03284886A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003163375A (en) * | 2001-11-29 | 2003-06-06 | Sanyo Electric Co Ltd | Nitride semiconductor element and its manufacturing method |
| JP2010114411A (en) * | 2008-11-06 | 2010-05-20 | Samsung Electro-Mechanics Co Ltd | Compound semiconductor light emitting element, and method for manufacturing the same |
| US8188496B2 (en) | 2008-11-06 | 2012-05-29 | Samsung Led Co., Ltd. | Semiconductor light emitting device including substrate having protection layers and method for manufacturing the same |
| US8916402B2 (en) | 2008-11-06 | 2014-12-23 | Samsung Electronics Co., Ltd. | Semiconductor light emitting device including substrate having protection layers providing protection against chemicals and method for manufacturing the same |
| JP2010147463A (en) * | 2008-12-17 | 2010-07-01 | Seoul Semiconductor Co Ltd | Light-emitting diode having plurality of luminescence cells, and method of manufacturing the same |
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