JP3515851B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device such as a GaN-based light emitting device,
In particular, the present invention relates to a manufacturing method having an etching step of simultaneously etching a plurality of types of semiconductor layers.

[0002]

2. Description of the Related Art A conventional example of a method for manufacturing a semiconductor device will be described by taking a GaN-based light emitting element used for an indicator lamp, a full color type display or the like as an example.

FIG. 10 is a sectional view schematically showing one structural example of such a light emitting element.

As shown in the figure, the sapphire substrate 10
On 01, an n-type GaN layer 1003 is formed via an Al _x Ga _1-x N buffer layer 1002 (here, x = 0 and hereinafter referred to as “GaN layer”). A step difference of, for example, about 0.2 μm is formed on the surface of the n-type GaN layer 1003. The n-type Al _y Ga _1-y N cladding layer 1004 (0 ≦ y ≦
1), but Al / Ti layers 1008 are formed on the lower side. Further, the In _z Ga _1-z N active layer 10 is formed on the surface of the n-type Al _y Ga _1-y N cladding layer 1004.
05 (0 ≦ z ≦ 1), a p-type Al _y Ga _1-y N cladding layer 1006 and a p-type GaN layer 1007 are sequentially stacked,
A as a positive electrode is formed on the surface of the p-type GaN layer 1007.
The u / Ni layer 1009 is formed.

According to such a structure, the Au / Ni layer 1
009 is used as a positive electrode and the Al / Ti layer 1008 is used as a negative electrode.
By passing a current of about A, it is possible to emit light of a predetermined wavelength from the In _z Ga _1-z N active layer.

Next, a conventional example of a method for manufacturing the semiconductor light emitting device shown in FIG. 10 will be described with reference to FIGS.

First, for example, MOCVD (Metalorganic Chemical Vaper Deposit) is formed on the sapphire substrate 1001.
GaN layer 1101, n-type Ga
N layer 1102, n-type Al _y Ga _1-y N layer 1103, In
_z Ga _1-z N layer 1104, p-type Al _y Ga _1-y N layer 11
05 and p-type GaN layer 1106 are sequentially stacked (see FIG. 1).
1).

Next, on the surface of the p-type GaN layer 1106,
For example, a SiO ₂ film having a film thickness of, for example, 0.2 to 1 μm is formed by PCVD (Plasma Chemical Vaper Deposition) or the like, and a SiO ₂ film pattern 1107 is further formed by using a normal photolithography technique (FIG. 12). reference).

Then, by using the pattern 1107 as a mask, the layers 1101 to 1106 are etched to perform element isolation (see FIG. 13). As the etching method at this time, for example, wet etching using phosphoric acid at 200 ° C. can be used.

Then, a normal resist film is formed on the SiO ₂ film.
It is formed on the surface of the film 1107 and the side surfaces of the layers 1101 to 1106. Then, a resist pattern 1108 is formed by removing a part of the resist film on the surface of the SiO ₂ film 1107 by using a normal photolithography technique (see FIG. 14).

Thereafter, this resist pattern 1108
Using the as a mask, the n-type GaN layer 1102, each of the layers 1103 to 1106 and the SiO ₂ film 1107 thereon are etched. At this time, the n-type GaN layer 1102 is etched only in a region of about 0.2 μm from the surface (see FIG. 15). Then, the SiO ₂ film 1107
By removing the resist film 1108 and Ga
N buffer layer 1002, n-type GaN layer 1003, n-type A
l _y Ga _1-y N cladding layer 1004, In _z Ga _1-z N
Active layer 1005, p-type Al _y Ga _1-y N cladding layer 10
A laminated structure composed of 06 and the p-type GaN layer 1007 can be obtained (see FIG. 16).

Finally, Al / is formed on the exposed surface of the n-type GaN layer 1003 by using a normal deposition technique or patterning technique.
By forming the Ti layer 1008 and further forming the Au / Ni layer 1009 on the surface of the p-type GaN layer 1007 by the same technique, the light emitting device as shown in FIG. 10 can be obtained.

[0013]

As described above, the semiconductor light emitting device has a plurality of semiconductor layers 1002 to 1002 made of different materials.
It has a structure in which 1007 are laminated (see FIG. 10). Then, in the manufacturing process, it is necessary to simultaneously etch the stacked semiconductor layers 1101 to 1106 (the above process and reference). Here, these semiconductor layers have different etching rates. For example, in etching using phosphoric acid at 200 ° C. as described above, the etching rate of the In _z Ga _{1 -z} N layer 1104 is about 40 nm / min, while n
_-Type GaN layer 1102 and n-type Al _y Ga _1-y N layer 1103
Is about 30 nm, and the p-type Al _y Ga _1-y N layer 1105 and the p-type GaN layer 1106 are about 3 nm.

Therefore, the conventional manufacturing method has a drawback that it is extremely difficult to set etching conditions.

For example, if the layers 1103 to 1106 are to be etched (see the above steps and FIG. 15), if the etching proceeds too much, the active layer 1005 will be removed later.
Since the etching amount of the In _z Ga _1-z N layer 1104, which becomes the following, is too large, the volume of the active layer 1005 becomes small.
Luminous efficiency is reduced. Further, if the etching progresses too much in this way, the etching amount of the n-type GaN layer 1102 is too large, and the thickness of the layer at this portion becomes thin. Therefore, when the light emitting element is completed (see FIG. 10). ) To Al /
Ti layer 1008 and n-type Al _y Ga _1-y N cladding layer 10
The electric resistance with 04 becomes large.

On the other hand, when the etching amount is too small in the above step, the n-type Al _y Ga _1-y N layer 1103 is formed.
Of the n-type GaN layer 11 which will be the layer 1003 in a later step.
In some cases, the surface of No. 02 is not exposed. In this case,
The yield of the light emitting device is reduced.

As described above, in the conventional manufacturing method, the variation in the etching rate of each layer causes the deterioration of the characteristics of the device and the yield.

Note that such a problem is not limited to the case of the GaN-based light emitting element as shown in FIG. 10, but may occur in the laminated structure of other semiconductor devices.

The present invention has been made in view of the above-mentioned drawbacks of the prior art, and provides a method of manufacturing a semiconductor device capable of reducing the variation in the etching rate of each semiconductor layer constituting the laminated structure. The purpose is to

[0020]

A method of manufacturing a semiconductor device according to the present invention comprises a step of sequentially laminating a plurality of types of GaN-based semiconductor layers on an insulating substrate and an etching treatment for the plurality of types of semiconductor layers simultaneously. In the method for manufacturing a semiconductor device having an etching step, the etching step selectively introduces Ga ions into a partial region of the semiconductor layer by an ion implantation method until reaching a layer that is to be exposed by etching. The method is characterized by including a first step of implanting and a second step of removing a region into which an impurity has been introduced in the first step by etching.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, one embodiment of the present invention will be described by taking as an example the case of being applied to the manufacture of a GaN-based light emitting device having a double hetero structure shown in FIG.

1 to 9 are process cross-sectional views for explaining a method for manufacturing a GaN-based light emitting device according to this embodiment.

First, Al _x Ga _1-x N is formed on the sapphire substrate 1001 by using a technique such as MOCVD.
Layer 101 (0 ≦ x ≦ 1, here x = 0, and the following “G
referred to aN layer "), n-type GaN layer 102, n-type Al _y G
a _1-y N layer 103 (0 ≦ y ≦ 1) , In z Ga 1-z N layer 104 (0 ≦ z ≦ 1) , p -type Al _y Ga _1-y N layer 105
Then, the p-type GaN layer 106 is sequentially laminated (see FIG. 1).

In this step, if the MOCVD method is used, first, at a temperature of 500 to 600 ° C., for example, trimethylgallium (CH ₃ ) ₃ Ga gas and ammonia NH ₃ gas are used, and the film thickness is, for example, 0. 1 μm GaN
Form the layer 101. Next, for example, a temperature of 1000 to 11
At 00 ° C., using trimethylgallium (CH ₃ ) ₃ Ga gas and ammonia gas, a film having a thickness of 4 μm
The type GaN layer 102 is formed. Then, for example, a temperature of 100
0 to 1100, trimethylaluminum [(C
H _{3) 3} Al] _2, using trimethylgallium gas and ammonia gas to form the n-type Al _y Ga _1-y N layer 103 having a thickness of, for example, 0.15 [mu] m. Next, for example, at a temperature of 700 to 800 ° C., trimethylindium (C
H ₃ ) ₃ In gas, trimethylgallium gas, and ammonia gas are used to form In _z having a thickness of, for example, 0.1 μm.
The Ga _1-z N layer 104 is formed. Then, for example, a temperature of 10
At 00 to 1100 ° C., using trimethylaluminum gas, trimethylgallium gas and ammonia gas,
A p-type Al _y Ga _1-y N layer 1 having a thickness of 0.15 μm, for example
Form 05. Then, for example, at a temperature of 1100 ° C., using trimethylgallium gas and ammonia gas,
A p-type GaN layer 106 having a thickness of 0.3 μm, for example, is formed.

Next, on the surface of the p-type GaN layer 106, for example, by PCVD using silane SiH ₄ gas or the like,
A SiO ₂ film 107 having a film thickness of, for example, 1 to ₂ μm is formed,
Further, a resist film 108 is formed on the surface of the SiO ₂ film 107 by coating or the like (see FIG. 2).

Then, the SiO ₂ film 107 and the resist film 108 are formed by using an ordinary photolithography technique.
Is patterned (see FIG. 3).

Subsequently, Ga ions are implanted into the laminated portion composed of the semiconductor layers 101 to 106 by ion implantation using the resist film 108 as a mask (see FIG. 4, corresponding to the "first step" of the present invention). To). At this time, for example,
The acceleration voltage is 500 kV and the dose amount is 1 × 10 ¹⁵ .
This allows Ga ions to reach a depth of 0.1 μm from the surface of the sapphire substrate. In FIG. 4, the ion implantation region 110 is shown by hatching.

After the ion implantation is completed, the resist film 108 is removed.

Next, etching is performed using the pattern of the SiO ₂ film 107 as a mask, whereby the semiconductor layer 10 is formed.
Of the regions 1 to 106, the region where Ga ions are implanted in the above process is removed (see FIG. 5, corresponding to the “second process” of the present invention). At this time, the sapphire substrate 1001 is hardly etched.

As an etching method at this time, for example, wet etching using phosphoric acid at 200 ° C. can be used. The etching rate in this case is substantially the same for each of the semiconductor layers 101 to 106, and is about 60 n.
It was m / min.

Subsequently, a resist film 109 is formed on the SiO ₂ film.
It is formed on a part of the surface of the film 107 and the side surface of each of the layers 101 to 106. Then, using this resist film 109 as a mask, etching is performed using, for example, hydrofluoric acid,
The exposed surface of the SiO ₂ film 107 is removed, and the p-type GaN layer 10 is removed.
The surface of 6 is exposed (see FIG. 6).

After that, Ga ions are implanted near the surfaces of the semiconductor layers 103 to 106 and the N-type GaN layer 102 by ion implantation using the SiO ₂ film 107 and the resist film 109 as a mask (see FIG. 7, the present invention. "First
Process)). At this time, for example, the acceleration voltage is 400 kV and the dose amount is 1 × 10 ¹⁶ . As a result, Ga ions are removed from the surface of the N-type GaN layer 102 by 0.2
It is possible to reach a depth of μm. In FIG. 7, the ion implantation 111 is shown by hatching. Here, since the accuracy of the arrival depth by ion implantation is about ± 0.1 μm, the arrival depth of Ga ions can be controlled with sufficient accuracy.

Next, etching is performed using the patterns of the SiO ₂ film 107 and the resist film 109 as a mask.
This makes it possible to remove the region of the semiconductor layers 102 to 106 into which Ga ions have been implanted in the above steps (see FIG. 8, which corresponds to the “second step” of the present invention).

As the etching method at this time, for example, wet etching using phosphoric acid at 200 ° C. can be used. The etching rate in this case is substantially the same for each of the semiconductor layers 102 to 106, and is about 60 n.
It was m / min.

Further, as described above, when the ion implantation method is used, the accuracy of the reaching depth is very excellent, so N
The surface of the n-type GaN layer 102 can be reliably obtained, and n
Inconvenience hardly occurs such etching region type Al _y Ga _1-y N layer 102 is in the fully may remain without being etched.

Then, the GaN buffer layer 10 is removed by removing the SiO ₂ film 107 and the resist film 109.
02, n-type GaN layer 1003, n-type Al _y Ga _1-y N clad layer 1004, In _z Ga _1-z N active layer 1005,
p-type Al _y Ga _1-y N cladding layer 1006 and p-type G
A laminated structure including the aN layer 1007 can be obtained (see FIG. 9).

Finally, Al / is formed on the exposed surface of the n-type GaN layer 1003 by using a normal deposition technique or patterning technique.
By forming the Ti layer 1008 and further forming the Au / Ni layer 1009 on the surface of the p-type GaN layer 1007 by the same technique, the light emitting device as shown in FIG. 10 can be obtained.

As described above, according to the manufacturing method of this embodiment, Ga ions are preliminarily implanted into each of the semiconductor layers 101 to 106 (the above steps and) so that the etching rates of these semiconductor layers 101 to 106 are uniform. Therefore, the etching conditions can be easily set. Therefore, as in the conventional case, the etching progresses too much to lower the light emission efficiency or increase the electric resistance, and conversely, due to lack of etching, the n-type Al _y Ga _1-y N layer is formed. It is possible to avoid the disadvantage that the etching region of 102 is not completely etched and remains.

Particularly, by using the ion implantation method,
Since the accuracy of the reaching depth can be made very high, these effects become remarkable.

Furthermore, GaN-based semiconductor layers 101 to 10
Since Ga ions are introduced into 6,
Even if the ionic species remain in the completed light emitting element, there is no possibility of adverse effects. However, it is needless to say that the effect of the present invention can be obtained by using other ionic species.

In the present embodiment, the case where the present invention is applied to a GaN-based light emitting element has been described. However, as long as it has a step of simultaneously etching a plurality of types of semiconductor layers, for example, another Ga compound-based material is used. Of course, it can be applied to other semiconductor laminated structures such as semiconductor devices and silicon semiconductor devices.

The method for forming the mask pattern, the etching method, etc. are not limited.

[0043]

As described in detail above, according to the present invention, it is possible to provide a method for manufacturing a semiconductor device capable of reducing variations in etching rate of each semiconductor layer constituting a laminated structure.

[Brief description of drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 10 is a sectional view schematically showing a structural example of a semiconductor device.

FIG. 11 is a process sectional view for explaining the conventional method for manufacturing a semiconductor device.

FIG. 12 is a process cross-sectional view for explaining the conventional method for manufacturing a semiconductor device.

FIG. 13 is a process cross-sectional view for explaining the conventional method for manufacturing a semiconductor device.

FIG. 14 is a process cross-sectional view for explaining the conventional method for manufacturing a semiconductor device.

FIG. 15 is a process cross-sectional view for explaining the conventional method for manufacturing a semiconductor device.

FIG. 16 is a process cross-sectional view for explaining the conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

101 GaN layer 102 n-type GaN layer 103 n-type Al _y Ga _1-y N layer 104 In _z Ga _1-z N layer 105 p-type Al _y Ga _1-y N layer 106 p-type GaN layer 107 SiO ₂ film 108, 109 resist film 1001 sapphire substrate 1002 GaN buffer layer 1003 n-type GaN layer 1004 n-type Al _y Ga _1-y N cladding layer 1005 In _z Ga _1-z N active layer 1006 p-type Al _y Ga _1-y N cladding layer 1007 p-type GaN layer 1008 Al / Ti layer 1009 Au / Ni layer

Claims (2)

(57) [Claims] 1. A method of manufacturing a semiconductor device, comprising: a step of sequentially laminating a plurality of types of GaN-based semiconductor layers on an insulating substrate; and an etching step of simultaneously performing an etching process on the plurality of types of semiconductor layers. Is a first step of selectively implanting Ga ions by an ion implantation method into a region of the semiconductor layer until reaching a layer that is to be exposed by etching.
A second step of removing a region into which impurities have been introduced in the step of by etching, and a method of manufacturing a semiconductor device. 2. The substrate is a sapphire substrate, the semiconductor layers of the plurality of types are Al _x Ga _{1 -x} N buffer layers, and
Conductivity type GaN layer, first conductivity type Al _y Ga _1-y N clad layer, In _z Ga _1-z N active layer, second conductivity type Al _y Ga
_1-y N cladding layer and second conductivity type GaN layer (0 ≦ x ≦
1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1), The method for manufacturing a semiconductor device according to claim 1, wherein