KR20100076083A - Light emitting diode having plurality of light emitting cells and method of fabricating the same - Google Patents

Light emitting diode having plurality of light emitting cells and method of fabricating the same Download PDF

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Publication number
KR20100076083A
KR20100076083A KR20080128522A KR20080128522A KR20100076083A KR 20100076083 A KR20100076083 A KR 20100076083A KR 20080128522 A KR20080128522 A KR 20080128522A KR 20080128522 A KR20080128522 A KR 20080128522A KR 20100076083 A KR20100076083 A KR 20100076083A
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South Korea
Prior art keywords
insulating layer
layer
light emitting
formed
emitting diode
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KR20080128522A
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Korean (ko)
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갈대성
김대원
서원철
예경희
이주웅
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서울반도체 주식회사
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Publication of KR20100076083A publication Critical patent/KR20100076083A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50Wavelength conversion elements
    • H01L33/507Wavelength conversion elements the elements being in intimate contact with parts other than the semiconductor body or integrated with parts other than the semiconductor body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

PURPOSE: A light emitting diode having a plurality of light emitting cells and a method for fabricating the same are provided to secure strong junction between first and second insulation layers by forming the second insulation layer with the same material as the first insulation layer and greater thickness than the first insulation layer. CONSTITUTION: A plurality of light emitting cells(56) are located on a single board(51) and separated from each other. A first insulation layer(63) comprises an opening. Wirings(65) are formed on the first insulation layer. A second insulation layer(67) covers the first insulation layer and the wirings. The first insulation layer and the second insulation layer are formed of the same material. The first insulation layer is formed relatively thicker than the second insulation layer.

Description

LIGHT EMITTING DIODE HAVING PLURALITY OF LIGHT EMITTING CELLS AND METHOD OF FABRICATING THE SAME

The present invention relates to a light emitting diode and a method of manufacturing the same, and more particularly to a light emitting diode having a plurality of light emitting cells and wirings connecting the light emitting cells and having an insulating layer for protecting the light emitting cells and the wirings and the same. It relates to a manufacturing method.

Since the development of GaN-based light emitting diodes emitting blue light, various efforts have been made to improve the light emitting efficiency of light emitting diodes, and many structural improvements have been made for various applications. Blue or ultraviolet gallium nitride-based light-emitting diodes are currently used in a variety of applications, such as color LED display device, LED traffic signal, white LED, and is expected to replace the white fluorescent lamp in the general lighting field.

Such light emitting diodes generally emit light by a forward current and require the supply of a direct current. In consideration of the characteristics of the light emitting diode operating under the forward current, a technique of connecting a plurality of light emitting cells in parallel or in parallel or operating a plurality of light emitting cells under an AC power supply using a bridge rectifier has been tried and commercialized. to be. In addition, a light emitting diode capable of outputting high power and high efficiency light under a high voltage DC power supply by forming a plurality of light emitting cells on a single substrate and connecting them in series and in parallel has been developed. Such light emitting diodes may emit light of high power and high efficiency under an AC or DC power supply by forming a plurality of light emitting cells on a single substrate and connecting the light emitting cells through wires.

A light emitting diode that can be connected to a high voltage alternating current or direct current power source using a plurality of light emitting cells is described, for example, in " Light-EMITTING DEVICE HAVING " in WO 2004/023568 (Al). LIGHT-EMITTING ELEMENTS, which was disclosed by SAKAI et. Al.

The light emitting cells are electrically connected to each other by air bridge wirings, and a light emitting diode that can be driven under an AC or DC power supply through the connection of these wirings is provided.

However, the connection of the light emitting cells using the air bridge wiring is likely to cause a problem such as disconnection of the wiring or increase in wiring resistance due to the reliability of the wiring, that is, moisture or external impact from the outside. In order to protect this disadvantage, a wiring forming technique using a step cover process is used. The step cover process is a technique of forming an insulating layer covering the light emitting cells and forming wirings on the insulating layer, which is structurally stable compared to the air bridge because the wirings are laid on the insulating layer.

However, as the wiring using the step cover process is also exposed to the outside, the wiring may be disconnected due to moisture or external impact. In the case of a light emitting diode using a plurality of light emitting cells, many wires are used, and even if any one of the wires is disconnected, the entire light emitting diode cannot be operated. In addition, as a large number of wires are used, moisture from the outside is likely to penetrate into the light emitting cells, thereby lowering the luminous efficiency of the light emitting cells.

On the other hand, when the light emitting diode is used in practical applications such as general lighting, it is necessary to implement a light of various colors such as white light by converting ultraviolet light or blue light into a long wavelength light using a fluorescent material. Conventionally, such a fluorescent material has been applied to an epoxy resin or the like covering a light emitting diode chip that emits monochromatic light at the package level. In the white light emitting device, a color conversion material layer containing a fluorescent material is formed in the packaging process separately from the manufacturing process of the light emitting diode chip, which complicates the packaging process of the light emitting diode and causes a high defect rate of the packaging process. The failure of the packaging process results in a significant cost loss compared to the failure of the LED chip manufacturing process.

SUMMARY OF THE INVENTION An object of the present invention is to provide a light emitting diode and a method of manufacturing the same, which can prevent wire breakage, increased wiring resistance, or reduced performance of light emitting cells due to moisture penetration or external impact from the outside.

Another technical problem to be solved by the present invention is to form an insulating layer for protecting the wirings and the light emitting cells, a light emitting diode capable of enhancing the adhesion between the insulating layer and the base layer on which it is formed and a method of manufacturing the same. To provide.

Another object of the present invention is to provide a light emitting diode having a fluorescent material for converting a wavelength of light emitted from a light emitting cell at a chip level, and a method of manufacturing the same.

In order to solve the above technical problems, the light emitting diodes according to an aspect of the present invention, are spaced apart from each other on a single substrate, each of the lower semiconductor layer, the upper semiconductor layer and the lower semiconductor layer located on one region of the lower semiconductor layer A plurality of light emitting cells including an active layer interposed between a semiconductor layer and the upper semiconductor layer; A first insulating layer covering an entire surface of the light emitting cells, the first insulating layer having openings formed in the other regions of the lower semiconductor layers and the upper semiconductor layers, respectively; Wires formed on the first insulating layer and electrically connecting adjacent light emitting cells through the openings; And a second insulating layer covering the first insulating layer and the wirings. In addition, the first insulating layer and the second insulating layer are formed of the same material, the first insulating layer is relatively thicker than the second insulating layer.

Since the second insulating layer covers the wires and the light emitting cells, the wires and the light emitting cells can be protected from moisture penetration or external impact from the outside. Furthermore, by forming the first insulating layer and the second insulating layer with the same material, it is possible to improve the adhesion between the first insulating layer and the second insulating layer, thereby preventing the second insulating layer from being peeled off. In addition, it is possible to further prevent the second insulating layer from being peeled off by making the first insulating layer relatively thicker than the second insulating layer.

The first insulating layer may have a thickness within the range of 4500 kPa to 1 μm, and the second insulating layer may have a thickness greater than 500 kPa. When the first insulating layer is 4500 Å or less, an electrical short may easily occur between the wirings and the light emitting cells. On the other hand, the thicker the first insulating layer can prevent the short circuit between the wirings and the light emitting cells, but if the thickness is excessively thick, the light transmittance is lowered and the light emitting efficiency is reduced. Therefore, it is preferable that the 2nd insulating layer is formed in the thickness of 1 micrometer or less. On the other hand, when the second insulating layer is thinner than 500 mW, it is difficult to prevent moisture penetration from outside and protect the light emitting cells.

Here, the thickness of the said 1st insulating layer and a 2nd insulating layer means the thickness at the time of being formed on a flat board | substrate unless it limits in particular. In general, the thickness of the first insulating layer or the second insulating layer formed on the actual light emitting diode is relatively thinner than the thickness.

The first insulating layer and the second insulating layer may be a silicon oxide film or a silicon nitride film formed by plasma enhanced chemical vapor deposition. The silicon oxide film or silicon nitride film may be deposited at a temperature of 200 ~ 300 ℃.

In particular, the second insulating layer is preferably a layer deposited at a temperature in the range of -20% to + 20% of the deposition temperature of the first insulating layer. In the case of plasma enhanced chemical vapor deposition, the film quality can vary considerably depending on the deposition temperature. Therefore, the adhesive force between the second insulating layer and the first insulating layer can be improved by adopting the first insulating layer and the second insulating layer formed at almost similar temperatures.

The wirings may have a multilayer structure having a lower layer in contact with the first insulating layer and an upper layer in contact with the second insulating layer. The lower layer may be a Cr layer or a Ti layer, and the upper layer may be a Cr layer or a Ti layer. In particular, when the first insulating layer is an oxide film or a nitride film, the Cr layer or the Ti layer may be strongly adhered to the first insulating layer. Moreover, the adhesive force can be further enhanced by heat-treating the Cr layer or the Ti layer. In addition, an Au layer, Au / Ni layer, or Au / Al layer may be interposed between the lower layer and the upper layer.

The first insulating layer and the second insulating layer may be a polymer, for example, spin-on-glass (SOG) or benzocyclobutene (BCB). Since these films are formed using spin coating, the forming process is very simple. In addition, the second insulating layer may contain a phosphor in at least a portion of the region. Accordingly, white light or other various colors may be implemented at the chip level.

Alternatively, the phosphor layer may be located on the second insulating layer. Such a phosphor layer may be coated by, for example, incorporating a phosphor into a resin or coated using electrophoresis.

Meanwhile, transparent electrode layers may be interposed between the first insulating layer and the upper semiconductor layers. The transparent electrode layer may be ITO, or may be a transparent metal. In the case of the metal transparent electrode layer, the transparent electrode layers may include at least one metal selected from the group consisting of Au, Ni, Pt, Al, Cr, and Ti.

The wires may be connected to the transparent electrode layers to be electrically connected to the upper semiconductor layers. In addition, the transparent electrode layers may have openings exposing the upper semiconductor layers, and the wirings may fill the openings of the transparent electrode layers.

In order to solve the above technical problem, the LED manufacturing method according to another aspect of the present invention, forming a plurality of light emitting cells spaced apart from each other on a single substrate, each of the light emitting cells of the lower semiconductor layer, the lower semiconductor layer An upper semiconductor layer positioned over an area, and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer; Forming a first insulating layer covering the plurality of light emitting cells, the first insulating layer having other regions of the lower semiconductor layers and openings formed on the upper semiconductor layers; Forming interconnections on the first insulating layer to electrically connect the light emitting cells through the openings; Forming a second insulating layer covering the first insulating layer and the wirings. In addition, the first insulating layer and the second insulating layer are formed of the same material, the first insulating layer is relatively thicker than the second insulating layer.

Accordingly, the wirings and the light emitting cells can be protected from moisture or external impact, and the adhesion between the first insulating layer and the second insulating layer can be enhanced.

On the other hand, the first insulating layer may have a thickness in the range of 4500 ~ 1㎛, the second insulating layer may be formed to have a thickness of more than 500Å. Further, the first insulating layer and the second insulating layer may be a silicon oxide film or a silicon nitride film formed by plasma enhanced chemical vapor deposition. The first insulating layer and the second insulating layer may be deposited at a temperature of 200 ~ 300 ℃. In addition, the second insulating layer may be deposited at a temperature in the range of -20% to + 20% of the deposition temperature of the first insulating layer.

The wirings may include a lower layer in contact with the first insulating layer and an upper layer in contact with the second insulating layer, wherein the lower layer may be a Cr layer or a Ti layer, and the upper layer may be a Cr layer or a Ti layer. In addition, before forming the second insulating layer, the wirings may be heat treated to improve the interface bonding property between the wirings and the first insulating layer. In this case, the wires may be heat treated in a temperature range of 300 ~ 500 ℃.

In some embodiments of the present invention, the first insulating layer and the second insulating layer may be formed of a polymer. Furthermore, the second insulating layer may contain a phosphor.

In other embodiments of the present invention, a phosphor layer may be formed on the second insulating layer. The phosphor layer may be formed by dispersing the phosphor in a resin and coated on the second insulating layer, or may be formed using an electrophoresis method.

The forming of the plurality of light emitting cells may further include forming a transparent electrode layer on the upper semiconductor layer. The transparent electrode layer may be heat-treated at a temperature of 500 ~ 800 ℃. In addition, the transparent electrode layer may be formed to have an opening exposing the upper semiconductor layer, and the opening may be filled by the wirings.

According to the present invention, the first insulating layer and the second insulating layer are formed of the same material, and the first insulating layer is formed relatively thicker than the second insulating layer, thereby improving adhesion between the first insulating layer and the second insulating layer. It can be strengthened and the peeling of the second insulating layer can be prevented. In addition, since the second insulating layer covers the wires and the light emitting cells, it is possible to prevent moisture from penetrating into the light emitting diode from the outside and protect the wires and the light emitting cells from external impact.

Furthermore, since the Cr layer or the Ti layer having strong adhesion to the insulating layer is used as the lower layer and the upper layer of the wiring, the adhesive force between the wiring and the insulating layer is also strengthened, whereby peeling of the second insulating layer can be further prevented.

In addition, by including a phosphor in the second insulating layer, or by forming a phosphor layer on the second insulating layer it is possible to implement a light of various colors such as white light at the chip level, it is possible to simplify the packaging process.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to ensure that the spirit of the present invention can be fully conveyed to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. And, in the drawings, the width, length, thickness, etc. of the components may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 1, the light emitting diode includes a substrate 51, a plurality of light emitting cells 56, a first insulating layer 63, wires 65, and a second insulating layer 67, and a buffer layer. 53, the transparent electrode layer 61, and the phosphor layer 69 may be included. The substrate 51 may be an insulating substrate, for example, a sapphire substrate.

The plurality of light emitting cells 56 are spaced apart from each other on the single substrate 51. Each of the light emitting cells 56 includes a lower semiconductor layer 55, an upper semiconductor layer 59 positioned on one region of the lower semiconductor layer, and an active layer 57 interposed between the lower semiconductor layer and the upper semiconductor layer. It includes. The lower and upper semiconductor layers are n-type and p-type, or p-type and n-type, respectively.

The lower semiconductor layer 55, the active layer 57, and the upper semiconductor layer 59 may be formed of a gallium nitride-based semiconductor material, that is, (Al, In, Ga) N. The active layer 57 has a composition element and composition ratio determined so as to emit light having a desired wavelength such as ultraviolet light or blue light, and the lower semiconductor layer 55 and the upper semiconductor layer 59 have a bandgap compared to the active layer 57. It is formed of large material.

The lower semiconductor layer 55 and / or the upper semiconductor layer 59 may be formed as a single layer, as shown, but may be formed in a multilayer structure. In addition, the active layer 57 may have a single quantum well or multiple quantum well structures.

Meanwhile, a buffer layer 53 may be interposed between the light emitting cells 56 and the substrate 51. The buffer layer 53 may be adopted to mitigate lattice mismatch between the substrate 51 and the lower semiconductor layer 55 to be formed thereon.

The first insulating layer 63 covers the entire surface of the light emitting cells 56. The first insulating layer 63 has openings in other regions of the lower semiconductor layers 55, that is, in an area adjacent to the region where the upper semiconductor layer 59 is formed, and also on the upper semiconductor layers 59. With openings. The openings are spaced apart from each other, so that sidewalls of the light emitting cells 56 are covered by the first insulating layer 63. The first insulating layer 63 also covers the substrate 51 in the regions between the light emitting cells 56. The first insulating layer 63 may be formed of a silicon oxide film (SiO 2 ) or a silicon nitride film, and may be a layer formed in a temperature range of 200 ° C. to 300 ° C. using a plasma chemical vapor deposition method. In this case, the first insulating layer 63 is preferably formed to a thickness of 4500 ~ 1㎛. When formed to a thickness smaller than 4500Å, a first insulating layer having a relatively thin thickness is formed by the layer covering characteristic under the light emitting cells, and an electrical short circuit may occur between the wiring formed on the first insulating layer and the light emitting cells. Can be. On the other hand, the thicker the first insulating layer can prevent the electrical short, the lower the light transmittance to reduce the luminous efficiency, it is preferable not to exceed the thickness of 1㎛.

Meanwhile, the wirings 65 are formed on the first insulating layer 63. The wirings 65 are electrically connected to the lower semiconductor layers 55 and the upper semiconductor layers 59 through the openings. In addition, the wirings 65 may electrically connect the lower semiconductor layers 55 and the upper semiconductor layers 59 of adjacent light emitting cells 56 to form a series array of light emitting cells 56. . A plurality of such arrays may be formed, and the plurality of arrays may be connected in reverse parallel to each other and connected to an AC power supply. In addition, a bridge rectifier (not shown) connected to a series array of light emitting cells may be formed, and the light emitting cells may be driven under AC power by the bridge rectifier. The bridge rectifier may be formed by connecting light emitting cells having the same structure as the light emitting cells 56 using the wirings 65.

Alternatively, the wirings may connect the lower semiconductor layers 55 of adjacent light emitting cells to each other or the upper semiconductor layers 59 to each other. Accordingly, a plurality of light emitting cells 56 connected in series and in parallel may be provided.

The wirings 65 may be formed of a conductive material, for example, a doped semiconductor material or metal such as polycrystalline silicon. In particular, the interconnections 65 may be formed in a multi-layered structure, and may include, for example, a lower layer 65a of Cr or Ti and an upper layer 65c of Cr or Ti. In addition, an intermediate layer 65b of Au, Au / Ni, or Au / Al may be interposed between the lower layer 65a and the upper layer 65c.

Meanwhile, the transparent electrode layers 61 may be interposed between the upper semiconductor layers 59 and the insulating layer 63. The transparent electrode layers 61 are exposed by the openings formed on the upper semiconductor layers 59. The transparent electrode layers 65 transmit light generated in the active layer 57 and distribute and supply current to the upper semiconductor layers 59. The wires 65 may be in contact with the transparent electrode layers 65 exposed by the openings and may be electrically connected to the upper semiconductor layers 55. In addition, the transparent electrode layers 61 may have openings exposing the upper semiconductor layers 59, and the wirings 65 may fill openings in the transparent electrode layers.

The second insulating layer 67 covers the wires 65 and the first insulating layer 63. The second insulating layer 67 prevents the wires 65 from being contaminated by moisture or the like, and prevents the wires 65 and the light emitting cells 56 from being damaged by an external impact.

The second insulating layer 67 may be formed of the same material as the first insulating layer 63 and may be formed of a silicon oxide film (SiO 2 ) or a silicon nitride film. Like the first insulating layer, the second insulating layer 67 may be a layer formed in a temperature range of 200 to 300 ° C. using a plasma chemical vapor deposition method. Further, when the first insulating layer 63 is a layer formed by using the PLAMA chemical vapor deposition method, the second insulating layer 67 is -20% to +20 to the deposition temperature of the first insulating layer 63. It is preferred to be a layer deposited within the temperature range of%, more preferably a layer deposited at the same deposition temperature.

This result can be confirmed from FIG. 2. FIG. 2 shows that the silicon oxide film is deposited at 250 ° C. with the first insulating layer 63 and the deposition temperature is changed with the second insulating layer 67. The pass rate of the sample is shown in%. Twenty samples were prepared for each deposition temperature of the second insulating layer, and the samples were tested under humidification conditions. Referring to FIG. 2, the second insulating layer was found to have excellent reliability when deposited at a deposition temperature within ± 20% of the deposition temperature of the first insulating layer (250 ° C.). In this case, it can be seen that the reliability is drastically reduced. In addition, when the first insulating layer and the second insulating layer are deposited at the same deposition temperature, it exhibits a 100% pass rate, which is the best reliability.

On the other hand, the second insulating layer 67 has a thickness relatively thinner than the first insulating layer 63, and preferably has a thickness of 500 kPa or more. Since the second insulating layer 67 is relatively thin as compared with the first insulating layer 63, the second insulating layer can be prevented from being peeled from the first insulating layer. In addition, when the second insulating layer is thinner than 2500 kPa, it is difficult to protect the wiring and the light emitting cell from external impact or moisture penetration.

The phosphor layer 69 may be a layer in which phosphors are dispersed in a resin or a layer deposited by electrophoresis. The phosphor layer 69 covers the second insulating layer 67 to wavelength convert the light emitted from the light emitting cells 56.

3 to 9 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 3, a lower semiconductor layer 55, an active layer 57, and an upper semiconductor layer 59 are formed on the substrate 51. In addition, before the lower semiconductor layer 55 is formed, the buffer layer 53 may be formed on the substrate 51.

The substrate 51 may include sapphire (Al 2 O 3 ), silicon carbide (SiC), zinc oxide (ZnO), silicon (Si), gallium arsenide (GaAs), gallium phosphorus (GaP), and lithium-alumina (LiAl 2 O). 3 ), but may be boron nitride (BN), aluminum nitride (AlN) or gallium nitride (GaN) substrate, but is not limited thereto, and may be variously selected according to the material of the semiconductor layer to be formed on the substrate 51. have.

The buffer layer 53 is formed to mitigate lattice mismatch between the substrate 51 and the semiconductor layer 55 to be formed thereon, and may be formed of, for example, gallium nitride (GaN) or aluminum nitride (AlN). When the substrate 51 is a conductive substrate, the buffer layer 53 is preferably formed of an insulating layer or a semi-insulating layer, and may be formed of AlN or semi-insulating GaN.

The lower semiconductor layer 55, the active layer 57, and the upper semiconductor layer 59 may be formed of a gallium nitride-based semiconductor material, that is, (Al, In, Ga) N. The lower and upper semiconductor layers 55 and 59 and the active layer 57 use metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy, or hydride vapor phase epitaxy (HVPE) technology. Can be grown intermittently or continuously.

The lower and upper semiconductor layers are n-type and p-type, or p-type and n-type, respectively. In the gallium nitride-based compound semiconductor layer, the n-type semiconductor layer may be formed by doping with silicon (Si) as an impurity, and the p-type semiconductor layer may be formed by doping with magnesium (Mg) as an impurity.

Referring to FIG. 4, the upper semiconductor layer 59, the active layer 57, and the lower semiconductor layer 55 are patterned to form light emitting cells 56 spaced apart from each other. In this case, the upper semiconductor layer 59 is positioned on a portion of the lower semiconductor layer 55, and another region of the lower semiconductor layer 55 is exposed. Meanwhile, the buffer layer 53 may be removed between the light emitting cells to expose the substrate 51.

Referring to FIG. 5, a transparent electrode layer 61 may be formed on the upper semiconductor layer 59 of the light emitting cell 56. The transparent electrode layer 65 may be formed of a metal oxide such as indium tin oxide (ITO) or a transparent metal. In the case of a transparent metal, the transparent electrode layer 61 may include at least one metal selected from the group consisting of Au, Ni, Pt, Al, Cr, and Ti or an alloy thereof.

The transparent electrode layer 61 may have an opening 61a exposing the upper semiconductor layer 59. The transparent electrode layer 61 may be formed by being deposited on the light emitting cells 56, but is formed on the upper semiconductor layer 59 before forming the light emitting cells 56, and patterning the upper semiconductor layer. Can be patterned before.

The transparent electrode layer 61 may be heat-treated, for example, in a temperature range of 500 to 800 ° C. for the upper semiconductor layer 59 and the ohmic contact.

Referring to FIG. 6, a continuous first insulating layer 63 is formed on a substrate 51 having light emitting cells 56. The first insulating layer 63 covers the sidewalls and the upper surface of the light emitting cells 56 and covers the upper portion of the substrate 51 in the region between the light emitting cells 56. The first insulating layer 63 may be formed of, for example, a silicon oxide film or a silicon nitride film using plasma enhanced chemical vapor deposition (CVD). In this case, the first insulating layer 63 may be deposited in a temperature range of 200 ~ 300 ℃, it is preferably formed to a thickness of 4500 ~ 1㎛.

After that, the openings 63a are formed on the upper semiconductor layers 59 by patterning the first insulating layer 63, and the openings 63b are formed on other regions of the lower semiconductor layers 55. Is formed. When the transparent electrode layers 61 are formed, the transparent electrode layers 61 are exposed by the openings. In addition, when the transparent electrode layers 61 have openings 61a, the openings 63a of the first insulating layer 63 expose the openings 61a of the transparent electrode layers 61.

Referring to FIG. 7, wirings 65 are formed on the first insulating layer 63 having the openings 63a. The wires 65 are electrically connected to the lower semiconductor layers 55 and the upper semiconductor layers 59 through the openings 63a and 63b, and electrically connect adjacent light emitting cells 56. .

The wires 65 may be formed using a plating technique or a general electron beam deposition, chemical vapor deposition or physical vapor deposition technique.

Meanwhile, the interconnections 65 may be formed of a conductive material, for example, a doped semiconductor material or metal such as polycrystalline silicon. In particular, the interconnections 65 may be formed in a multi-layer structure, and may include, for example, a lower layer of Cr or Ti (65a in FIG. 1) and an upper layer of Cr or Ti (65c in FIG. 1). In addition, an intermediate layer of Au, Au / Ni or Au / Al (65b in FIG. 1) may be interposed between the lower layer and the upper layer. The wires 65 may be heat-treated in a temperature range of 300 to 500 ° C. in order to improve adhesion to the first insulating layer 63.

Referring to FIG. 8, a first insulating layer 67 is formed on the substrate 51 on which the wires 65 are formed. The second insulating layer 67 covers the wirings 65 and the first insulating layer 63. The second insulating layer may be formed of the same material as the first insulating layer 63, for example, a silicon oxide film or a silicon nitride film, and may be formed in a temperature range of 200 ° C. to 300 ° C. using a plasma enhanced chemical vapor deposition technique. In particular, the second insulating layer 67 is preferably deposited within a temperature range of -20% to + 20% relative to the deposition temperature of the first insulating layer 63.

Referring to FIG. 9, a phosphor layer 69 may be formed on the second insulating layer 67. The phosphor layer 69 may be formed by dispersing a phosphor in a resin and then coating the phosphor on the second insulating layer 67, or may be formed on the second insulating layer 67 using an electrophoresis method. have. As a result, a light emitting diode having a fluorescent material at the chip level is completed.

10 is a cross-sectional view for describing a light emitting diode according to another exemplary embodiment of the present invention. Here, a light emitting diode employing a polymer as the first insulating layer and the second insulating layer will be described.

Referring to FIG. 10, the light emitting diode may include a substrate 51, a plurality of light emitting cells 56, a first insulating layer 83, wires 85, and a second insulating layer 87. And a buffer layer 53 and a transparent electrode layer 61. Since the substrate 51, the light emitting cells 56, and the transparent electrode layer 61 are the same as the light emitting diodes described with reference to FIG. 1, a detailed description thereof will be omitted.

The first insulating layer 83 is formed of SOG or BCB or other transparent polymer to fill the space between the light emitting cells 56. The first insulating layer 83 may cover other regions of the lower semiconductor layers 55, and in this case, have openings that expose the lower semiconductor layers 55. In addition, the first insulating layer 83 exposes the upper semiconductor layers 59 or the transparent electrode layers 61. Sidewalls of the light emitting cells 56 are covered by the first insulating layer 83.

Meanwhile, the wirings 85 are formed on the first insulating layer 83 to be electrically connected to the lower semiconductor layers 55 and the upper semiconductor layers 59. The wirings 85 are electrically connected to the lower semiconductor layers 55 through the openings and to the upper semiconductor layers 59. In addition, the wirings 85 may electrically connect the lower semiconductor layers 55 and the upper semiconductor layers 59 of adjacent light emitting cells 56 to form a series array of light emitting cells 56. . A plurality of such arrays may be formed, and the plurality of arrays may be connected in reverse parallel to each other and connected to an AC power supply. In addition, a bridge rectifier (not shown) connected to a series array of light emitting cells may be formed, and the light emitting cells may be driven under AC power by the bridge rectifier. The bridge rectifier may be formed by connecting the light emitting cells having the same structure as the light emitting cells 56 using the wirings 85.

Alternatively, the wires 85 may connect the lower semiconductor layers 55 of adjacent light emitting cells to each other or the upper semiconductor layers 59 to each other. Accordingly, a plurality of light emitting cells 56 connected in series and in parallel may be provided.

The wirings 65 may be formed of a conductive material, for example, a doped semiconductor material or metal such as polycrystalline silicon. In particular, the wirings 65 may be formed in a multilayer structure.

The second insulating layer 87 covers the wires 85 and the first insulating layer 83. The second insulating layer 87 is formed of a polymer having the same material as the first insulating layer 83. Thus, the adhesion between the first insulating layer 83 and the second insulating layer 87 is enhanced. In addition, the second insulating layer 87 is preferably thinner than the thickness of the first insulating layer 83 filling the space between the light emitting cells 56.

On the other hand, the second insulating layer 87 may contain a phosphor. Accordingly, a light emitting diode capable of converting wavelength at the chip level may be provided.

According to the present embodiment, since the first insulating layer is formed using a polymer, the wirings 85 and the second insulating layer 87 can be formed on the relatively flat first insulating layer to further improve the reliability of the wiring. Can be improved.

11 to 13 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 11, as described above with reference to FIGS. 3 to 5, a plurality of light emitting cells 56 and a transparent electrode layer 61 spaced apart from each other are formed on a single substrate 51. The light emitting cells 56 have a lower semiconductor layer 55, an active layer 57, and an upper semiconductor layer 59, respectively. The transparent electrode layer 61 may have openings 61a exposing the upper semiconductor layers 59.

Referring to FIG. 12, a first insulating layer 83 is formed to cover the light emitting cells 56 and the transparent electrode layer 61. The first insulating layer 83 is formed of a polymer and fills a space between the light emitting cells 56 and covers the entire surface of the light emitting cells 56.

Referring to FIG. 13, the first insulating layer 83 is partially etched away to expose the transparent electrode layer 61. After that, wirings 85 are formed on the first insulating layer 83 and the light emitting cells 56. The wirings 85 may be formed of a material as described with reference to FIG. 7.

Thereafter, a second insulating layer (87 in FIG. 10) covering the wires 85 and the first insulating layer 83 is formed. The second insulating layer may be formed of a polymer having the same material as that of the first insulating layer 83 and may contain a phosphor.

On the other hand, when the second insulating layer is thicker than the first insulating layer, the light transmittance is deteriorated, and the second insulating layer or the first insulating layer may be peeled from the light emitting cells by external impact. Therefore, the second insulating layer 87 is preferably thinner than the thickness of the first insulating layer 83 (in this case, the thickness of the insulating layer 83 filling the space between the light emitting cells).

In the present embodiment, it has been described that the phosphor is contained in the second insulating layer 87, but the phosphor may also be contained in the first insulating layer 83. In addition, a phosphor layer may be separately formed on the second insulating layer 87.

1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.

2 shows the reliability test pass rate according to the deposition temperature of the first insulating layer and the second insulating layer.

3 to 9 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.

10 is a cross-sectional view for describing a light emitting diode according to another exemplary embodiment of the present invention.

11 to 13 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention.

Claims (28)

  1. A plurality of light emitting cells, which are spaced apart from each other on a single substrate, include a lower semiconductor layer, an upper semiconductor layer positioned above an area of the lower semiconductor layer, and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer. field;
    A first insulating layer covering an entire surface of the light emitting cells, the first insulating layer having openings formed in the other regions of the lower semiconductor layers and the upper semiconductor layers, respectively;
    Wires formed on the first insulating layer and electrically connecting adjacent light emitting cells through the openings; And
    A second insulating layer covering the first insulating layer and the wirings;
    The first insulating layer and the second insulating layer is formed of the same material,
    The first insulating layer is relatively thicker than the second insulating layer.
  2. The light emitting diode of claim 1, wherein the first insulating layer has a thickness in the range of 4500 kPa to 1 µm, and the second insulating layer has a thickness greater than 500 kPa.
  3. The light emitting diode of claim 2, wherein the first insulating layer and the second insulating layer are silicon oxide films deposited at a temperature of 200 ° C. to 300 ° C. by plasma enhanced chemical vapor deposition.
  4. The light emitting diode of claim 3, wherein the second insulating layer is a silicon oxide film deposited at a temperature within a range of -20% to + 20% of the deposition temperature of the first insulating layer.
  5. The method according to claim 2, wherein the wiring has a multi-layer structure having a lower layer in contact with the first insulating layer and the upper layer in contact with the second insulating layer, the lower layer is a Cr layer or a Ti layer, the upper layer is a Cr layer or a Ti layer Light emitting diode.
  6. The light emitting diode of claim 5, further comprising an Au layer, an Au / Ni layer, and an Au / Al layer interposed between the lower layer and the upper layer.
  7. The light emitting diode of claim 2, wherein the first insulating layer and the second insulating layer are silicon nitride.
  8. The light emitting diode of claim 1, wherein the first insulating layer and the second insulating layer are polymers.
  9. The light emitting diode of claim 8, wherein the second insulating layer contains a phosphor in at least a partial region.
  10. The light emitting diode of claim 1, further comprising a phosphor layer on the second insulating layer.
  11. The light emitting diode of claim 1, further comprising transparent electrode layers interposed between the first insulating layer and the upper semiconductor layers.
  12. The light emitting diode of claim 11, wherein the transparent electrode layer is ITO.
  13. The light emitting diode of claim 11, wherein the transparent electrode layers include at least one metal selected from the group consisting of Au, Ni, Pt, Al, Cr, and Ti.
  14. The light emitting diode of claim 11, wherein the transparent electrode layers have openings exposing the upper semiconductor layers, and the wirings fill the openings of the transparent electrode layers.
  15. Forming a plurality of light emitting cells spaced apart from each other on a single substrate, wherein the light emitting cells are respectively disposed between a lower semiconductor layer, an upper semiconductor layer positioned above an area of the lower semiconductor layer, and between the lower semiconductor layer and the upper semiconductor layer; Including an intervening active layer,
    Forming a first insulating layer covering the plurality of light emitting cells, the first insulating layer having other regions of the lower semiconductor layers and openings formed on the upper semiconductor layers,
    Forming interconnections on the first insulating layer to electrically connect the light emitting cells through the openings;
    Forming a second insulating layer covering the first insulating layer and the wirings;
    The first insulating layer and the second insulating layer is formed of the same material,
    The first insulating layer is a relatively thicker light emitting diode manufacturing method than the second insulating layer.
  16. The method of claim 15, wherein the first insulating layer has a thickness within the range of 4500 kPa to 1 μm, and the second insulating layer has a thickness greater than 500 kPa.
  17. The method of claim 16, wherein the first insulating layer and the second insulating layer are silicon oxide films deposited at a temperature of 200 ° C. to 300 ° C. by plasma enhanced chemical vapor deposition.
  18. The method of claim 17, wherein the second insulating layer is a silicon oxide film deposited at a temperature within a range of −20% to + 20% of the deposition temperature of the first insulating layer.
  19. The method of claim 16, wherein the wirings include a lower layer in contact with the first insulating layer and an upper layer in contact with the second insulating layer, wherein the lower layer is a Cr layer, and the upper layer is a Cr layer or a Ti layer.
  20. The method of claim 19, further comprising heat treating the wirings to improve an interface bonding property between the wirings and the first insulating layer before forming the second insulating layer.
  21. The method of claim 20, wherein the wirings are heat treated at a temperature in a range of 300 ° C. to 500 ° C. 21.
  22. The method of claim 16, wherein the first insulating layer and the second insulating layer are silicon nitride films formed by plasma enhanced chemical vapor deposition.
  23. The method of claim 15, wherein the first insulating layer and the second insulating layer are formed of a polymer.
  24. The method of claim 23, wherein the second insulating layer contains a phosphor.
  25. The method of claim 15, further comprising forming a phosphor layer on the second insulating layer.
  26. The method of claim 1, wherein the forming of the plurality of light emitting cells further comprises forming a transparent electrode layer on the upper semiconductor layer.
  27. The method of claim 26, wherein the transparent electrode layer is heat-treated at a temperature of 500 ~ 800 ℃.
  28. The method of claim 26, wherein the transparent electrode layer is formed to have an opening that exposes the upper semiconductor layer,
    And the wirings fill the openings of the transparent electrode layer.
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TW098128710A TWI483381B (en) 2008-12-17 2009-08-26 Light emitting diode having plurality of light emitting cells and method of fabricating the same
EP20090013481 EP2200085B1 (en) 2008-12-17 2009-10-26 Light emitting diode having plurality of light emitting cells
US12/620,887 US7709849B1 (en) 2008-12-17 2009-11-18 Light emitting diode having plurality of light emitting cells and method of fabricating the same
EP20090014469 EP2200086B1 (en) 2008-12-17 2009-11-19 Method of fabricating a light emitting diode having a plurality of light emitting cells
CN 200910224858 CN101752399B (en) 2008-12-17 2009-11-27 Light emitting diode having a plurality of light emitting cells and method of fabricating the same
JP2009270778A JP4663810B2 (en) 2008-12-17 2009-11-27 Light emitting diode having a plurality of light emitting cells and method for manufacturing the same
JP2009273134A JP5706082B2 (en) 2008-12-17 2009-12-01 Light emitting diode having a plurality of light emitting cells and method for manufacturing the same
US12/633,603 US7846755B2 (en) 2008-12-17 2009-12-08 Light emitting diode having plurality of light emitting cells and method of fabricating the same

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US7714348B2 (en) * 2006-10-06 2010-05-11 Ac-Led Lighting, L.L.C. AC/DC light emitting diodes with integrated protection mechanism
US7768020B2 (en) * 2007-03-13 2010-08-03 Seoul Opto Device Co., Ltd. AC light emitting diode
KR100974923B1 (en) 2007-03-19 2010-08-10 서울옵토디바이스주식회사 Light emitting diode

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EP2416556A2 (en) 2010-08-06 2012-02-08 Samsung Electronics Co., Ltd. Controller chip and image forming apparatus to perform color mis-registration correction and methods thereof
WO2013168929A1 (en) * 2012-05-11 2013-11-14 Seoul Opto Device Co., Ltd. Light emitting diode having plurality of light emitting elements and method of fabricating the same
KR20140020190A (en) * 2012-08-07 2014-02-18 서울바이오시스 주식회사 Light emitting diode array on wafer level and method of forming the same
KR20180098486A (en) * 2012-08-07 2018-09-04 서울바이오시스 주식회사 Light emitting diode array on wafer level
KR20140029174A (en) * 2012-08-28 2014-03-10 서울바이오시스 주식회사 Light emitting diode array on wafer level and method of forming the same

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US7709849B1 (en) 2010-05-04
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JP2010147462A (en) 2010-07-01
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TW201025558A (en) 2010-07-01
JP2010147463A (en) 2010-07-01

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