TWI482171B - 撓性及可擴展之記憶體架構 - Google Patents

撓性及可擴展之記憶體架構 Download PDF

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Publication number
TWI482171B
TWI482171B TW098126414A TW98126414A TWI482171B TW I482171 B TWI482171 B TW I482171B TW 098126414 A TW098126414 A TW 098126414A TW 98126414 A TW98126414 A TW 98126414A TW I482171 B TWI482171 B TW I482171B
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TW
Taiwan
Prior art keywords
memory
group
coupled
source
memory blocks
Prior art date
Application number
TW098126414A
Other languages
English (en)
Chinese (zh)
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TW201021048A (en
Inventor
David R Resnick
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of TW201021048A publication Critical patent/TW201021048A/zh
Application granted granted Critical
Publication of TWI482171B publication Critical patent/TWI482171B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/287—Multiplexed DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
TW098126414A 2008-08-05 2009-08-05 撓性及可擴展之記憶體架構 TWI482171B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/186,357 US8656082B2 (en) 2008-08-05 2008-08-05 Flexible and expandable memory architectures

Publications (2)

Publication Number Publication Date
TW201021048A TW201021048A (en) 2010-06-01
TWI482171B true TWI482171B (zh) 2015-04-21

Family

ID=41653955

Family Applications (2)

Application Number Title Priority Date Filing Date
TW098126414A TWI482171B (zh) 2008-08-05 2009-08-05 撓性及可擴展之記憶體架構
TW104106918A TWI559323B (zh) 2008-08-05 2009-08-05 撓性及可擴展之記憶體架構

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW104106918A TWI559323B (zh) 2008-08-05 2009-08-05 撓性及可擴展之記憶體架構

Country Status (7)

Country Link
US (2) US8656082B2 (enExample)
EP (1) EP2310943B1 (enExample)
JP (2) JP5666445B2 (enExample)
KR (2) KR101584391B1 (enExample)
CN (2) CN102144223B (enExample)
TW (2) TWI482171B (enExample)
WO (1) WO2010016889A2 (enExample)

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US8656082B2 (en) 2008-08-05 2014-02-18 Micron Technology, Inc. Flexible and expandable memory architectures
US8549092B2 (en) * 2009-02-19 2013-10-01 Micron Technology, Inc. Memory network methods, apparatus, and systems
TWI474331B (zh) * 2009-06-30 2015-02-21 日立製作所股份有限公司 Semiconductor device
US20130019053A1 (en) * 2011-07-14 2013-01-17 Vinay Ashok Somanache Flash controller hardware architecture for flash devices
US8996822B2 (en) * 2011-07-29 2015-03-31 Micron Technology, Inc. Multi-device memory serial architecture
US9003160B2 (en) 2012-08-03 2015-04-07 International Business Machines Corporation Active buffered memory
US9569211B2 (en) * 2012-08-03 2017-02-14 International Business Machines Corporation Predication in a vector processor
US9575755B2 (en) 2012-08-03 2017-02-21 International Business Machines Corporation Vector processing in an active memory device
US9632777B2 (en) 2012-08-03 2017-04-25 International Business Machines Corporation Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry
US9594724B2 (en) 2012-08-09 2017-03-14 International Business Machines Corporation Vector register file
US9298395B2 (en) 2012-10-22 2016-03-29 Globalfoundries Inc. Memory system connector
US8972782B2 (en) 2012-11-09 2015-03-03 International Business Machines Corporation Exposed-pipeline processing element with rollback
JP5985403B2 (ja) 2013-01-10 2016-09-06 株式会社東芝 ストレージ装置
US9244684B2 (en) 2013-03-15 2016-01-26 Intel Corporation Limited range vector memory access instructions, processors, methods, and systems
US9236564B2 (en) 2013-12-11 2016-01-12 Samsung Electronics Co., Ltd. Method and system for providing an engineered magnetic layer including Heusler layers and an amorphous insertion layer
US9880971B2 (en) 2013-12-20 2018-01-30 Rambus Inc. Memory appliance for accessing memory
US9558143B2 (en) * 2014-05-09 2017-01-31 Micron Technology, Inc. Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device

Citations (5)

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US20060277355A1 (en) * 2005-06-01 2006-12-07 Mark Ellsberry Capacity-expanding memory device
US20070011578A1 (en) * 2005-06-08 2007-01-11 Altera Corporation Reducing false positives in configuration error detection for programmable devices
US20070136537A1 (en) * 2005-12-14 2007-06-14 Sun Microsystems, Inc. System memory board subsystem using dram with stacked dedicated high speed point to point links
US20080099753A1 (en) * 2006-10-31 2008-05-01 Samsung Electronics Co., Ltd. Phase change memory devices having dual lower electrodes and methods of fabricating the same
US20090172213A1 (en) * 2007-12-31 2009-07-02 Sowmiya Jayachandran Command completion detection in a mass storage device

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DE69530292T2 (de) * 1994-04-13 2003-12-04 Ericsson Inc., Research Triangle Park Effiziente adressierung von grossen speichern
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CN102033581B (zh) * 2009-12-18 2012-05-30 中国科学院声学研究所 一种基于多核网络处理器的高可扩展性atca板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060277355A1 (en) * 2005-06-01 2006-12-07 Mark Ellsberry Capacity-expanding memory device
US20070011578A1 (en) * 2005-06-08 2007-01-11 Altera Corporation Reducing false positives in configuration error detection for programmable devices
US20070136537A1 (en) * 2005-12-14 2007-06-14 Sun Microsystems, Inc. System memory board subsystem using dram with stacked dedicated high speed point to point links
US20080099753A1 (en) * 2006-10-31 2008-05-01 Samsung Electronics Co., Ltd. Phase change memory devices having dual lower electrodes and methods of fabricating the same
US20090172213A1 (en) * 2007-12-31 2009-07-02 Sowmiya Jayachandran Command completion detection in a mass storage device

Also Published As

Publication number Publication date
EP2310943A2 (en) 2011-04-20
JP5820038B2 (ja) 2015-11-24
US9348785B2 (en) 2016-05-24
JP5666445B2 (ja) 2015-02-12
CN102144223B (zh) 2014-11-26
JP2015008011A (ja) 2015-01-15
EP2310943B1 (en) 2015-04-08
CN102144223A (zh) 2011-08-03
US8656082B2 (en) 2014-02-18
US20140164667A1 (en) 2014-06-12
JP2011530736A (ja) 2011-12-22
US20100036994A1 (en) 2010-02-11
CN104281556A (zh) 2015-01-14
EP2310943A4 (en) 2012-06-27
KR20150068494A (ko) 2015-06-19
KR101584391B1 (ko) 2016-01-21
TW201523628A (zh) 2015-06-16
KR101563474B1 (ko) 2015-10-26
KR20110050497A (ko) 2011-05-13
CN104281556B (zh) 2019-11-08
WO2010016889A2 (en) 2010-02-11
WO2010016889A3 (en) 2010-05-14
TW201021048A (en) 2010-06-01
TWI559323B (zh) 2016-11-21

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