CN102144223B - 灵活及可扩展的存储器架构 - Google Patents

灵活及可扩展的存储器架构 Download PDF

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Publication number
CN102144223B
CN102144223B CN200980134760.9A CN200980134760A CN102144223B CN 102144223 B CN102144223 B CN 102144223B CN 200980134760 A CN200980134760 A CN 200980134760A CN 102144223 B CN102144223 B CN 102144223B
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China
Prior art keywords
memory
group
coupled
source
cube
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Chinese (zh)
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CN102144223A (zh
Inventor
戴维·R·雷斯尼克
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Micron Technology Inc
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Micron Technology Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/287—Multiplexed DMA

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
CN200980134760.9A 2008-08-05 2009-08-04 灵活及可扩展的存储器架构 Active CN102144223B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410553458.XA CN104281556B (zh) 2008-08-05 2009-08-04 灵活及可扩展的存储器架构

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/186,357 US8656082B2 (en) 2008-08-05 2008-08-05 Flexible and expandable memory architectures
US12/186,357 2008-08-05
PCT/US2009/004461 WO2010016889A2 (en) 2008-08-05 2009-08-04 Flexible and expandable memory architectures

Related Child Applications (1)

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CN201410553458.XA Division CN104281556B (zh) 2008-08-05 2009-08-04 灵活及可扩展的存储器架构

Publications (2)

Publication Number Publication Date
CN102144223A CN102144223A (zh) 2011-08-03
CN102144223B true CN102144223B (zh) 2014-11-26

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CN200980134760.9A Active CN102144223B (zh) 2008-08-05 2009-08-04 灵活及可扩展的存储器架构
CN201410553458.XA Active CN104281556B (zh) 2008-08-05 2009-08-04 灵活及可扩展的存储器架构

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CN201410553458.XA Active CN104281556B (zh) 2008-08-05 2009-08-04 灵活及可扩展的存储器架构

Country Status (7)

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US (2) US8656082B2 (enExample)
EP (1) EP2310943B1 (enExample)
JP (2) JP5666445B2 (enExample)
KR (2) KR101584391B1 (enExample)
CN (2) CN102144223B (enExample)
TW (2) TWI482171B (enExample)
WO (1) WO2010016889A2 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8656082B2 (en) 2008-08-05 2014-02-18 Micron Technology, Inc. Flexible and expandable memory architectures
US8549092B2 (en) * 2009-02-19 2013-10-01 Micron Technology, Inc. Memory network methods, apparatus, and systems
TWI474331B (zh) * 2009-06-30 2015-02-21 日立製作所股份有限公司 Semiconductor device
US20130019053A1 (en) * 2011-07-14 2013-01-17 Vinay Ashok Somanache Flash controller hardware architecture for flash devices
US8996822B2 (en) * 2011-07-29 2015-03-31 Micron Technology, Inc. Multi-device memory serial architecture
US9003160B2 (en) 2012-08-03 2015-04-07 International Business Machines Corporation Active buffered memory
US9569211B2 (en) * 2012-08-03 2017-02-14 International Business Machines Corporation Predication in a vector processor
US9575755B2 (en) 2012-08-03 2017-02-21 International Business Machines Corporation Vector processing in an active memory device
US9632777B2 (en) 2012-08-03 2017-04-25 International Business Machines Corporation Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry
US9594724B2 (en) 2012-08-09 2017-03-14 International Business Machines Corporation Vector register file
US9298395B2 (en) 2012-10-22 2016-03-29 Globalfoundries Inc. Memory system connector
US8972782B2 (en) 2012-11-09 2015-03-03 International Business Machines Corporation Exposed-pipeline processing element with rollback
JP5985403B2 (ja) 2013-01-10 2016-09-06 株式会社東芝 ストレージ装置
US9244684B2 (en) 2013-03-15 2016-01-26 Intel Corporation Limited range vector memory access instructions, processors, methods, and systems
US9236564B2 (en) 2013-12-11 2016-01-12 Samsung Electronics Co., Ltd. Method and system for providing an engineered magnetic layer including Heusler layers and an amorphous insertion layer
US9880971B2 (en) 2013-12-20 2018-01-30 Rambus Inc. Memory appliance for accessing memory
US9558143B2 (en) * 2014-05-09 2017-01-31 Micron Technology, Inc. Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396606A (en) * 1991-07-31 1995-03-07 Franklin Electronic Publishers, Incorporated Address bus switching between sequential and non-sequential ROM searches
CN1205477A (zh) * 1998-07-16 1999-01-20 英业达股份有限公司 存储器替代方法及其装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69530292T2 (de) * 1994-04-13 2003-12-04 Ericsson Inc., Research Triangle Park Effiziente adressierung von grossen speichern
US6038630A (en) * 1998-03-24 2000-03-14 International Business Machines Corporation Shared access control device for integrated system with multiple functional units accessing external structures over multiple data buses
US6633947B1 (en) * 1998-09-16 2003-10-14 Intel Corporation Memory expansion channel for propagation of control and request packets
JP4483168B2 (ja) * 2002-10-23 2010-06-16 株式会社日立製作所 ディスクアレイ制御装置
US7870218B2 (en) * 2003-04-09 2011-01-11 Nec Laboratories America, Inc. Peer-to-peer system and method with improved utilization
US7788451B2 (en) * 2004-02-05 2010-08-31 Micron Technology, Inc. Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
US7366864B2 (en) * 2004-03-08 2008-04-29 Micron Technology, Inc. Memory hub architecture having programmable lane widths
US7120723B2 (en) * 2004-03-25 2006-10-10 Micron Technology, Inc. System and method for memory hub-based expansion bus
CA2597692A1 (en) * 2005-04-21 2006-11-02 Violin Memory, Inc. Interconnection system
US20060277355A1 (en) * 2005-06-01 2006-12-07 Mark Ellsberry Capacity-expanding memory device
DE102005024988A1 (de) * 2005-06-01 2006-12-07 Robert Bosch Gmbh Verfahren zur Kommunikation zwischen mindestens zwei Teilnehmern eines Kommunikationssystems
US7620876B2 (en) * 2005-06-08 2009-11-17 Altera Corporation Reducing false positives in configuration error detection for programmable devices
US7409491B2 (en) * 2005-12-14 2008-08-05 Sun Microsystems, Inc. System memory board subsystem using DRAM with stacked dedicated high speed point to point links
US7493439B2 (en) * 2006-08-01 2009-02-17 International Business Machines Corporation Systems and methods for providing performance monitoring in a memory system
KR100827661B1 (ko) * 2006-10-31 2008-05-07 삼성전자주식회사 이중의 하부 전극을 갖는 상변화 기억소자 및 그 제조방법
US8145869B2 (en) 2007-01-12 2012-03-27 Broadbus Technologies, Inc. Data access and multi-chip controller
US20090172213A1 (en) * 2007-12-31 2009-07-02 Sowmiya Jayachandran Command completion detection in a mass storage device
US8656082B2 (en) 2008-08-05 2014-02-18 Micron Technology, Inc. Flexible and expandable memory architectures
CN102033581B (zh) * 2009-12-18 2012-05-30 中国科学院声学研究所 一种基于多核网络处理器的高可扩展性atca板

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396606A (en) * 1991-07-31 1995-03-07 Franklin Electronic Publishers, Incorporated Address bus switching between sequential and non-sequential ROM searches
CN1205477A (zh) * 1998-07-16 1999-01-20 英业达股份有限公司 存储器替代方法及其装置

Also Published As

Publication number Publication date
EP2310943A2 (en) 2011-04-20
JP5820038B2 (ja) 2015-11-24
US9348785B2 (en) 2016-05-24
JP5666445B2 (ja) 2015-02-12
JP2015008011A (ja) 2015-01-15
EP2310943B1 (en) 2015-04-08
CN102144223A (zh) 2011-08-03
TWI482171B (zh) 2015-04-21
US8656082B2 (en) 2014-02-18
US20140164667A1 (en) 2014-06-12
JP2011530736A (ja) 2011-12-22
US20100036994A1 (en) 2010-02-11
CN104281556A (zh) 2015-01-14
EP2310943A4 (en) 2012-06-27
KR20150068494A (ko) 2015-06-19
KR101584391B1 (ko) 2016-01-21
TW201523628A (zh) 2015-06-16
KR101563474B1 (ko) 2015-10-26
KR20110050497A (ko) 2011-05-13
CN104281556B (zh) 2019-11-08
WO2010016889A2 (en) 2010-02-11
WO2010016889A3 (en) 2010-05-14
TW201021048A (en) 2010-06-01
TWI559323B (zh) 2016-11-21

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