TWI477436B - Method for manufacturing a micro-electromechanical device - Google Patents

Method for manufacturing a micro-electromechanical device Download PDF

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TWI477436B
TWI477436B TW100106943A TW100106943A TWI477436B TW I477436 B TWI477436 B TW I477436B TW 100106943 A TW100106943 A TW 100106943A TW 100106943 A TW100106943 A TW 100106943A TW I477436 B TWI477436 B TW I477436B
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substrate
microstructure
layer
circuit layer
recess
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TW201236965A (en
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Siewseong Tan
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Memsor Corp
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製造微機電裝置之方法Method of manufacturing a microelectromechanical device

本發明是有關於一種製造微機電裝置的方法。The present invention is directed to a method of making a microelectromechanical device.

隨著半導體製程技術的進步,已推動微機電系統(MEMS)的蓬勃發展。在傳統微機械系統的製造方法中,主動元件製程與微機電製程是分開進行,在分別完成主動元件電路與微機電裝置後,再將兩者整合在同一基材上而完成微機電系統。上述的製造方法又稱為「System In Package」(SIP)。With the advancement of semiconductor process technology, the development of microelectromechanical systems (MEMS) has been promoted. In the manufacturing method of the conventional micromechanical system, the active component process and the microelectromechanical process are performed separately, and after the active component circuit and the microelectromechanical device are respectively completed, the two are integrated on the same substrate to complete the MEMS system. The above manufacturing method is also called "System In Package" (SIP).

另一種習知的製造方式是在形成主動元件電路中諸如金屬氧化物半導體元件(MOS)及雙載子接面電晶體(BJT)等半導體元件後,再進行形成微機電結構的製程,然後再進行主動元件電路的金屬化製程而完成晶圓層級(wafer level)的微機電系統。隨後將晶圓切割成晶片(Die),最後再進行晶片的封裝。Another conventional manufacturing method is to form a microelectromechanical structure after forming semiconductor elements such as a metal oxide semiconductor device (MOS) and a bipolar junction transistor (BJT) in an active device circuit, and then A wafer level MEMS is completed by performing a metallization process of the active device circuit. The wafer is then diced into wafers (Die) and finally wafer packaged.

無論是上述何種製造方式,在微機電裝置的製造過程中,通常採用諸如反應性離子蝕刻(RIE)之電漿蝕刻方式來形成微機電裝置中可移動的構件或部分。但是,以上述方式所形成的微機電裝置的輪廓(profile)並不理想。此外,在形成微機電裝置的可移動的構件時,通常必須藉由一研磨步驟才能完成。但是,研磨步驟常伴隨震動發生,而導致微機電裝置中的某些細微結構受損。Regardless of the manufacturing method described above, in the manufacturing process of a microelectromechanical device, a plasma etching method such as reactive ion etching (RIE) is generally employed to form a movable member or portion of the microelectromechanical device. However, the profile of the microelectromechanical device formed in the above manner is not ideal. In addition, when forming a movable member of a microelectromechanical device, it usually has to be completed by a grinding step. However, the grinding step is often accompanied by vibrations that cause some of the fine structures in the microelectromechanical device to be damaged.

因此,目前亟需一種新的製造方法,期能改善上述問題。Therefore, there is a need for a new manufacturing method that will improve the above problems.

本發明之一目的係提供一種製造微機電裝置的方法,俾能改善上述問題。It is an object of the present invention to provide a method of fabricating a microelectromechanical device that can ameliorate the above problems.

根據本發明一實施方式,此方法包含以下步驟:(a)形成一電路層於一基材之一上表面,其中電路層包含一微結構以及一主動元件,且微結構電性連接主動元件;(b)形成一凹槽貫穿電路層並深入基材,使凹槽之一底部低於基材之上表面,其中凹槽圍繞微結構之周邊的一部分;(c)形成一犧牲層填充於凹槽內;(d)配置一上蓋體於電路層上方,以覆蓋微結構;(e)由基材之下表面一側移除基材的部分,以露出犧牲層;(f)移除犧牲層以釋放微結構;以及(g)配置一下蓋體於基材下方。According to an embodiment of the invention, the method comprises the steps of: (a) forming a circuit layer on an upper surface of a substrate, wherein the circuit layer comprises a microstructure and an active component, and the microstructure is electrically connected to the active component; (b) forming a recess through the circuit layer and deep into the substrate such that one of the bottoms of the recess is lower than the upper surface of the substrate, wherein the recess surrounds a portion of the periphery of the microstructure; (c) a sacrificial layer is formed to fill the recess (d) arranging an upper cover over the circuit layer to cover the microstructure; (e) removing a portion of the substrate from a side of the lower surface of the substrate to expose the sacrificial layer; (f) removing the sacrificial layer To release the microstructure; and (g) to configure the cover below the substrate.

根據本發明一實施例,步驟(a)之電路層更包括一連接墊以及一保護層,其中連接墊電性連接主動元件,保護層位於電路層之一外表面,且覆蓋連接墊。在一實施例中,於步驟(g)後更包括:(h)移除上蓋體之部分,以露出位於連接墊上方之保護層的部分;以及(g)移除保護層之部分,以露出連接墊。According to an embodiment of the invention, the circuit layer of step (a) further comprises a connection pad and a protective layer, wherein the connection pad is electrically connected to the active component, and the protection layer is located on an outer surface of the circuit layer and covers the connection pad. In an embodiment, after the step (g), the method further comprises: (h) removing a portion of the upper cover to expose a portion of the protective layer above the connection pad; and (g) removing a portion of the protective layer to expose Connection pad.

根據本發明一實施例,步驟(a)之主動元件為一互補式金屬氧化物半導體元件或雙極互補式金屬氧化物半導體元件。According to an embodiment of the invention, the active component of step (a) is a complementary metal oxide semiconductor component or a bipolar complementary metal oxide semiconductor component.

根據本發明一實施例,步驟(b)之底部與上表面間之一垂直距離為約5 μm至約100 μmAccording to an embodiment of the invention, the vertical distance between the bottom of the step (b) and the upper surface is from about 5 μm to about 100 μm.

根據本發明一實施例,步驟(c)之犧牲層為一高分子材料,且覆蓋微結構之一上表面。According to an embodiment of the invention, the sacrificial layer of step (c) is a polymer material and covers an upper surface of the microstructure.

根據本發明一實施例,步驟(e)包含研磨基材之下表面,以露出犧牲層。According to an embodiment of the invention, step (e) comprises grinding the underlying surface of the substrate to expose the sacrificial layer.

根據本發明一實施例,步驟(e)包含研磨基材之下表面,以及以深式反應離子蝕刻經研磨之基材,以露出犧牲層。According to an embodiment of the invention, step (e) comprises grinding the underlying surface of the substrate and etching the ground substrate by deep reactive ion etching to expose the sacrificial layer.

根據本發明一實施例,步驟(f)係以一氧電漿移除犧牲層。According to an embodiment of the invention, step (f) removes the sacrificial layer with an oxygen plasma.

根據本發明另一實施方式,製造微機電裝置的方法包含以下步驟。形成電路層於基材之上表面,電路層包含特徵結構以及微結構;其中特徵結構圍繞微結構之周邊的一部分並貫穿電路層,特徵結構包含一介電結構貫穿電路層以及一金屬結構貫穿電路層並環繞介電結構。接著,移除特徵結構以露出基材;其中移除特徵結構包含依序以乾式蝕刻移除介電結構以及濕式蝕刻移除金屬結構。然後,移除露出基材之一部分,以形成一凹槽;此凹槽貫穿電路層並具有一底部低於基材之上表面,凹槽圍繞微結構周邊的部分。隨後,形成一犧牲層填充於凹槽內,再配置一上蓋體於電路層上方以覆蓋微結構。接著,再由基材之下表面一側移除基材的部分,以露出犧牲層。然後,移除犧牲層以釋放微結構,並配置一下蓋體於基材下方。According to another embodiment of the present invention, a method of fabricating a microelectromechanical device includes the following steps. Forming a circuit layer on the upper surface of the substrate, the circuit layer comprising the characteristic structure and the microstructure; wherein the feature structure surrounds a portion of the periphery of the microstructure and penetrates the circuit layer, the feature structure comprises a dielectric structure penetrating the circuit layer and a metal structure penetrating circuit Layer and surround the dielectric structure. Next, the features are removed to expose the substrate; wherein removing the features comprises sequentially removing the dielectric structure by dry etching and wet etching to remove the metal structure. Then, a portion of the exposed substrate is removed to form a recess; the recess extends through the circuit layer and has a bottom portion that is lower than the upper surface of the substrate, the recess surrounding the perimeter of the microstructure. Subsequently, a sacrificial layer is formed to fill the recess, and an upper cover is disposed over the circuit layer to cover the microstructure. Next, a portion of the substrate is removed from the lower surface side of the substrate to expose the sacrificial layer. The sacrificial layer is then removed to release the microstructure and the cover is placed under the substrate.

請參照第1圖,其為本發明一實施方式之微機電裝置的上視示意圖。微機電裝置可應用在例如加速度偵測器(accelerometer)或陀螺儀(gyroscope)等之微機電慣性感測裝置。第1圖係繪示一微機電加速度偵測器,但本發明以下所揭露的製造方法可適用在其他的微機電裝置中,並不限於微機電加速度偵測器。Please refer to FIG. 1 , which is a top view of a microelectromechanical device according to an embodiment of the present invention. The microelectromechanical device can be applied to a microelectromechanical inertial sensing device such as an accelerometer or a gyroscope. FIG. 1 illustrates a microelectromechanical acceleration detector, but the manufacturing method disclosed in the present invention is applicable to other microelectromechanical devices, and is not limited to a microelectromechanical acceleration detector.

如第1圖所示,微機電加速度偵測器100主要包括可動的微結構110、半導體電路120、複數個連接墊130以及電路層140。半導體電路120大致配置在可動的微結構110之外圍。連接墊130通常可配置在半導體電路120的外圍。As shown in FIG. 1 , the MEMS acceleration detector 100 mainly includes a movable microstructure 110 , a semiconductor circuit 120 , a plurality of connection pads 130 , and a circuit layer 140 . The semiconductor circuit 120 is disposed substantially at the periphery of the movable microstructures 110. The connection pads 130 are typically configurable on the periphery of the semiconductor circuit 120.

微結構110容置在電路層140的貫穿空間142中,且微結構包括中心部112、至少一彈性支撐件114以及至少一第一電極116。彈性支撐件114連接中心部112與電路層140,且使中心部112呈現可移動狀態。當一外力作用在中心部112時,中心部112可產生位移;當外力消失時,中心部112可以回到原來的位置。彈性支撐件114的寬度可例如為約0.5μm至約10μm。第一電極116由中心部112向外延伸至貫穿空間142中。第一電極116的寬度可例如為約0.1μm至約10μm。The microstructure 110 is received in the through space 142 of the circuit layer 140 , and the microstructure includes a central portion 112 , at least one elastic support 114 , and at least one first electrode 116 . The elastic support member 114 connects the central portion 112 with the circuit layer 140 and causes the central portion 112 to assume a movable state. When an external force acts on the center portion 112, the center portion 112 can be displaced; when the external force disappears, the center portion 112 can return to the original position. The width of the elastic support 114 can be, for example, from about 0.5 μm to about 10 μm. The first electrode 116 extends outwardly from the central portion 112 into the through space 142. The width of the first electrode 116 may be, for example, from about 0.1 μm to about 10 μm.

電路層140包含有一第二電極144,第二電極144向貫穿空間142延伸,並與第一電極116形成一電容。The circuit layer 140 includes a second electrode 144 extending toward the through space 142 and forming a capacitance with the first electrode 116.

半導體電路120電性連接第二電極144及第一電極116,以量測兩電極116、144之間的電容值,並將所量測的電容訊號轉變為一電壓或電流訊號。半導體電路120可包括一互補式金屬氧化物半導體裝置。半導體電路120可經由連接墊130而電性連接一外部電路(未繪示)。The semiconductor circuit 120 is electrically connected to the second electrode 144 and the first electrode 116 to measure the capacitance between the two electrodes 116 and 144 and convert the measured capacitance signal into a voltage or current signal. Semiconductor circuit 120 can include a complementary metal oxide semiconductor device. The semiconductor circuit 120 can be electrically connected to an external circuit (not shown) via the connection pad 130.

在操作時,當微機電加速度偵測器100受到一加速度時,第二電極144與第一電極116之間的距離改變,使其間的電容值發生變化。半導體電路120量測上述電容值或電容值的變化量,而得以估算微機電加速度偵測器100所受到的加速度。In operation, when the MEMS acceleration detector 100 is subjected to an acceleration, the distance between the second electrode 144 and the first electrode 116 changes, and the capacitance value therebetween changes. The semiconductor circuit 120 measures the amount of change in the capacitance value or the capacitance value to estimate the acceleration received by the MEMS acceleration detector 100.

上述微機電加速度偵測器100僅為示範性例子,以易於瞭解本發明下文揭露的製造方法,本發明下文揭露的製造方法可用以製造其他的微機電裝置。再者,以下所揭露的各實施例,在有益的情形下可相互組合或取代,也可在一實施例中附加其他的實施例,而無須進一步的記載或說明。The above described microelectromechanical acceleration detector 100 is merely an illustrative example to facilitate an understanding of the manufacturing methods disclosed herein, and the manufacturing methods disclosed herein may be used to fabricate other microelectromechanical devices. Furthermore, the embodiments disclosed in the following may be combined or substituted with each other in an advantageous manner, and other embodiments may be added to an embodiment without further description or description.

第2圖為本發明一實施方式之製造微機電裝置之方法200的流程圖。第3至16圖係繪示本發明實施方式之製造方法中各製程階段的剖面示意圖,其大致為第1圖中線段3-3’的剖面示意圖。2 is a flow chart of a method 200 of fabricating a microelectromechanical device in accordance with an embodiment of the present invention. 3 to 16 are schematic cross-sectional views showing respective process stages in the manufacturing method of the embodiment of the present invention, which is roughly a schematic cross-sectional view of the line segment 3-3' in Fig. 1.

進行步驟210,形成電路層320於基材310的上表面,如第3圖所示。基材310可例如為矽晶圓或其他適合用以製造半導體元件的基材。電路層320包含微結構330以及主動元件322。微結構電性連接主動元件。主動元件322可例如為互補式金屬氧化物半導體元件(CMOS)或雙極互補式金屬氧化物半導體元件(BiCMOS)。Step 210 is performed to form circuit layer 320 on the upper surface of substrate 310, as shown in FIG. Substrate 310 can be, for example, a germanium wafer or other substrate suitable for use in fabricating semiconductor components. Circuit layer 320 includes microstructures 330 and active components 322. The microstructure is electrically connected to the active component. The active component 322 can be, for example, a complementary metal oxide semiconductor device (CMOS) or a bipolar complementary metal oxide semiconductor device (BiCMOS).

在一實施方式中,電路層320更包含特徵結構340填充於區域A中。特徵結構340圍繞微結構330之周邊的一部分,並貫穿電路層320。在後續的步驟中,特徵結構340將會被移除而形成第1圖繪示的貫穿空間142的一部分。換言之,特徵結構340預先填充在後續欲移除的區域A中。In an embodiment, circuit layer 320 further includes feature structure 340 filled in region A. Feature structure 340 surrounds a portion of the perimeter of microstructure 330 and extends through circuit layer 320. In a subsequent step, feature structure 340 will be removed to form a portion of through space 142 depicted in FIG. In other words, the feature structure 340 is pre-filled in the area A to be subsequently removed.

特徵結構340包含介電結構342以及金屬結構344。介電結構342貫穿電路層320,並接觸下方的基材310。介電結構342可例如為氧化矽或氮化矽,或由氧化矽及氮化矽堆疊而構成。金屬結構344也同樣貫穿電路層320,並且環繞介電結構342。換言之,金屬結構344形成在特徵結構340的外緣。更詳細而言,金屬結構344可包含344a及344b兩部分。金屬結構的344a部分實體連接電路層320與介電結構342;金屬結構的344b部分實體連接微結構330與介電結構342。Feature structure 340 includes a dielectric structure 342 and a metal structure 344. Dielectric structure 342 extends through circuit layer 320 and contacts underlying substrate 310. The dielectric structure 342 can be, for example, tantalum oxide or tantalum nitride, or a stack of tantalum oxide and tantalum nitride. Metal structure 344 also extends through circuit layer 320 and surrounds dielectric structure 342. In other words, the metal structure 344 is formed on the outer edge of the feature 340. In more detail, the metal structure 344 can comprise two portions 344a and 344b. The portion 344a of the metal structure physically connects the circuit layer 320 with the dielectric structure 342; the portion 344b of the metal structure physically connects the microstructure 330 with the dielectric structure 342.

在上述電路層320包含有特徵結構340的實施方式中,形成電路層320的步驟包括形成CMOS或BiCMOS的製程。在CMOS元件的標準製程中,可包括4道的金屬化製程以及2道的多晶矽化製程(2P4M製程),亦可包括5道的金屬化製程以及1道的多晶矽化製程(5M1P製程)。因此,在一實施例中,當形成CMOS元件322時,可藉由適當的光罩設計,同時形成特徵結構340。舉例而言,當形成CMOS元件322中的介電層時,可同時形成特徵結構340的介電結構342。當形成CMOS元件322的金屬層時,可同時形成特徵結構340中部分的金屬結構344。當填充金屬於CMOS元件的連接孔(via)時,可同時形成金屬結構344的一部分。因此,能夠在形成CMOS元件322的同時,逐步形成特徵結構340。在一實施例中,填充在CMOS元件通孔的金屬為鎢,CMOS元件322的金屬層為鋁。因此,金屬結構344可由鋁層及鎢層堆疊而成。亦即,金屬結構344為多層結構,且至少由兩種金屬材料所構成。In embodiments in which the circuit layer 320 described above includes features 340, the step of forming the circuit layer 320 includes forming a CMOS or BiCMOS process. In the standard process of CMOS components, it can include four metallization processes and two polysiliconization processes (2P4M process), and can also include five metallization processes and one polysiliconization process (5M1P process). Thus, in an embodiment, when CMOS component 322 is formed, feature 340 can be formed simultaneously by a suitable reticle design. For example, when forming a dielectric layer in CMOS device 322, dielectric structure 342 of feature structure 340 can be formed simultaneously. When the metal layer of CMOS element 322 is formed, portions of metal structure 344 in feature structure 340 can be formed simultaneously. When the metal is filled in the via of the CMOS device, a portion of the metal structure 344 can be formed simultaneously. Therefore, the feature structure 340 can be formed step by step while forming the CMOS element 322. In one embodiment, the metal filled in the via of the CMOS device is tungsten, and the metal layer of the CMOS device 322 is aluminum. Therefore, the metal structure 344 can be formed by stacking an aluminum layer and a tungsten layer. That is, the metal structure 344 is a multilayer structure and is composed of at least two metal materials.

在另一實施方式中,電路層320可不包含特徵結構340,微結構330周邊(如第3圖所示的區域A)填充諸如氧化矽或氮化矽等介電材料以取代特徵結構。In another embodiment, the circuit layer 320 may not include the feature structure 340, and the periphery of the microstructure 330 (such as the region A shown in FIG. 3) is filled with a dielectric material such as hafnium oxide or tantalum nitride instead of the feature structure.

在又一實施方式中,電路層320可更包括一連接墊324以及一保護層326。連接墊324電性連接主動元件322。保護層326位於電路層320的外表面,且覆蓋連接墊324。保護層326的材料可例如為氧化矽。In yet another embodiment, the circuit layer 320 can further include a connection pad 324 and a protective layer 326. The connection pad 324 is electrically connected to the active component 322. The protective layer 326 is located on the outer surface of the circuit layer 320 and covers the connection pads 324. The material of the protective layer 326 may be, for example, cerium oxide.

在步驟220中,形成凹槽312貫穿電路層320並深入基材310,如第4圖所示。凹槽312的底部312b低於基材之上表面310a,且凹槽312圍繞微結構330之周邊的一部分。在後續步驟中,凹槽312將形成第1圖繪示的貫穿空間142。以下將示例性地敘述兩種形成凹槽312的實施方式。In step 220, a recess 312 is formed through the circuit layer 320 and into the substrate 310, as shown in FIG. The bottom 312b of the recess 312 is lower than the upper surface 310a of the substrate, and the recess 312 surrounds a portion of the perimeter of the microstructure 330. In a subsequent step, the groove 312 will form a through space 142 as depicted in FIG. Two embodiments of forming the recess 312 will be exemplarily described below.

在電路層320包含有特徵結構340的實施方式中,先形成一光阻層350於電路層320及微結構330上,如第4A圖所示。光阻層350具有開口352,以露出特徵結構340。接著,以諸如反應性離子蝕刻(reactive ion etching,RIE)之乾式蝕刻法移除介電結構342,如第4B圖所示。反應性離子蝕刻僅會蝕刻諸如氧化矽及氮化矽之介電材料,不會蝕刻金屬材料。在進行反應性離子蝕刻的過程中,由於微結構330的側壁以及電路層320的側壁被金屬結構344覆蓋,所以反應性離子蝕刻不會傷害或蝕刻微結構330及電路層320的側壁,而使微結構330及電路層320的側壁得以保持原本的輪廓外觀。隨後,再以濕式蝕刻移除金屬結構344,如第4C圖所示。移除金屬結構344後,在電路層320中形成第4C圖繪示的開口B,並使開口B中的基材310暴露出來。濕式蝕刻採用的蝕刻劑對於金屬材料與氧化物材料(或氮化物)具有高的蝕刻選擇比,例如高於15:1或高於20:1或高於30:1或更高。因此,在移除金屬結構344時,幾乎不會損害微結構330及電路層320原本的側壁輪廓外觀。例如,蝕刻劑中包含硫酸和過氧化氫,硫酸與過氧化氫的重量比為約2:1。當然其他商品化的金屬蝕刻劑也可適用於本發明中。最後,在藉由例如深式反應離子蝕刻(Deep Reactive Ion Etching,DRIE)移除露出的基材310的一部分,而形成第4圖繪示的凹槽312。上述實施方式,可使微結構330的側壁與基材310上表面之間的夾角θ為約85度至約95度。此外,間隙d兩側的微結構330側壁及電路層320側壁的表面平整。因此,可以提升微機電裝置的性能以及品質穩定性。In an embodiment in which the circuit layer 320 includes the features 340, a photoresist layer 350 is formed over the circuit layer 320 and the microstructures 330, as shown in FIG. 4A. The photoresist layer 350 has an opening 352 to expose the features 340. Next, the dielectric structure 342 is removed by a dry etching method such as reactive ion etching (RIE) as shown in FIG. 4B. Reactive ion etching only etches dielectric materials such as hafnium oxide and tantalum nitride without etching the metal material. During the reactive ion etching process, since the sidewalls of the microstructure 330 and the sidewalls of the circuit layer 320 are covered by the metal structure 344, the reactive ion etching does not damage or etch the sidewalls of the microstructure 330 and the circuit layer 320. The sidewalls of the microstructures 330 and circuit layers 320 maintain their original contoured appearance. Subsequently, the metal structure 344 is removed by wet etching as shown in FIG. 4C. After the metal structure 344 is removed, the opening B shown in FIG. 4C is formed in the circuit layer 320, and the substrate 310 in the opening B is exposed. The etchant employed in the wet etching has a high etching selectivity for the metal material and the oxide material (or nitride), for example, higher than 15:1 or higher than 20:1 or higher than 30:1 or higher. Therefore, when the metal structure 344 is removed, the original sidewall profile appearance of the microstructure 330 and the circuit layer 320 is hardly impaired. For example, the etchant contains sulfuric acid and hydrogen peroxide, and the weight ratio of sulfuric acid to hydrogen peroxide is about 2:1. Of course, other commercially available metal etchants are also suitable for use in the present invention. Finally, a portion of the exposed substrate 310 is removed by, for example, Deep Reactive Ion Etching (DRIE) to form a recess 312 as shown in FIG. In the above embodiment, the angle θ between the sidewall of the microstructure 330 and the upper surface of the substrate 310 may be from about 85 degrees to about 95 degrees. In addition, the sidewalls of the microstructures 330 on both sides of the gap d and the sidewalls of the circuit layer 320 are flat. Therefore, the performance and quality stability of the microelectromechanical device can be improved.

在電路層320不包含特徵結構340的實施方式中,電路層320的區域A中為介電材料。可使用RIE移除區域A中的介電材料,而在電路層320中形成第4C圖繪示的開口B。接著,在藉由例如深式反應離子蝕刻(Deep Reactive Ion Etching,DRIE)移除露出的基材310的一部分,而形成第4圖繪示的凹槽312。In embodiments in which circuit layer 320 does not include feature structure 340, region A of circuit layer 320 is a dielectric material. The dielectric material in the region A can be removed using the RIE, and the opening B shown in FIG. 4C is formed in the circuit layer 320. Next, a portion of the exposed substrate 310 is removed by, for example, Deep Reactive Ion Etching (DRIE) to form a recess 312 as shown in FIG.

在一實施例中,上述底部312b與上表面310a間之一垂直距離d為約5 μm至約100 μm,如第4圖所示。In one embodiment, a vertical distance d between the bottom portion 312b and the upper surface 310a is from about 5 μm to about 100 μm, as shown in FIG.

在步驟230中,形成一犧牲層360填充於凹槽312內,如第5圖所示。犧牲層可例如為高分子材料所製成。舉例而言,犧牲層可為一光阻材料,經旋轉塗佈、乾燥、曝光及顯影後,填充在凹槽312中。犧牲層的材料可例如為酚醛樹脂型光阻、丙烯酸樹脂型光阻或其他有機材料。在一實施例中,犧牲層360除了填充於凹槽312中,並覆蓋微結構330的上表面332。In step 230, a sacrificial layer 360 is formed to fill the recess 312, as shown in FIG. The sacrificial layer can be made, for example, of a polymer material. For example, the sacrificial layer can be a photoresist material that is filled in the recess 312 after spin coating, drying, exposure, and development. The material of the sacrificial layer may be, for example, a phenol resin type photoresist, an acrylic type photoresist or other organic material. In an embodiment, the sacrificial layer 360 is filled in the recess 312 and covers the upper surface 332 of the microstructure 330.

在步驟240中,配置上蓋體370於電路層320上方,以覆蓋微結構330,如第6圖所示。上蓋體370用以保護最終形成的微機電裝置,上蓋體370可例如為玻璃或矽基板所製成。在一實施例中,上蓋體370可藉由一黏著層372而固定於電路層320上方。In step 240, an upper cover 370 is disposed over the circuit layer 320 to cover the microstructures 330, as shown in FIG. The upper cover 370 is used to protect the finally formed microelectromechanical device, and the upper cover 370 can be made, for example, of a glass or tantalum substrate. In an embodiment, the upper cover 370 can be fixed above the circuit layer 320 by an adhesive layer 372.

在步驟250中,由基材310的下表面310b一側移除基材310的部分,以露出犧牲層360。以下示例性地敘述兩種完成此步驟的方式。In step 250, portions of the substrate 310 are removed from the side of the lower surface 310b of the substrate 310 to expose the sacrificial layer 360. Two ways of accomplishing this step are exemplarily described below.

在一實施方式中,可先研磨基材310的下表面310b,使基材310的厚度減少至一定厚度,如第7A圖所示。例如,可將基材310的厚度研磨至約150μm。隨後,再以DRIE對基材310的下表面進行蝕刻,使基材310的下表面形成一凹陷314。凹陷314的深度足以使犧牲層360暴露出來,如第7B圖所示。In one embodiment, the lower surface 310b of the substrate 310 may be first ground to reduce the thickness of the substrate 310 to a certain thickness, as shown in FIG. 7A. For example, the thickness of the substrate 310 can be ground to about 150 [mu]m. Subsequently, the lower surface of the substrate 310 is etched by DRIE to form a recess 314 on the lower surface of the substrate 310. The depth of the recess 314 is sufficient to expose the sacrificial layer 360 as shown in Figure 7B.

在另一實施方式中,直接研磨基材310之下表面直到犧牲層露出為止。此實施方式並不使用DRIE製程。如第7C圖所示。In another embodiment, the lower surface of the substrate 310 is directly ground until the sacrificial layer is exposed. This embodiment does not use a DRIE process. As shown in Figure 7C.

習知技術中,在研磨基材的下表面時,常伴隨發生震動,而導致微結構中的細微結構因震動而受損。例如,第1圖繪示的彈性支撐件114或電極116、144的寬度通常僅為約0.1μm至約10μm,很容易因震動而受損。本發明之實施方式中,形成凹槽312後,再於凹槽312內填入犧牲層360,可以有效防止微結構因震動而受損壞。此外,填充在於凹槽312的犧牲層360,也可以避免在進行步驟240時,黏著層372或其他污染物進入凹槽312中。從而,根據本發明之實施方式,可以有效提高微機電裝置的良率。In the prior art, when the lower surface of the substrate is ground, vibration is often accompanied, and the fine structure in the microstructure is damaged by vibration. For example, the elastic support member 114 or the electrodes 116, 144 shown in Fig. 1 are typically only about 0.1 μm to about 10 μm wide and are easily damaged by vibration. In the embodiment of the present invention, after the recess 312 is formed, the sacrificial layer 360 is filled in the recess 312, which can effectively prevent the microstructure from being damaged by vibration. In addition, filling the sacrificial layer 360 in the recess 312 also prevents the adhesive layer 372 or other contaminants from entering the recess 312 when step 240 is performed. Thus, according to an embodiment of the present invention, the yield of the microelectromechanical device can be effectively improved.

在步驟260中,移除犧牲層360以釋放微結構330,如第8A及8B圖所示。第8A圖係對應第7B圖的實施方式,第8B圖係對應第7C圖的實施方式。在一實施方式中,可利用氧電漿移除犧牲層360。在其他實施方式中,可利用其他化學溶劑來移除犧牲層360。換言之,可根據犧牲層360的材料性質或製程需求來改變或調整移除犧牲層360的方法。本文中,「釋放微結構」係指使微機電裝置產生具有可相對移動的構造或部件。具體而言,移除犧牲層360後,微結構330可相對電路層320而發生位移。In step 260, the sacrificial layer 360 is removed to release the microstructures 330 as shown in Figures 8A and 8B. Fig. 8A corresponds to the embodiment of Fig. 7B, and Fig. 8B corresponds to the embodiment of Fig. 7C. In an embodiment, the sacrificial layer 360 may be removed using an oxygen plasma. In other embodiments, other chemical solvents may be utilized to remove the sacrificial layer 360. In other words, the method of removing the sacrificial layer 360 can be changed or adjusted depending on the material properties or process requirements of the sacrificial layer 360. As used herein, "releasing microstructure" means causing a microelectromechanical device to produce a structure or component that is relatively movable. In particular, after the sacrificial layer 360 is removed, the microstructures 330 can be displaced relative to the circuit layer 320.

在步驟270中,配置下蓋體380於基材310的下方,而形成微機電裝置300,如第9A及9B圖所示(第9A及9B圖分別對應第8A及8B圖的實施方式)。下蓋體380以及上蓋體370形成一封閉空間C圍繞微結構330。微結構330可在封閉空間C中發生相對位移,而使微機電裝置產生預定的功能。上蓋體370及下蓋體380用以保護微結構330,同時可防止污染物進入封閉空間C中。下蓋體380的材料可與上蓋體370相同或不同。在一實施例中,下蓋體380可藉由一黏著層382而固定於基材310的下方。In step 270, the lower cover 380 is disposed below the substrate 310 to form the microelectromechanical device 300 as shown in FIGS. 9A and 9B (the 9A and 9B drawings correspond to the embodiments of FIGS. 8A and 8B, respectively). The lower cover 380 and the upper cover 370 form a closed space C surrounding the microstructures 330. The microstructures 330 can be relatively displaced in the enclosed space C to cause the microelectromechanical device to produce a predetermined function. The upper cover 370 and the lower cover 380 serve to protect the microstructures 330 while preventing contaminants from entering the enclosed space C. The material of the lower cover 380 may be the same as or different from the upper cover 370. In an embodiment, the lower cover 380 can be fixed under the substrate 310 by an adhesive layer 382.

微機電裝置300可藉由各式的連接方式而電性連接至一外部電路或系統。微機電裝置與外部電路或系統的連接方式通常與微機電裝置的封裝形式有關。以下係以四方扁平無引腳封裝(Quad Flat Non-leaded package,QFN)為例,說明微機電裝置如何與外部電路連接。本發明所屬技術領域具通常知識者應可理解,其他的連接方式亦可適用於本發明中,因此本發明並不限於以下所揭露的方法或步驟。The MEMS device 300 can be electrically connected to an external circuit or system by various connection methods. The manner in which the MEMS device is connected to an external circuit or system is generally related to the package form of the MEMS device. The following is an example of a Quad Flat Non-leaded Package (QFN) to illustrate how a microelectromechanical device can be connected to an external circuit. It should be understood by those skilled in the art that other forms of connection are also applicable to the present invention, and thus the present invention is not limited to the methods or steps disclosed herein.

在一實施方式中,於步驟270後,移除部分的上蓋體370而露出位於連接墊326上方部分的保護層326,如第10A及10B圖所示(第10A及10B圖分別對應第9A及9B圖的實施方式)。此步驟可藉由雷射切割或機械式切割來完成,其為本領域技術人員所習知。隨後,可藉由例如RIE製程來移除露出部分的保護層326,而使保護層326下方的連接墊324露出,如第11A及11B圖所示。暴露出的連接墊324可作為微機電裝置與外部電路的連接點。In an embodiment, after step 270, a portion of the upper cover 370 is removed to expose the protective layer 326 located above the connection pad 326, as shown in FIGS. 10A and 10B (the 10A and 10B drawings respectively correspond to the 9A and The implementation of Figure 9B). This step can be accomplished by laser cutting or mechanical cutting, which is well known to those skilled in the art. Subsequently, the exposed portion of the protective layer 326 can be removed by, for example, an RIE process, and the connection pads 324 under the protective layer 326 are exposed as shown in FIGS. 11A and 11B. The exposed connection pads 324 can serve as a connection point for the microelectromechanical device to external circuitry.

雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100...微機電加速度偵測器100. . . MEMS acceleration detector

110...微結構110. . . microstructure

112...中心部112. . . Central department

114...彈性支撐件114. . . Elastic support

116...第一電極116. . . First electrode

120...半導體電路120. . . Semiconductor circuit

130...連接墊130. . . Connection pad

140...基材140. . . Substrate

142...貫穿空間142. . . Through space

144...第二電極144. . . Second electrode

200...方法200. . . method

210、220、230、240、250、260、270...步驟210, 220, 230, 240, 250, 260, 270. . . step

300...微機電裝置300. . . Microelectromechanical device

310...基材310. . . Substrate

310a...上表面310a. . . Upper surface

310b...下表面310b. . . lower surface

312...凹槽312. . . Groove

312b...底部312b. . . bottom

314...凹陷314. . . Depression

320...電路層320. . . Circuit layer

322...主動元件322. . . Active component

324...連接墊324. . . Connection pad

326...保護層326. . . The protective layer

330...微結構330. . . microstructure

332...上表面332. . . Upper surface

340...特徵結構340. . . Feature structure

342...介電結構342. . . Dielectric structure

344...金屬結構344. . . Metal structure

350...光阻層350. . . Photoresist layer

352...開口352. . . Opening

360...犧牲層360. . . Sacrificial layer

370...上蓋體370. . . Upper cover

372...黏著層372. . . Adhesive layer

380...下蓋體380. . . Lower cover

382...黏著層382. . . Adhesive layer

A...區域A. . . region

B...開口B. . . Opening

C...封閉空間C. . . Closed space

d...距離d. . . distance

θ...夾角θ. . . Angle

第1圖係繪示本發明一實施方式之微機電裝置的上視圖。1 is a top view of a microelectromechanical device according to an embodiment of the present invention.

第2圖係繪示本發明一實施方式之製造微機電裝置之方法的流程圖。2 is a flow chart showing a method of manufacturing a microelectromechanical device according to an embodiment of the present invention.

第3至11B圖係繪示本發明之製造微機電裝置的方法中各製程階段的剖面示意圖。3 to 11B are schematic cross-sectional views showing respective process stages in the method of fabricating a microelectromechanical device of the present invention.

200...方法200. . . method

210、220、230、240、250、260、270...步驟210, 220, 230, 240, 250, 260, 270. . . step

Claims (10)

一種製造微機電裝置之方法,包括:(a)形成一電路層於一基材之一上表面,其中該電路層包含一微結構以及一主動元件,且該微結構電性連接該主動元件;(b)形成一凹槽貫穿該電路層並深入該基材,使該凹槽之一底部低於該基材之上表面,其中該凹槽圍繞該微結構之周邊的一部分;(c)形成一犧牲層填充於該凹槽內;(d)配置一上蓋體於該電路層上方,以覆蓋該微結構;(e)由該基材之下表面一側移除該基材的部分,以露出該犧牲層;(f)移除該犧牲層以釋放該微結構;以及(g)配置一下蓋體於該基材下方,該下蓋體以及該上蓋體形成一封閉空間圍繞該微結構。 A method of fabricating a microelectromechanical device, comprising: (a) forming a circuit layer on an upper surface of a substrate, wherein the circuit layer comprises a microstructure and an active component, and the microstructure is electrically connected to the active component; (b) forming a recess extending through the circuit layer and into the substrate such that a bottom of the recess is lower than an upper surface of the substrate, wherein the recess surrounds a portion of the perimeter of the microstructure; (c) forming a sacrificial layer is filled in the recess; (d) an upper cover is disposed over the circuit layer to cover the microstructure; (e) a portion of the substrate is removed from a side of the lower surface of the substrate to Exposing the sacrificial layer; (f) removing the sacrificial layer to release the microstructure; and (g) disposing the cover under the substrate, the lower cover and the upper cover forming a closed space surrounding the microstructure. 如請求項1所述之方法,其中步驟(a)之該電路層更包括一連接墊以及一保護層,其中該連接墊電性連接該主動元件,該保護層位於該電路層之一外表面,且覆蓋該連接墊。 The method of claim 1, wherein the circuit layer of the step (a) further comprises a connection pad and a protective layer, wherein the connection pad is electrically connected to the active component, and the protective layer is located on an outer surface of the circuit layer And covering the connection pad. 如請求項2所述之方法,於步驟(g)後更包括:(h)移除該上蓋體之部分,以露出位於該連接墊上方之該保護層的部分;以及 (i)移除該保護層之該部分,以露出該連接墊。 The method of claim 2, after the step (g), further comprising: (h) removing a portion of the upper cover to expose a portion of the protective layer above the connection pad; (i) removing the portion of the protective layer to expose the connection pad. 如請求項1所述之方法,其中步驟(a)之該主動元件為一互補式金屬氧化物半導體元件或雙極互補式金屬氧化物半導體元件。 The method of claim 1, wherein the active component of step (a) is a complementary metal oxide semiconductor device or a bipolar complementary metal oxide semiconductor device. 如請求項1所述之方法,其中步驟(b)之該底部與該上表面間之一垂直距離為約5μm至約100μm。 The method of claim 1, wherein a vertical distance between the bottom of the step (b) and the upper surface is from about 5 μm to about 100 μm. 如請求項1所述之方法,其中步驟(c)之該犧牲層為一高分子材料,且覆蓋該微結構之一上表面。 The method of claim 1, wherein the sacrificial layer of the step (c) is a polymer material and covers an upper surface of the microstructure. 如請求項1所述之方法,其中步驟(e)包含:研磨該基材之下表面,以露出該犧牲層。 The method of claim 1, wherein the step (e) comprises: grinding a lower surface of the substrate to expose the sacrificial layer. 如請求項1所述之方法,其中步驟(e)包含:研磨該基材之下表面;以及以深式反應離子蝕刻該經研磨之基材,以露出該犧牲層。 The method of claim 1, wherein the step (e) comprises: grinding the lower surface of the substrate; and etching the ground substrate by deep reactive ion etching to expose the sacrificial layer. 如請求項1所述之方法,其中步驟(f)係以一氧電漿移除該犧牲層。 The method of claim 1, wherein the step (f) removes the sacrificial layer with an oxygen plasma. 一種製造微機電裝置之方法,包括: 形成一電路層於一基材之一上表面,該電路層包含一特徵結構以及一微結構,其中該特徵結構圍繞該微結構之周邊的一部分並貫穿該電路層,其中該特徵結構包含:一介電結構,貫穿該電路層;以及一金屬結構,貫穿該電路層並環繞該介電結構;移除該特徵結構,以露出該基材,其中移除該特徵結構包含依序以乾式蝕刻移除該介電結構以及濕式蝕刻移除該金屬結構;移除該露出基材之一部分,以形成一凹槽,其中該凹槽貫穿該電路層,並具有一底部低於該基材之上表面,且該凹槽圍繞該微結構周邊的該部分;形成一犧牲層填充於該凹槽內;配置一上蓋體於該電路層上方,以覆蓋該微結構;由該基材之下表面一側移除該基材的部分,以露出該犧牲層;移除該犧牲層以釋放該微結構;以及配置一下蓋體於該基材下方,該下蓋體以及該上蓋體形成一封閉空間圍繞該微結構。A method of fabricating a microelectromechanical device, comprising: Forming a circuit layer on an upper surface of a substrate, the circuit layer comprising a feature structure and a microstructure, wherein the feature structure surrounds a portion of the periphery of the microstructure and penetrates the circuit layer, wherein the feature structure comprises: a dielectric structure extending through the circuit layer; and a metal structure extending through the circuit layer and surrounding the dielectric structure; removing the feature to expose the substrate, wherein removing the feature comprises sequentially etching dry Removing the metal structure in addition to the dielectric structure and wet etching; removing a portion of the exposed substrate to form a recess, wherein the recess extends through the circuit layer and has a bottom lower than the substrate a surface, and the groove surrounds the portion of the periphery of the microstructure; a sacrificial layer is formed in the recess; an upper cover is disposed over the circuit layer to cover the microstructure; and a lower surface of the substrate is Removing a portion of the substrate to expose the sacrificial layer; removing the sacrificial layer to release the microstructure; and disposing a cover under the substrate, the lower cover and the upper cover forming a closure The microstructure around the room.
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